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Wed, 12 Mar 2025 04:56:13 -0700 (PDT) From: Akihiko Odaki Date: Wed, 12 Mar 2025 20:55:55 +0900 Subject: [PATCH v3 1/6] KVM: arm64: PMU: Set raw values from user to PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250312-pmc-v3-1-0411cab5dc3d@daynix.com> References: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> In-Reply-To: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki , stable@vger.kernel.org X-Mailer: b4 0.15-dev-edae6 Commit a45f41d754e0 ("KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}") changed KVM_SET_ONE_REG to update the mentioned registers in a way matching with the behavior of guest register writes. This is a breaking change of a UAPI though the new semantics looks cleaner and VMMs are not prepared for this. Firecracker, QEMU, and crosvm perform migration by listing registers with KVM_GET_REG_LIST, getting their values with KVM_GET_ONE_REG and setting them with KVM_SET_ONE_REG. This algorithm assumes KVM_SET_ONE_REG restores the values retrieved with KVM_GET_ONE_REG without any alteration. However, bit operations added by the earlier commit do not preserve the values retried with KVM_GET_ONE_REG and potentially break migration. Remove the bit operations that alter the values retrieved with KVM_GET_ONE_REG. Cc: stable@vger.kernel.org Fixes: a45f41d754e0 ("KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CL= R}, PMOVS{SET,CLR}") Signed-off-by: Akihiko Odaki Acked-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 42791971f758..0a2ce931a946 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1126,26 +1126,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu= , struct sys_reg_params *p, =20 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, = u64 val) { - bool set; - - val &=3D kvm_pmu_valid_counter_mask(vcpu); - - switch (r->reg) { - case PMOVSSET_EL0: - /* CRm[1] being set indicates a SET register, and CLR otherwise */ - set =3D r->CRm & 2; - break; - default: - /* Op2[0] being set indicates a SET register, and CLR otherwise */ - set =3D r->Op2 & 1; - break; - } - - if (set) - __vcpu_sys_reg(vcpu, r->reg) |=3D val; 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Wed, 12 Mar 2025 04:56:18 -0700 (PDT) Received: from localhost ([157.82.205.237]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-736a6e5c13asm10966593b3a.157.2025.03.12.04.56.15 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 04:56:18 -0700 (PDT) From: Akihiko Odaki Date: Wed, 12 Mar 2025 20:55:56 +0900 Subject: [PATCH v3 2/6] KVM: arm64: PMU: Assume PMU presence in pmu-emul.c Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250312-pmc-v3-2-0411cab5dc3d@daynix.com> References: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> In-Reply-To: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.15-dev-edae6 Many functions in pmu-emul.c checks kvm_vcpu_has_pmu(vcpu). A favorable interpretation is defensive programming, but it also has downsides: - It is confusing as it implies these functions are called without PMU although most of them are called only when a PMU is present. - It makes semantics of functions fuzzy. For example, calling kvm_pmu_disable_counter_mask() without PMU may result in no-op as there are no enabled counters, but it's unclear what kvm_pmu_get_counter_value() returns when there is no PMU. - It allows callers without checking kvm_vcpu_has_pmu(vcpu), but it is often wrong to call these functions without PMU. - It is error-prone to duplicate kvm_vcpu_has_pmu(vcpu) checks into multiple functions. Many functions are called for system registers, and the system register infrastructure already employs less error-prone, comprehensive checks. Check kvm_vcpu_has_pmu(vcpu) in callers of these functions instead, and remove the obsolete checks from pmu-emul.c. Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/arm.c | 8 +++++--- arch/arm64/kvm/guest.c | 12 ++++++++++++ arch/arm64/kvm/pmu-emul.c | 34 ++-------------------------------- arch/arm64/kvm/sys_regs.c | 6 ++++-- 4 files changed, 23 insertions(+), 37 deletions(-) diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c index f66ce098f03b..e375468a2217 100644 --- a/arch/arm64/kvm/arm.c +++ b/arch/arm64/kvm/arm.c @@ -834,9 +834,11 @@ int kvm_arch_vcpu_run_pid_change(struct kvm_vcpu *vcpu) if (ret) return ret; =20 - ret =3D kvm_arm_pmu_v3_enable(vcpu); - if (ret) - return ret; + if (kvm_vcpu_has_pmu(vcpu)) { + ret =3D kvm_arm_pmu_v3_enable(vcpu); + if (ret) + return ret; + } =20 if (is_protected_kvm_enabled()) { ret =3D pkvm_create_hyp_vm(kvm); diff --git a/arch/arm64/kvm/guest.c b/arch/arm64/kvm/guest.c index 962f985977c2..fc09eec3fd94 100644 --- a/arch/arm64/kvm/guest.c +++ b/arch/arm64/kvm/guest.c @@ -951,6 +951,10 @@ int kvm_arm_vcpu_arch_set_attr(struct kvm_vcpu *vcpu, =20 switch (attr->group) { case KVM_ARM_VCPU_PMU_V3_CTRL: + if (!kvm_vcpu_has_pmu(vcpu)) { + ret =3D -ENODEV; + break; + } mutex_lock(&vcpu->kvm->arch.config_lock); ret =3D kvm_arm_pmu_v3_set_attr(vcpu, attr); mutex_unlock(&vcpu->kvm->arch.config_lock); @@ -976,6 +980,10 @@ int kvm_arm_vcpu_arch_get_attr(struct kvm_vcpu *vcpu, =20 switch (attr->group) { case KVM_ARM_VCPU_PMU_V3_CTRL: + if (!kvm_vcpu_has_pmu(vcpu)) { + ret =3D -ENODEV; + break; + } ret =3D kvm_arm_pmu_v3_get_attr(vcpu, attr); break; case KVM_ARM_VCPU_TIMER_CTRL: @@ -999,6 +1007,10 @@ int kvm_arm_vcpu_arch_has_attr(struct kvm_vcpu *vcpu, =20 switch (attr->group) { case KVM_ARM_VCPU_PMU_V3_CTRL: + if (!kvm_vcpu_has_pmu(vcpu)) { + ret =3D -ENXIO; + break; + } ret =3D kvm_arm_pmu_v3_has_attr(vcpu, attr); break; case KVM_ARM_VCPU_TIMER_CTRL: diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index e3e82b66e226..3e5bf414447f 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -144,9 +144,6 @@ static u64 kvm_pmu_get_pmc_value(struct kvm_pmc *pmc) */ u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx) { - if (!kvm_vcpu_has_pmu(vcpu)) - return 0; - return kvm_pmu_get_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, select_idx)); } =20 @@ -185,9 +182,6 @@ static void kvm_pmu_set_pmc_value(struct kvm_pmc *pmc, = u64 val, bool force) */ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 = val) { - if (!kvm_vcpu_has_pmu(vcpu)) - return; - kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, select_idx), val, false); } =20 @@ -289,8 +283,6 @@ u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu) void kvm_pmu_enable_counter_mask(struct kvm_vcpu *vcpu, u64 val) { int i; - if (!kvm_vcpu_has_pmu(vcpu)) - return; =20 if (!(kvm_vcpu_read_pmcr(vcpu) & ARMV8_PMU_PMCR_E) || !val) return; @@ -324,7 +316,7 @@ void kvm_pmu_disable_counter_mask(struct kvm_vcpu *vcpu= , u64 val) { int i; =20 - if (!kvm_vcpu_has_pmu(vcpu) || !val) + if (!val) return; =20 for (i =3D 0; i < KVM_ARMV8_PMU_MAX_COUNTERS; i++) { @@ -357,9 +349,6 @@ static void kvm_pmu_update_state(struct kvm_vcpu *vcpu) struct kvm_pmu *pmu =3D &vcpu->arch.pmu; bool overflow; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return; - overflow =3D !!kvm_pmu_overflow_status(vcpu); if (pmu->irq_level =3D=3D overflow) return; @@ -555,9 +544,6 @@ void kvm_pmu_handle_pmcr(struct kvm_vcpu *vcpu, u64 val) { int i; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return; - /* Fixup PMCR_EL0 to reconcile the PMU version and the LP bit */ if (!kvm_has_feat(vcpu->kvm, ID_AA64DFR0_EL1, PMUVer, V3P5)) val &=3D ~ARMV8_PMU_PMCR_LP; @@ -696,9 +682,6 @@ void kvm_pmu_set_counter_event_type(struct kvm_vcpu *vc= pu, u64 data, struct kvm_pmc *pmc =3D kvm_vcpu_idx_to_pmc(vcpu, select_idx); u64 reg; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return; - reg =3D counter_index_to_evtreg(pmc->idx); __vcpu_sys_reg(vcpu, reg) =3D data & kvm_pmu_evtyper_mask(vcpu->kvm); =20 @@ -804,9 +787,6 @@ u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmce= id1) u64 val, mask =3D 0; int base, i, nr_events; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return 0; - if (!pmceid1) { val =3D compute_pmceid0(cpu_pmu); base =3D 0; @@ -847,9 +827,6 @@ void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) =20 int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) { - if (!kvm_vcpu_has_pmu(vcpu)) - return 0; - if (!vcpu->arch.pmu.created) return -EINVAL; =20 @@ -1022,9 +999,6 @@ int kvm_arm_pmu_v3_set_attr(struct kvm_vcpu *vcpu, str= uct kvm_device_attr *attr) =20 lockdep_assert_held(&kvm->arch.config_lock); =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return -ENODEV; - if (vcpu->arch.pmu.created) return -EBUSY; =20 @@ -1129,9 +1103,6 @@ int kvm_arm_pmu_v3_get_attr(struct kvm_vcpu *vcpu, st= ruct kvm_device_attr *attr) if (!irqchip_in_kernel(vcpu->kvm)) return -EINVAL; =20 - if (!kvm_vcpu_has_pmu(vcpu)) - return -ENODEV; - if (!kvm_arm_pmu_irq_initialized(vcpu)) return -ENXIO; =20 @@ -1150,8 +1121,7 @@ int kvm_arm_pmu_v3_has_attr(struct kvm_vcpu *vcpu, st= ruct kvm_device_attr *attr) case KVM_ARM_VCPU_PMU_V3_INIT: case KVM_ARM_VCPU_PMU_V3_FILTER: case KVM_ARM_VCPU_PMU_V3_SET_PMU: - if (kvm_vcpu_has_pmu(vcpu)) - return 0; + return 0; } =20 return -ENXIO; diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 0a2ce931a946..6e75557bea1d 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1784,12 +1784,14 @@ static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcp= u, static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd) { - u8 perfmon =3D pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit()); 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Wed, 12 Mar 2025 04:56:24 -0700 (PDT) Received: from localhost ([157.82.205.237]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-736b7bb0bf2sm9336341b3a.42.2025.03.12.04.56.21 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 04:56:23 -0700 (PDT) From: Akihiko Odaki Date: Wed, 12 Mar 2025 20:55:57 +0900 Subject: [PATCH v3 3/6] KVM: arm64: PMU: Fix SET_ONE_REG for vPMC regs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250312-pmc-v3-3-0411cab5dc3d@daynix.com> References: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> In-Reply-To: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.15-dev-edae6 Reload the perf event when setting the vPMU counter (vPMC) registers (PMCCNTR_EL0 and PMEVCNTR_EL0). This is a change corresponding to commit 9228b26194d1 ("KVM: arm64: PMU: Fix GET_ONE_REG for vPMC regs to return the current value") but for SET_ONE_REG. Values of vPMC registers are saved in sysreg files on certain occasions. These saved values don't represent the current values of the vPMC registers if the perf events for the vPMCs count events after the save. The current values of those registers are the sum of the sysreg file value and the current perf event counter value. But, when userspace writes those registers (using KVM_SET_ONE_REG), KVM only updates the sysreg file value and leaves the current perf event counter value as is. It is also important to keep the correct state even if userspace writes them after first run, specifically when debugging Windows on QEMU with GDB; QEMU tries to write back all visible registers when resuming the VM execution with GDB, corrupting the PMU state. Windows always uses the PMU so this can cause adverse effects on that particular OS. Fix this by releasing the current perf event and trigger recreating one with KVM_REQ_RELOAD_PMU. Fixes: 051ff581ce70 ("arm64: KVM: Add access handler for event counter regi= ster") Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 13 +++++++++++++ arch/arm64/kvm/sys_regs.c | 20 +++++++++++++++++++- include/kvm/arm_pmu.h | 1 + 3 files changed, 33 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 3e5bf414447f..1cfe53b6353e 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -185,6 +185,19 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, = u64 select_idx, u64 val) kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, select_idx), val, false); } =20 +/** + * kvm_pmu_set_counter_value_user - set PMU counter value from user + * @vcpu: The vcpu pointer + * @select_idx: The counter index + * @val: The counter value + */ +void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, u64 select_idx,= u64 val) +{ + kvm_pmu_release_perf_event(kvm_vcpu_idx_to_pmc(vcpu, select_idx)); + __vcpu_sys_reg(vcpu, counter_index_to_reg(select_idx)) =3D val; + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); +} + /** * kvm_pmu_release_perf_event - remove the perf event * @pmc: The PMU counter pointer diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 6e75557bea1d..26182cae4ac7 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1035,6 +1035,22 @@ static int get_pmu_evcntr(struct kvm_vcpu *vcpu, con= st struct sys_reg_desc *r, return 0; } =20 +static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc= *r, + u64 val) +{ + u64 idx; + + if (r->CRn =3D=3D 9 && r->CRm =3D=3D 13 && r->Op2 =3D=3D 0) + /* PMCCNTR_EL0 */ + idx =3D ARMV8_PMU_CYCLE_IDX; + else + /* PMEVCNTRn_EL0 */ + idx =3D ((r->CRm & 3) << 3) | (r->Op2 & 7); + + kvm_pmu_set_counter_value_user(vcpu, idx, val); + return 0; +} + static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -1309,6 +1325,7 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const stru= ct sys_reg_desc *r, #define PMU_PMEVCNTR_EL0(n) \ { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ .reset =3D reset_pmevcntr, .get_user =3D get_pmu_evcntr, \ + .set_user =3D set_pmu_evcntr, \ .access =3D access_pmu_evcntr, .reg =3D (PMEVCNTR0_EL0 + n), } =20 /* Macro to expand the PMEVTYPERn_EL0 register */ @@ -2665,7 +2682,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { .access =3D access_pmceid, .reset =3D NULL }, { PMU_SYS_REG(PMCCNTR_EL0), .access =3D access_pmu_evcntr, .reset =3D reset_unknown, - .reg =3D PMCCNTR_EL0, .get_user =3D get_pmu_evcntr}, + .reg =3D PMCCNTR_EL0, .get_user =3D get_pmu_evcntr, + .set_user =3D set_pmu_evcntr }, { PMU_SYS_REG(PMXEVTYPER_EL0), .access =3D access_pmu_evtyper, .reset =3D NULL }, { PMU_SYS_REG(PMXEVCNTR_EL0), diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 28b380ad8dfa..9c062756ebfa 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -41,6 +41,7 @@ bool kvm_supports_guest_pmuv3(void); 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Wed, 12 Mar 2025 04:56:28 -0700 (PDT) Received: from localhost ([157.82.205.237]) by smtp.gmail.com with UTF8SMTPSA id d9443c01a7336-22410aa457csm114113705ad.212.2025.03.12.04.56.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 04:56:28 -0700 (PDT) From: Akihiko Odaki Date: Wed, 12 Mar 2025 20:55:58 +0900 Subject: [PATCH v3 4/6] KVM: arm64: PMU: Reload when user modifies registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250312-pmc-v3-4-0411cab5dc3d@daynix.com> References: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> In-Reply-To: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.15-dev-edae6 Commit d0c94c49792c ("KVM: arm64: Restore PMU configuration on first run") added the code to reload the PMU configuration on first run. It is also important to keep the correct state even if system registers are modified after first run, specifically when debugging Windows on QEMU with GDB; QEMU tries to write back all visible registers when resuming the VM execution with GDB, corrupting the PMU state. Windows always uses the PMU so this can cause adverse effects on that particular OS. The usual register writes are already handled independently, but register writes from userspace and ones for reset are not covered. Trigger the code to reload the PMU configuration in these code paths instead so that PMU configuration changes made by users will be applied also after the first run. Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 3 --- arch/arm64/kvm/sys_regs.c | 6 ++++++ 2 files changed, 6 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 1cfe53b6353e..78cfa8b0964d 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -862,9 +862,6 @@ int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) return -EINVAL; } =20 - /* One-off reload of the PMU on first run */ - kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); - return 0; } =20 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 26182cae4ac7..307ce37d0434 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1143,6 +1143,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu,= struct sys_reg_params *p, static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, = u64 val) { __vcpu_sys_reg(vcpu, r->reg) =3D val & kvm_pmu_valid_counter_mask(vcpu); + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 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Wed, 12 Mar 2025 04:56:33 -0700 (PDT) Received: from localhost ([157.82.205.237]) by smtp.gmail.com with UTF8SMTPSA id 41be03b00d2f7-af2f01909a6sm9911068a12.7.2025.03.12.04.56.30 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 04:56:32 -0700 (PDT) From: Akihiko Odaki Date: Wed, 12 Mar 2025 20:55:59 +0900 Subject: [PATCH v3 5/6] KVM: arm64: PMU: Call kvm_pmu_handle_pmcr() after masking PMCNTENSET_EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250312-pmc-v3-5-0411cab5dc3d@daynix.com> References: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> In-Reply-To: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.15-dev-edae6 kvm_pmu_handle_pmcr() expects PMCNTENSET_EL0 only contains valid counters. Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 78cfa8b0964d..2d19c6048091 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -831,11 +831,11 @@ void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) { u64 mask =3D kvm_pmu_valid_counter_mask(vcpu); =20 - kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu)); - __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &=3D mask; __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &=3D mask; __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &=3D mask; + + kvm_pmu_handle_pmcr(vcpu, kvm_vcpu_read_pmcr(vcpu)); } =20 int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) --=20 2.48.1 From nobody Tue Dec 16 11:06:25 2025 Received: from mail-pl1-f169.google.com (mail-pl1-f169.google.com [209.85.214.169]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 358D024501E for ; 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Wed, 12 Mar 2025 04:56:37 -0700 (PDT) Received: from localhost ([157.82.205.237]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-736d4f20913sm6410407b3a.13.2025.03.12.04.56.34 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 12 Mar 2025 04:56:37 -0700 (PDT) From: Akihiko Odaki Date: Wed, 12 Mar 2025 20:56:00 +0900 Subject: [PATCH v3 6/6] KVM: arm64: Reload PMCNTENSET_EL0 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250312-pmc-v3-6-0411cab5dc3d@daynix.com> References: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> In-Reply-To: <20250312-pmc-v3-0-0411cab5dc3d@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.15-dev-edae6 Disable counters that are no longer included in PMCNTENSET_EL0. It is not necessary to enable counters included in PMCNTENSET_EL0 because kvm_pmu_handle_pmcr() does so if appropriate. Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 2d19c6048091..b14655dda6db 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -831,6 +831,8 @@ void kvm_vcpu_reload_pmu(struct kvm_vcpu *vcpu) { u64 mask =3D kvm_pmu_valid_counter_mask(vcpu); =20 + kvm_pmu_disable_counter_mask(vcpu, ~__vcpu_sys_reg(vcpu, PMCNTENSET_EL0)); + __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &=3D mask; __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &=3D mask; __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &=3D mask; --=20 2.48.1