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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.49.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:49:44 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 01/11] rust: error: Add EOVERFLOW Date: Tue, 11 Mar 2025 19:47:57 +0200 Message-ID: <20250311174930.2348813-2-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Trivial addition for missing EOVERFLOW error. This is used by a subsequent patch that might require returning EOVERFLOW as a result of `checked_mul`. Reviewed-by: Alice Ryhl Reviewed-by: Andreas Hindborg Signed-off-by: Abdiel Janulgue --- rust/kernel/error.rs | 1 + 1 file changed, 1 insertion(+) diff --git a/rust/kernel/error.rs b/rust/kernel/error.rs index f6ecf09cb65f..1e510181432c 100644 --- a/rust/kernel/error.rs +++ b/rust/kernel/error.rs @@ -64,6 +64,7 @@ macro_rules! declare_err { declare_err!(EPIPE, "Broken pipe."); declare_err!(EDOM, "Math argument out of domain of func."); declare_err!(ERANGE, "Math result not representable."); + declare_err!(EOVERFLOW, "Value too large for defined data type."); declare_err!(ERESTARTSYS, "Restart the system call."); declare_err!(ERESTARTNOINTR, "System call was interrupted by a signal = and will be restarted."); declare_err!(ERESTARTNOHAND, "Restart if no handler."); --=20 2.43.0 From nobody Sun Feb 8 17:47:44 2026 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 76F2F262D11; Tue, 11 Mar 2025 17:49:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715391; cv=none; b=tQjc9ESPAPny/qOgN0h6iae7I5xYI08wUBnXJp8GFsjCFierp6m2lORwYzuR83v037A3u0nWC4Xhefl6H3yIVHQWuEm2/1FNtmtMEzEoSwcFFXtpa+f2oU2YoM+MTbF6wvc/Sci49jFEukSyIDDImZW7bUwSrM50kTSK8+57Sfo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715391; c=relaxed/simple; bh=jd3pjpbP3u0XG/zQ4FkolYGa8M3aLwzwOJdwsZPxFh0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GcToMNEvE1eWZMLZtZLQOiX9fof1ENWAZLHxAjtFXHHOgS5vPEFMJ+WX/eTZSwC9FNOjkQcX/JwLxvLVH8sUXjv99F7QWdF/O9Aj1QydmePfDrD4QsM1SoczGcz40oRN0+xltCWxtVPLdiSyXo8U9LOtkviEW3l7KA0+SqCSFvc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=WPDJtrVe; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="WPDJtrVe" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-54954fa61c9so6647078e87.1; Tue, 11 Mar 2025 10:49:49 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1741715387; x=1742320187; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=26ftVVDMFL7fcXox6xAbGSeaOBehXNbtEaGLInHmYME=; b=WPDJtrVeUuNwwmjqPoQth3bTig28Q0wkWZA4vSHEH9UIUu2eZVgKE5JU8S6ZAzWaPV 8NHj4W+CZ/5TLAVWmfWZ46hm7M6WY5rDzFUQrCMKFZYsfZqkNBg/lxKjYShyKWRptnCm t6av4U3C4HVrHPqsJUkbopTnP9Cd/3+BUipDC6JAleBHyRqOq3n89YmrcJ2/hRTfyKC5 tvsbwi1wTqy1wng4LVPNJmvRnQ9QyiZ8wZQgt5g3tS7L+ERHEIRBlG6ARLfb17eBVvPS ot+Kp64mnPU7gVxV44FmJfV60lSuaPebtdFAug+jX48o1H0lU6Cn6M13oJDpEOt93afG wl3w== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741715387; x=1742320187; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=26ftVVDMFL7fcXox6xAbGSeaOBehXNbtEaGLInHmYME=; b=By2evI0VlnW/TJsJOiye0EsTyrc5XY2t9Q93g7F74e8rvODDOJ6qGOCt/iVRLIsm5F XD1U3Dow/cniWBWqjhY+WiN8N66x99v0gRi0vel0K2IZHJ90ndn7CjI3e8u9V3kdYcDF ByEVo1r57EbV+Tj7Hyx0m1+iZVEpx8/jpvXcBiVI+To3JXyVslfxzqQqZWXY565hClum lB5nTSSE7rrDkvZZH78rgnIfP5jGI9bRxHoGhC16KDHf3EtEsUSDIfAOqRXpE3egC4lK ULO6ylIhbk2444e6MtjnnOJfvfoo6ZgTrH2VCLQg/uAfNfHvkXapTy6jdf30ENP0jAgX owAw== X-Forwarded-Encrypted: i=1; AJvYcCXel/MZwSnXtgUwAqdKeIIvaOQ0SQKpOnrXpeeE8C+ST97qXf8sVq9Adid91e7bEF0272rHQZrneuF2RYU=@vger.kernel.org X-Gm-Message-State: AOJu0YzL5V9+CR8/MHHBOt3oepmD0RSn4BK9mhXodZ+lRyT4vY1aa5Hv pWGxCBLwnkU7tNxDvO+haNEqpaMXFpO9WQdSOOifXsK/njzspLZ7vVTBEw== X-Gm-Gg: ASbGnctY0b54pOrW76y95cLCq76tc/aqa0IzPlZd+kOHmVplkhG+p0aiVHPQVV4WQbd OCn74JbY+24UYcwnv6Fnt/dfrvsQyzAu74KwTdsG3c+5MOf+4PvTt/8PKgT73mcryoq/62eJy+o RHhkG0PdvI/oCTq72LQ5la665eFNOUetH/Vv5YnPRkQnAKmj5P05JMHy7iYVwrj0pY226GkDGSG 2YbuZvhXb0t5TWFBSLzTk/s7i0PeyuTVstR1tF9/gd27FxkGAl1Y2yJcE7iYOUarpy4U8+IuIE0 gBgHQjmUqLrWIMWws9r5BzqQwTwNRCI+ZS5B/jzJiMS/u+/Wc2g5OYiLFqolgq06N6yMujA8BOg VXzERcr9h3K8r9QZBzt5QQQ== X-Google-Smtp-Source: AGHT+IHqacWmh9GZ5CrLIUXFLsz7r4MoxfnCF7V5Kr8h01h0vocdacx2/ekktKa08qJT/2OUlLaXdA== X-Received: by 2002:a05:6512:1598:b0:549:8d67:c48e with SMTP id 2adb3069b0e04-54990e673a2mr5712430e87.29.1741715387053; Tue, 11 Mar 2025 10:49:47 -0700 (PDT) Received: from abj-NUC9VXQNX.. (dsl-hkibng22-54f8dc-251.dhcp.inet.fi. [84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.49.45 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:49:45 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 02/11] rust: add dma coherent allocator abstraction. Date: Tue, 11 Mar 2025 19:47:58 +0200 Message-ID: <20250311174930.2348813-3-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a simple dma coherent allocator rust abstraction. Based on Andreas Hindborg's dma abstractions from the rnvme driver, which was also based on earlier work by Wedson Almeida Filho. Reviewed-by: Alice Ryhl Signed-off-by: Abdiel Janulgue --- rust/bindings/bindings_helper.h | 1 + rust/kernel/dma.rs | 369 ++++++++++++++++++++++++++++++++ rust/kernel/lib.rs | 1 + 3 files changed, 371 insertions(+) create mode 100644 rust/kernel/dma.rs diff --git a/rust/bindings/bindings_helper.h b/rust/bindings/bindings_helpe= r.h index ae39fc18a8bf..ccb988340df6 100644 --- a/rust/bindings/bindings_helper.h +++ b/rust/bindings/bindings_helper.h @@ -12,6 +12,7 @@ #include #include #include +#include #include #include #include diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs new file mode 100644 index 000000000000..325b00fe7871 --- /dev/null +++ b/rust/kernel/dma.rs @@ -0,0 +1,369 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Direct memory access (DMA). +//! +//! C header: [`include/linux/dma-mapping.h`](srctree/include/linux/dma-ma= pping.h) + +use crate::{ + bindings, build_assert, + device::Device, + error::code::*, + error::Result, + transmute::{AsBytes, FromBytes}, + types::ARef, +}; + +/// Possible attributes associated with a DMA mapping. +/// +/// They can be combined with the operators `|`, `&`, and `!`. +/// +/// Values can be used from the [`attrs`] module. +/// +/// # Examples +/// +/// ``` +/// use kernel::device::Device; +/// use kernel::dma::{attrs::*, CoherentAllocation}; +/// +/// # fn test(dev: &Device) -> Result { +/// let attribs =3D DMA_ATTR_FORCE_CONTIGUOUS | DMA_ATTR_NO_WARN; +/// let c: CoherentAllocation =3D +/// CoherentAllocation::alloc_attrs(dev, 4, GFP_KERNEL, attribs)?; +/// # Ok::<(), Error>(()) } +/// ``` +#[derive(Clone, Copy, PartialEq)] +#[repr(transparent)] +pub struct Attrs(u32); + +impl Attrs { + /// Get the raw representation of this attribute. + pub(crate) fn as_raw(self) -> crate::ffi::c_ulong { + self.0 as _ + } + + /// Check whether `flags` is contained in `self`. + pub fn contains(self, flags: Attrs) -> bool { + (self & flags) =3D=3D flags + } +} + +impl core::ops::BitOr for Attrs { + type Output =3D Self; + fn bitor(self, rhs: Self) -> Self::Output { + Self(self.0 | rhs.0) + } +} + +impl core::ops::BitAnd for Attrs { + type Output =3D Self; + fn bitand(self, rhs: Self) -> Self::Output { + Self(self.0 & rhs.0) + } +} + +impl core::ops::Not for Attrs { + type Output =3D Self; + fn not(self) -> Self::Output { + Self(!self.0) + } +} + +/// DMA mapping attributes. +pub mod attrs { + use super::Attrs; + + /// Specifies that reads and writes to the mapping may be weakly order= ed, that is that reads + /// and writes may pass each other. + pub const DMA_ATTR_WEAK_ORDERING: Attrs =3D Attrs(bindings::DMA_ATTR_W= EAK_ORDERING); + + /// Specifies that writes to the mapping may be buffered to improve pe= rformance. + pub const DMA_ATTR_WRITE_COMBINE: Attrs =3D Attrs(bindings::DMA_ATTR_W= RITE_COMBINE); + + /// Lets the platform to avoid creating a kernel virtual mapping for t= he allocated buffer. + pub const DMA_ATTR_NO_KERNEL_MAPPING: Attrs =3D Attrs(bindings::DMA_AT= TR_NO_KERNEL_MAPPING); + + /// Allows platform code to skip synchronization of the CPU cache for = the given buffer assuming + /// that it has been already transferred to 'device' domain. + pub const DMA_ATTR_SKIP_CPU_SYNC: Attrs =3D Attrs(bindings::DMA_ATTR_S= KIP_CPU_SYNC); + + /// Forces contiguous allocation of the buffer in physical memory. + pub const DMA_ATTR_FORCE_CONTIGUOUS: Attrs =3D Attrs(bindings::DMA_ATT= R_FORCE_CONTIGUOUS); + + /// This is a hint to the DMA-mapping subsystem that it's probably not= worth the time to try + /// to allocate memory to in a way that gives better TLB efficiency. + pub const DMA_ATTR_ALLOC_SINGLE_PAGES: Attrs =3D Attrs(bindings::DMA_A= TTR_ALLOC_SINGLE_PAGES); + + /// This tells the DMA-mapping subsystem to suppress allocation failur= e reports (similarly to + /// __GFP_NOWARN). + pub const DMA_ATTR_NO_WARN: Attrs =3D Attrs(bindings::DMA_ATTR_NO_WARN= ); + + /// Used to indicate that the buffer is fully accessible at an elevate= d privilege level (and + /// ideally inaccessible or at least read-only at lesser-privileged le= vels). + pub const DMA_ATTR_PRIVILEGED: Attrs =3D Attrs(bindings::DMA_ATTR_PRIV= ILEGED); +} + +/// An abstraction of the `dma_alloc_coherent` API. +/// +/// This is an abstraction around the `dma_alloc_coherent` API which is us= ed to allocate and map +/// large consistent DMA regions. +/// +/// A [`CoherentAllocation`] instance contains a pointer to the allocated = region (in the +/// processor's virtual address space) and the device address which can be= given to the device +/// as the DMA address base of the region. The region is released once [`C= oherentAllocation`] +/// is dropped. +/// +/// # Invariants +/// +/// For the lifetime of an instance of [`CoherentAllocation`], the `cpu_ad= dr` is a valid pointer +/// to an allocated region of consistent memory and `dma_handle` is the DM= A address base of +/// the region. +// TODO +// +// DMA allocations potentially carry device resources (e.g.IOMMU mappings)= , hence for soundness +// reasons DMA allocation would need to be embedded in a `Devres` containe= r, in order to ensure +// that device resources can never survive device unbind. +// +// However, it is neither desirable nor necessary to protect the allocated= memory of the DMA +// allocation from surviving device unbind; it would require RCU read side= critical sections to +// access the memory, which may require subsequent unnecessary copies. +// +// Hence, find a way to revoke the device resources of a `CoherentAllocati= on`, but not the +// entire `CoherentAllocation` including the allocated memory itself. +pub struct CoherentAllocation { + dev: ARef, + dma_handle: bindings::dma_addr_t, + count: usize, + cpu_addr: *mut T, + dma_attrs: Attrs, +} + +impl CoherentAllocation { + /// Allocates a region of `size_of:: * count` of consistent memory. + /// + /// # Examples + /// + /// ``` + /// use kernel::device::Device; + /// use kernel::dma::{attrs::*, CoherentAllocation}; + /// + /// # fn test(dev: &Device) -> Result { + /// let c: CoherentAllocation =3D + /// CoherentAllocation::alloc_attrs(dev, 4, GFP_KERNEL, DMA_ATTR_N= O_WARN)?; + /// # Ok::<(), Error>(()) } + /// ``` + pub fn alloc_attrs( + dev: &Device, + count: usize, + gfp_flags: kernel::alloc::Flags, + dma_attrs: Attrs, + ) -> Result> { + build_assert!( + core::mem::size_of::() > 0, + "It doesn't make sense for the allocated type to be a ZST" + ); + + let size =3D count + .checked_mul(core::mem::size_of::()) + .ok_or(EOVERFLOW)?; + let mut dma_handle =3D 0; + // SAFETY: Device pointer is guaranteed as valid by the type invar= iant on `Device`. + let ret =3D unsafe { + bindings::dma_alloc_attrs( + dev.as_raw(), + size, + &mut dma_handle, + gfp_flags.as_raw(), + dma_attrs.as_raw(), + ) + }; + if ret.is_null() { + return Err(ENOMEM); + } + // INVARIANT: We just successfully allocated a coherent region whi= ch is accessible for + // `count` elements, hence the cpu address is valid. We also hold = a refcounted reference + // to the device. + Ok(Self { + dev: dev.into(), + dma_handle, + count, + cpu_addr: ret as *mut T, + dma_attrs, + }) + } + + /// Performs the same functionality as [`CoherentAllocation::alloc_att= rs`], except the + /// `dma_attrs` is 0 by default. + pub fn alloc_coherent( + dev: &Device, + count: usize, + gfp_flags: kernel::alloc::Flags, + ) -> Result> { + CoherentAllocation::alloc_attrs(dev, count, gfp_flags, Attrs(0)) + } + + /// Returns the base address to the allocated region in the CPU's virt= ual address space. + pub fn start_ptr(&self) -> *const T { + self.cpu_addr + } + + /// Returns the base address to the allocated region in the CPU's virt= ual address space as + /// a mutable pointer. + pub fn start_ptr_mut(&mut self) -> *mut T { + self.cpu_addr + } + + /// Returns a DMA handle which may given to the device as the DMA addr= ess base of + /// the region. + pub fn dma_handle(&self) -> bindings::dma_addr_t { + self.dma_handle + } + + /// Returns a pointer to an element from the region with bounds checki= ng. `offset` is in + /// units of `T`, not the number of bytes. + /// + /// Public but hidden since it should only be used from [`dma_read`] a= nd [`dma_write`] macros. + #[doc(hidden)] + pub fn item_from_index(&self, offset: usize) -> Result<*mut T> { + if offset >=3D self.count { + return Err(EINVAL); + } + // SAFETY: + // - The pointer is valid due to type invariant on `CoherentAlloca= tion` + // and we've just checked that the range and index is within bound= s. + // - `offset` can't overflow since it is smaller than `self.count`= and we've checked + // that `self.count` won't overflow early in the constructor. + Ok(unsafe { self.cpu_addr.add(offset) }) + } + + /// Reads the value of `field` and ensures that its type is [`FromByte= s`]. + /// + /// # Safety + /// + /// This must be called from the [`dma_read`] macro which ensures that= the `field` pointer is + /// validated beforehand. + /// + /// Public but hidden since it should only be used from [`dma_read`] m= acro. + #[doc(hidden)] + pub unsafe fn field_read(&self, field: *const F) -> F { + // SAFETY: By the safety requirements field is valid. + unsafe { field.read_volatile() } + } + + /// Writes a value to `field` and ensures that its type is [`AsBytes`]. + /// + /// # Safety + /// + /// This must be called from the [`dma_write`] macro which ensures tha= t the `field` pointer is + /// validated beforehand. + /// + /// Public but hidden since it should only be used from [`dma_write`] = macro. + #[doc(hidden)] + pub unsafe fn field_write(&self, field: *mut F, val: F) { + // SAFETY: By the safety requirements field is valid. + unsafe { field.write_volatile(val) } + } +} + +/// Note that the device configured to do DMA must be halted before this o= bject is dropped. +impl Drop for CoherentAllocation { + fn drop(&mut self) { + let size =3D self.count * core::mem::size_of::(); + // SAFETY: Device pointer is guaranteed as valid by the type invar= iant on `Device`. + // The cpu address, and the dma handle are valid due to the type i= nvariants on + // `CoherentAllocation`. + unsafe { + bindings::dma_free_attrs( + self.dev.as_raw(), + size, + self.cpu_addr as _, + self.dma_handle, + self.dma_attrs.as_raw(), + ) + } + } +} + +/// Reads a field of an item from an allocated region of structs. +/// +/// # Examples +/// +/// ``` +/// use kernel::device::Device; +/// use kernel::dma::{attrs::*, CoherentAllocation}; +/// +/// struct MyStruct { field: u32, } +/// +/// // SAFETY: All bit patterns are acceptable values for `MyStruct`. +/// unsafe impl kernel::transmute::FromBytes for MyStruct{}; +/// // SAFETY: Instances of `MyStruct` have no uninitialized portions. +/// unsafe impl kernel::transmute::AsBytes for MyStruct{}; +/// +/// # fn test(alloc: &kernel::dma::CoherentAllocation) -> Result= { +/// let whole =3D kernel::dma_read!(alloc[2]); +/// let field =3D kernel::dma_read!(alloc[1].field); +/// # Ok::<(), Error>(()) } +/// ``` +#[macro_export] +macro_rules! dma_read { + ($dma:expr, $idx: expr, $($field:tt)*) =3D> {{ + let item =3D $crate::dma::CoherentAllocation::item_from_index(&$dm= a, $idx)?; + // SAFETY: `item_from_index` ensures that `item` is always a valid= pointer and can be + // dereferenced. The compiler also further validates the expressio= n on whether `field` + // is a member of `item` when expanded by the macro. + unsafe { + let ptr_field =3D ::core::ptr::addr_of!((*item) $($field)*); + $crate::dma::CoherentAllocation::field_read(&$dma, ptr_field) + } + }}; + ($dma:ident [ $idx:expr ] $($field:tt)* ) =3D> { + $crate::dma_read!($dma, $idx, $($field)*); + }; + ($($dma:ident).* [ $idx:expr ] $($field:tt)* ) =3D> { + $crate::dma_read!($($dma).*, $idx, $($field)*); + }; +} + +/// Writes to a field of an item from an allocated region of structs. +/// +/// # Examples +/// +/// ``` +/// use kernel::device::Device; +/// use kernel::dma::{attrs::*, CoherentAllocation}; +/// +/// struct MyStruct { member: u32, } +/// +/// // SAFETY: All bit patterns are acceptable values for `MyStruct`. +/// unsafe impl kernel::transmute::FromBytes for MyStruct{}; +/// // SAFETY: Instances of `MyStruct` have no uninitialized portions. +/// unsafe impl kernel::transmute::AsBytes for MyStruct{}; +/// +/// # fn test(alloc: &kernel::dma::CoherentAllocation) -> Result= { +/// kernel::dma_write!(alloc[2].member =3D 0xf); +/// kernel::dma_write!(alloc[1] =3D MyStruct { member: 0xf }); +/// # Ok::<(), Error>(()) } +/// ``` +#[macro_export] +macro_rules! dma_write { + ($dma:ident [ $idx:expr ] $($field:tt)*) =3D> {{ + $crate::dma_write!($dma, $idx, $($field)*); + }}; + ($($dma:ident).* [ $idx:expr ] $($field:tt)* ) =3D> {{ + $crate::dma_write!($($dma).*, $idx, $($field)*); + }}; + ($dma:expr, $idx: expr, =3D $val:expr) =3D> { + let item =3D $crate::dma::CoherentAllocation::item_from_index(&$dm= a, $idx)?; + // SAFETY: `item_from_index` ensures that `item` is always a valid= item. + unsafe { $crate::dma::CoherentAllocation::field_write(&$dma, item,= $val) } + }; + ($dma:expr, $idx: expr, $(.$field:ident)* =3D $val:expr) =3D> { + let item =3D $crate::dma::CoherentAllocation::item_from_index(&$dm= a, $idx)?; + // SAFETY: `item_from_index` ensures that `item` is always a valid= pointer and can be + // dereferenced. The compiler also further validates the expressio= n on whether `field` + // is a member of `item` when expanded by the macro. + unsafe { + let ptr_field =3D ::core::ptr::addr_of_mut!((*item) $(.$field)= *); + $crate::dma::CoherentAllocation::field_write(&$dma, ptr_field,= $val) + } + }; +} diff --git a/rust/kernel/lib.rs b/rust/kernel/lib.rs index 398242f92a96..8e76ef9b4346 100644 --- a/rust/kernel/lib.rs +++ b/rust/kernel/lib.rs @@ -44,6 +44,7 @@ pub mod device; pub mod device_id; pub mod devres; +pub mod dma; pub mod driver; pub mod error; pub mod faux; --=20 2.43.0 From nobody Sun Feb 8 17:47:44 2026 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BDBD2638A5; Tue, 11 Mar 2025 17:49:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715394; cv=none; b=W8u8sL0IGXiophtHrrkdZnIqDDub5T5LAZJv0ea1Hw/xi1dHeai8nu9+ZwpOnBHHKjXIW+K7nU76ugkoA0zZiyfKMIIfXvFn6ycqREgxBe8QuEDWhPgDkXi9y7qoVntkPpk0psyGJhL3+lU4mSeVZkiYvofEQd0ryd6b+tduAGc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715394; c=relaxed/simple; bh=NPurUptvYolnP+zwLTc8xyODM40c1STXAevHbBUYyUM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P7cxaq+gn0VKfOeaQE4aey0k0osW2Jd7gnHaesXP5+xLMvDblLoNQeDi3JiyczH43uuNGWCsywUrB5rTOaDKv3uHpNHJJOo5SETa0w1gev3w1nriVYOe+qyUBY5BKoJfwTrocKZ1fQ590hnB0LDBavO4tmlzqSSy5tV6Lu3/NOs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=kC7HJpin; arc=none smtp.client-ip=209.85.167.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="kC7HJpin" Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-54998f865b8so3710791e87.3; Tue, 11 Mar 2025 10:49:51 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1741715390; x=1742320190; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=HY0a+7Bd76kNssAI216pzAYL/YAAvUS9w1O5DEvCouw=; b=kC7HJpintuPxuFVQ376ZhKQeSlDm3afRVsBf+Aeln327+EPWPakKayCSqtlPnHPXzu o2/l8qxg1v2AYRWeOIAua3gU8CuXwi5nWFodgao66CEYpiAtyjAkCFAk/djm0eGuJwwn Tq1k15I7YFI3CEOqg4M6gjvDXCnSeOwK5Jhut0NjkTy+2KT9WluwbuG8XtFMkwYXwWhx Um0BMf6BlDf5UPSgRpS4c7SiESO1Vnv7zoNye0nRPjzFAa9NPQyFJieyc3bofW2TY5ix lgA44oDgYhX9KlE2Mw7dSe2/1dfnYyMP+oanI7A0rUa5b5X/iEuGavx62Iiu1QvjH+ai CP0g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741715390; x=1742320190; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=HY0a+7Bd76kNssAI216pzAYL/YAAvUS9w1O5DEvCouw=; b=lapScmNC564BFyE83vEp6L/2IW6n98op0M7BrDigliaDy2/WrcWko7jK7Zl4RxtYoE GCfwhCxmtu2czDMPcsSgoYR5o0CThuA4diSskmgh/qCf3dZX85wn3Kn3gFLhG6+95XPb mVRtWqp4fByqkIo+H9juUw6OjOhHRTS2FbYPuKO34n1bLwR93EnIeWQlgJppq9spKDRq cSNePulJ8WA/DaEb1/kELV+KgZxx8iynPLAHsJFU2DDSraHddwS/+qRv6Kl66vkpfQdt pHURKD9g/QaFjMQw7zgj7mbEye2/tP811PN5fGfS3xWXs8BFNETWkI2tcuRnBkUzNHsW biug== X-Forwarded-Encrypted: i=1; AJvYcCVQ7y9zVamA88Wv+PGi3o4kfLanVCMrSo+l+9V/GNgC2ZQpGj3ru/tAlF5hJidGMpASUTsC1Z95AZyPPdA=@vger.kernel.org X-Gm-Message-State: AOJu0YzNSsf3xXYtZyoAFzLrOtzmWcCHCjhoUDj4lAz5g3rukvtdiYn7 krBA2IBbVlONchsCFR8wVTjjxmFkVMv7tvaNGiAMOXrYj6VqQe9ovcwpsA== X-Gm-Gg: ASbGncv0jDdmBSkvmlAK9LgmxbLJr680ZEBoelxmpDYo2fJ+Fce8c/wnngbANfvIVoR V5uUZ3MxyUoAWChxletNO0+EZayflMIdeFaaLso2dVe7wVSIOOW2lO9dH4uc0BcVYHCfA9mlAMh FC3FV+GngCHoATf8Mt+uUXwjiipifTIgkT4ja5+9AZhe9l0oC0ucydmfyvc0L1diRuHJoHyWLT4 lGdo5ogUwpL3n/tgFubkvCDMDiDo25sCXahYJDSUWWkIoRMypz5J4kXNKki471NkdonLpXVpl2S y7PiJ0INGPrpEfTPTuYXfzryPzVyjMkl8p8Y5z7QEdOb0hcKTSKtFdYdcUxi7/pY+XY0jSUujaO 3aJ5FMkeZ13FUOSiBQn53Aw== X-Google-Smtp-Source: AGHT+IHwItuL4p8GEONkja8pXnOCoaN6KKG1lPFxAT9W4J2iw1+SfhfJZwRqf3e2PLRMhwdeW6DL/Q== X-Received: by 2002:a05:6512:3d8f:b0:549:9044:94b3 with SMTP id 2adb3069b0e04-54990e67285mr5883924e87.29.1741715390119; Tue, 11 Mar 2025 10:49:50 -0700 (PDT) Received: from abj-NUC9VXQNX.. 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.49.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:49:48 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 03/11] samples: rust: add Rust dma test sample driver Date: Tue, 11 Mar 2025 19:47:59 +0200 Message-ID: <20250311174930.2348813-4-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add a simple driver to excercise the basics of the Rust DMA coherent allocator bindings. Suggested-by: Danilo Krummrich Signed-off-by: Abdiel Janulgue --- samples/rust/Kconfig | 11 +++++ samples/rust/Makefile | 1 + samples/rust/rust_dma.rs | 97 ++++++++++++++++++++++++++++++++++++++++ 3 files changed, 109 insertions(+) create mode 100644 samples/rust/rust_dma.rs diff --git a/samples/rust/Kconfig b/samples/rust/Kconfig index 3b6eae84b297..e2d14aa6beec 100644 --- a/samples/rust/Kconfig +++ b/samples/rust/Kconfig @@ -78,4 +78,15 @@ config SAMPLE_RUST_HOSTPROGS =20 If unsure, say N. =20 +config SAMPLE_RUST_DRIVER_DMA + tristate "DMA Test Driver" + depends on PCI + help + This option builds the Rust dma test driver sample. + + To compile this as a module, choose M here: + the module will be called dma. + + If unsure, say N. + endif # SAMPLES_RUST diff --git a/samples/rust/Makefile b/samples/rust/Makefile index 0dbc6d90f1ef..1a9aff6e8d6a 100644 --- a/samples/rust/Makefile +++ b/samples/rust/Makefile @@ -7,6 +7,7 @@ obj-$(CONFIG_SAMPLE_RUST_PRINT) +=3D rust_print.o obj-$(CONFIG_SAMPLE_RUST_DRIVER_PCI) +=3D rust_driver_pci.o obj-$(CONFIG_SAMPLE_RUST_DRIVER_PLATFORM) +=3D rust_driver_platform.o obj-$(CONFIG_SAMPLE_RUST_DRIVER_FAUX) +=3D rust_driver_faux.o +obj-$(CONFIG_SAMPLE_RUST_DRIVER_DMA) +=3D rust_dma.o =20 rust_print-y :=3D rust_print_main.o rust_print_events.o =20 diff --git a/samples/rust/rust_dma.rs b/samples/rust/rust_dma.rs new file mode 100644 index 000000000000..1740140faba6 --- /dev/null +++ b/samples/rust/rust_dma.rs @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 + +//! Rust DMA api test (based on QEMU's `pci-testdev`). +//! +//! To make this driver probe, QEMU must be run with `-device pci-testdev`. + +use kernel::{bindings, dma::CoherentAllocation, pci, prelude::*}; + +struct DmaSampleDriver { + pdev: pci::Device, + ca: CoherentAllocation, +} + +const TEST_VALUES: [(u32, u32); 5] =3D [ + (0xa, 0xb), + (0xc, 0xd), + (0xe, 0xf), + (0xab, 0xba), + (0xcd, 0xef), +]; + +struct MyStruct { + h: u32, + b: u32, +} + +impl MyStruct { + fn new(h: u32, b: u32) -> Self { + Self { h, b } + } +} +// SAFETY: All bit patterns are acceptable values for `MyStruct`. +unsafe impl kernel::transmute::AsBytes for MyStruct {} +// SAFETY: Instances of `MyStruct` have no uninitialized portions. +unsafe impl kernel::transmute::FromBytes for MyStruct {} + +kernel::pci_device_table!( + PCI_TABLE, + MODULE_PCI_TABLE, + ::IdInfo, + [( + pci::DeviceId::from_id(bindings::PCI_VENDOR_ID_REDHAT, 0x5), + () + )] +); + +impl pci::Driver for DmaSampleDriver { + type IdInfo =3D (); + const ID_TABLE: pci::IdTable =3D &PCI_TABLE; + + fn probe(pdev: &mut pci::Device, _info: &Self::IdInfo) -> Result>> { + dev_info!(pdev.as_ref(), "Probe DMA test driver.\n"); + + let ca: CoherentAllocation =3D + CoherentAllocation::alloc_coherent(pdev.as_ref(), TEST_VALUES.= len(), GFP_KERNEL)?; + + || -> Result { + for (i, value) in TEST_VALUES.into_iter().enumerate() { + kernel::dma_write!(ca[i] =3D MyStruct::new(value.0, value.= 1)); + } + + Ok(()) + }()?; + + let drvdata =3D KBox::new( + Self { + pdev: pdev.clone(), + ca, + }, + GFP_KERNEL, + )?; + + Ok(drvdata.into()) + } +} + +impl Drop for DmaSampleDriver { + fn drop(&mut self) { + dev_info!(self.pdev.as_ref(), "Unload DMA test driver.\n"); + + let _ =3D || -> Result { + for (i, value) in TEST_VALUES.into_iter().enumerate() { + assert_eq!(kernel::dma_read!(self.ca[i].h), value.0); + assert_eq!(kernel::dma_read!(self.ca[i].b), value.1); + } + Ok(()) + }(); + } +} + +kernel::module_pci_driver! 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.49.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:49:51 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 04/11] MAINTAINERS: add entry for Rust dma mapping helpers device driver API Date: Tue, 11 Mar 2025 19:48:00 +0200 Message-ID: <20250311174930.2348813-5-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add an entry for the Rust dma mapping helpers abstractions. Nacked-by: Christoph Hellwig Acked-by: Danilo Krummrich Acked-by: Andreas Hindborg Signed-off-by: Abdiel Janulgue Acked-by: Marek Szyprowski --- MAINTAINERS | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 007ca67cc830..aa49c551fbec 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -6902,6 +6902,19 @@ F: include/linux/dma-mapping.h F: include/linux/swiotlb.h F: kernel/dma/ =20 +DMA MAPPING HELPERS DEVICE DRIVER API [RUST] +M: Abdiel Janulgue +M: Danilo Krummrich +R: Daniel Almeida +R: Robin Murphy +R: Andreas Hindborg +L: rust-for-linux@vger.kernel.org +S: Supported +W: https://rust-for-linux.com +T: git https://github.com/Rust-for-Linux/linux.git alloc-next +F: rust/kernel/dma.rs +F: samples/rust/rust_dma.rs + DMA-BUF HEAPS FRAMEWORK M: Sumit Semwal R: Benjamin Gaignard --=20 2.43.0 From nobody Sun Feb 8 17:47:44 2026 Received: from mail-lf1-f44.google.com (mail-lf1-f44.google.com [209.85.167.44]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0D6C0263C6B; Tue, 11 Mar 2025 17:49:55 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.44 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715397; cv=none; b=mOOmmgtwYIz7M/y2qdYp3OKyIDcPr8A/ArAZAJbmOn3IWEzPAWHt69eBSLch0zOq1v9/CbdJqPp6AJVOt+GwwWc6lxciC4ZQyAj/xNK8UZ+lLFKbPuU+5Qqvj81IYTWOXx+I6bha2Mxfhb4pxUG/ScMekFCBLECrOe7P4Ya/ND8= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715397; c=relaxed/simple; bh=g2IUN8jCVllbF1ZiAJOX0NP0fmAmUk0/qWWI8VzUu7g=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=sneDVswQwqEG46KbANzywvJIf5EWHt0N6Op7iE/6Nog5vLx54mARpLsSNXjIVSMaBxaNfAbuKhkFpwEVzS4IdMLknraLRFBpc8g4Km34a9FT3/+/CaN3H+sypLjA7zlsMGHlcQQXszSGwtI9Awqnq9DPg+5ZNBzElNjhwt/G64Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=ACAzO07K; arc=none smtp.client-ip=209.85.167.44 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="ACAzO07K" Received: by mail-lf1-f44.google.com with SMTP id 2adb3069b0e04-5495c1e1b63so5948092e87.0; Tue, 11 Mar 2025 10:49:55 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1741715394; x=1742320194; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=W4DDd/iic2hsiU29M8h+cyzkeUX9RCrQK1w4R9M79gk=; b=ACAzO07K4QwVkfLyRMiRcqfF6m/PloyGn/UndV2bbkBdR+AvNuOh7jqATmDiavXVKx /ALPLyPB/T93/3MpUk3uwnYkaXBHQ0V8VfCPTx//nOy1VOVRrKbGx5HdRT7ws+TnqUfs aoark/k0oyUd56EcgGoWThW7D9hTxQHJc8qsMKwIYSNbbqRl1mjxxcQSSzyHsX1jQD0f 3CkIAwNSzdatdn53pS+3gnjPqQuhiqiI9eyQj7lM+GzvJsHIn3xGTA526YOresEVdWUp 5F+qr1hZsZgytUud+B7jLeSW721hUYs2DWTPI/fICDhusSw5IVc3fqKeNdKXvf9HFa4+ wj6Q== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741715394; x=1742320194; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=W4DDd/iic2hsiU29M8h+cyzkeUX9RCrQK1w4R9M79gk=; b=hGckO7HHHxpLXZ1zb4O21qzunt2aYLHWJ7gqW2eTRZJHP0lQ4LUA+BmuEZhAF7gx5K gRZbynkZ+ANVpJhB5BlkSs68fndCoe6EgIVz0A3bCbFZnX7T+wSZpACCEIaLUynzU7j/ Y+/MErj9Wzkw5v4nL+jdwNOGHbpzvd7iP3pkm1aDebOM7HTMiFD4W/y90fdjxuFbTGwd /25Vxz9gQ7VSgQojb8WCHGdsYhXUq0H4xCtBWtq++PDegS1Gz+hMRZrmNsUngJyGqXhq ztnSN60qEs+PB+zmn+cVl9R0bAyyAh1LnyrAwGjaNmnVOXk29bB/bYboozKOe1uwR3xc CrEg== X-Forwarded-Encrypted: i=1; AJvYcCUrQylZZ9PKv+mSF/Bsu5PpN8yeuZGNk5hAh1gQfsJCKp6bFpvtX9tQaUF3jvMi93v7RvRvFJ12lNS26ZY=@vger.kernel.org X-Gm-Message-State: AOJu0YywN2IuouQ66w7WV3MNwAVSZnIByXhW08TbLJN+jflVXdeVYTae bfdWOb87EDP5P3rMQvpR7RfR5cQ/tQKpR/AP7AeosE0VCSGd5iTa5quV6w== X-Gm-Gg: ASbGncuyuCJLDYYBgoVXCMFS2IUbGvJzPEc63Iq7Kgyzp8y9CsghDp/6GUz7pGv+e/T RAR8wi98/1MyHUDmpjd20KDqtLsoLrFFBCMBhLHiKs8Q+EPESkYq1YONNqDUyICLjSQOdRwhTWi grgjXFDjBBtSqQDxEpwBFANKhe0St9JMdn0FxxieefCi/diRgcOlgH6id8GV+QqyO93NfvkYI4C XGN6v1tldr58gArBAigYn60r64vo4zrTa6QTU+Xd877QPln05cLKnxVLGn2mEUe/W27VvxOvglM 04EKgASdcltyyAzKvt2P5VsjpHr4ditb3qDGW8PXcxg7HSqnz/Oclc6bSStooKcAcVjTpSs9JTq NdAyS3X9V26qydh90noM/Hw== X-Google-Smtp-Source: AGHT+IEK8bFyfeYyDu9u2ggRv4bnWCiWDFZdozZy4sv0fCHGsi/lf50Ck2X/Ydwr4axZ6CUhdcQvDg== X-Received: by 2002:a05:6512:1116:b0:545:6fa:bf5f with SMTP id 2adb3069b0e04-549abaaaf60mr1682087e87.2.1741715393817; Tue, 11 Mar 2025 10:49:53 -0700 (PDT) Received: from abj-NUC9VXQNX.. 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.49.52 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:49:53 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 05/11] rust: dma: implement `dma::Device` trait Date: Tue, 11 Mar 2025 19:48:01 +0200 Message-ID: <20250311174930.2348813-6-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Danilo Krummrich Add a trait that defines the DMA specific methods of devices. The `dma::Device` trait should be implemented by (bus) device representations, where the underlying bus potentially supports DMA, such as `pci::Device` or `platform::Device`. Signed-off-by: Danilo Krummrich Signed-off-by: Abdiel Janulgue --- rust/kernel/dma.rs | 15 +++++++++++---- 1 file changed, 11 insertions(+), 4 deletions(-) diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index 325b00fe7871..7ff797a7ad18 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -6,13 +6,20 @@ =20 use crate::{ bindings, build_assert, - device::Device, + device, error::code::*, error::Result, transmute::{AsBytes, FromBytes}, types::ARef, }; =20 +/// Trait to be implemented by bus specific devices. +/// +/// The [`Device`] trait should be implemented by bus specific device repr= esentations, where the +/// underlying bus has potential support for DMA, such as [`crate::pci::De= vice`] or +/// [crate::platform::Device]. +pub trait Device: AsRef {} + /// Possible attributes associated with a DMA mapping. /// /// They can be combined with the operators `|`, `&`, and `!`. @@ -130,7 +137,7 @@ pub mod attrs { // Hence, find a way to revoke the device resources of a `CoherentAllocati= on`, but not the // entire `CoherentAllocation` including the allocated memory itself. pub struct CoherentAllocation { - dev: ARef, + dev: ARef, dma_handle: bindings::dma_addr_t, count: usize, cpu_addr: *mut T, @@ -152,7 +159,7 @@ impl CoherentAllocation { /// # Ok::<(), Error>(()) } /// ``` pub fn alloc_attrs( - dev: &Device, + dev: &device::Device, count: usize, gfp_flags: kernel::alloc::Flags, dma_attrs: Attrs, @@ -194,7 +201,7 @@ pub fn alloc_attrs( /// Performs the same functionality as [`CoherentAllocation::alloc_att= rs`], except the /// `dma_attrs` is 0 by default. pub fn alloc_coherent( - dev: &Device, + dev: &device::Device, count: usize, gfp_flags: kernel::alloc::Flags, ) -> Result> { --=20 2.43.0 From nobody Sun Feb 8 17:47:44 2026 Received: from mail-lj1-f177.google.com (mail-lj1-f177.google.com [209.85.208.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E3761263F3F; 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.49.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:49:55 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 06/11] rust: dma: add dma addressing capabilities Date: Tue, 11 Mar 2025 19:48:02 +0200 Message-ID: <20250311174930.2348813-7-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Danilo Krummrich Implement `dma_set_mask()` and `dma_set_mask_and_coherent()` in the `dma::Device` trait. Those methods are used to inform the kernel about the device's DMA addressing capabilities. Co-developed-by: Abdiel Janulgue Signed-off-by: Abdiel Janulgue Signed-off-by: Danilo Krummrich --- rust/helpers/dma.c | 8 ++++++++ rust/helpers/helpers.c | 1 + rust/kernel/dma.rs | 46 +++++++++++++++++++++++++++++++++++++++--- 3 files changed, 52 insertions(+), 3 deletions(-) create mode 100644 rust/helpers/dma.c diff --git a/rust/helpers/dma.c b/rust/helpers/dma.c new file mode 100644 index 000000000000..8eb482386f93 --- /dev/null +++ b/rust/helpers/dma.c @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0 + +#include + +int rust_helper_dma_set_mask_and_coherent(struct device *dev, u64 mask) +{ + return dma_set_mask_and_coherent(dev, mask); +} diff --git a/rust/helpers/helpers.c b/rust/helpers/helpers.c index 0640b7e115be..8f3808c8b7fe 100644 --- a/rust/helpers/helpers.c +++ b/rust/helpers/helpers.c @@ -13,6 +13,7 @@ #include "build_bug.c" #include "cred.c" #include "device.c" +#include "dma.c" #include "err.c" #include "fs.c" #include "io.c" diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index 7ff797a7ad18..ac3ec0042327 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -5,10 +5,10 @@ //! C header: [`include/linux/dma-mapping.h`](srctree/include/linux/dma-ma= pping.h) =20 use crate::{ - bindings, build_assert, - device, + bindings, build_assert, device, error::code::*, error::Result, + prelude::*, transmute::{AsBytes, FromBytes}, types::ARef, }; @@ -18,7 +18,35 @@ /// The [`Device`] trait should be implemented by bus specific device repr= esentations, where the /// underlying bus has potential support for DMA, such as [`crate::pci::De= vice`] or /// [crate::platform::Device]. -pub trait Device: AsRef {} +pub trait Device: AsRef { + /// Inform the kernel about the device's DMA addressing capabilities. + /// + /// Set both the DMA mask and the coherent DMA mask to the same value. + /// + /// Note that we don't check the return value from the C `dma_set_cohe= rent_mask` as the DMA API + /// guarantees that the coherent DMA mask can be set to the same or sm= aller than the streaming + /// DMA mask. + fn dma_set_mask_and_coherent(&mut self, mask: u64) -> Result { + // SAFETY: By the type invariant of `device::Device`, `self.as_ref= ().as_raw()` is valid. + let ret =3D unsafe { bindings::dma_set_mask_and_coherent(self.as_r= ef().as_raw(), mask) }; + if ret !=3D 0 { + Err(Error::from_errno(ret)) + } else { + Ok(()) + } + } + + /// Same as [`Self::dma_set_mask_and_coherent`], but set the mask only= for streaming mappings. + fn dma_set_mask(&mut self, mask: u64) -> Result { + // SAFETY: By the type invariant of `device::Device`, `self.as_ref= ().as_raw()` is valid. + let ret =3D unsafe { bindings::dma_set_mask(self.as_ref().as_raw()= , mask) }; + if ret !=3D 0 { + Err(Error::from_errno(ret)) + } else { + Ok(()) + } + } +} =20 /// Possible attributes associated with a DMA mapping. /// @@ -374,3 +402,15 @@ macro_rules! dma_write { } }; } + +/// Helper function to set the bit mask for DMA addressing. +pub const fn dma_bit_mask(n: usize) -> u64 { + if n > 64 { + return 0; + } + if n =3D=3D 64 { + !0 + } else { + (1 << (n)) - 1 + } +} --=20 2.43.0 From nobody Sun Feb 8 17:47:44 2026 Received: from mail-lj1-f171.google.com (mail-lj1-f171.google.com [209.85.208.171]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 828F6263C85; Tue, 11 Mar 2025 17:50:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.171 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715402; cv=none; b=ZmF6FwyBaC19TUOssLjo8mURkMLiVfAuH4gqBCQyjV5NfP9hnY+Uo0W5sS2gxmzkc1X6xyyQ9tnRGM7JnMj/Vdua9umW98WpGYUN4IgDbYrhAnSjXkWizkyL40xyJmDBUxkAPDXq7s4fsGoZ41Wxm5uv9ciWIeWunk+goEXFstI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715402; c=relaxed/simple; bh=VyefDGWH0N2YpL9VfzECx+ApcLuk3v2hDwgQ1bV/Fl0=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=aQAa1eT0AefvwyneddZ8Uc1I4q0YelfibW0k9L4nfPgqHOHO3DXMsJOkxaR/ohqcRMRpLRFnTgO5x392ewPMkQOajFSDn6bQitVicgkHvmW2n8Hh1DIQDuFzqUiTXUS/GlW3J87SoOXp0gOpP4+mv4ZebWl6u18Yg8Jxa/KFKPw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=FUeZJZr3; arc=none smtp.client-ip=209.85.208.171 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="FUeZJZr3" Received: by mail-lj1-f171.google.com with SMTP id 38308e7fff4ca-30613802a59so64189001fa.0; Tue, 11 Mar 2025 10:50:00 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1741715399; x=1742320199; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=9RE7FkHXPj3rgd/JOL9Q773Ys4uYomt6iSafrtUCPEA=; b=FUeZJZr3yXQFWbfN7otgg8iPf/9Mw88VcrL4GGMdj9K/OX3h7CGue9mRl+hRLyVdXm pWY9eInHLHzhYhXIYq7uhOwXAjHEAFIfLLl7yN34ilbakUEgl7VVLT+3bZ3aX0xX0Ggc LqnHQm02tinm+q+SHkS3FpydD8ZjtHv45krpl1vIEX1qXc9ZScHSZhdYNVv6uJsgvQmj E73aN9SVZZj9MatUPei6SLbAiThewYVS09fluQ+r73lHuriU2KWvs4QY1ZHiCUnIsHLM rj5Acnijq7obrtpWjMeUmrZXqGFOZzlgEnFIHVbrx2e8h+7GBHldJT16ycl5WkSLcCjU 5vlA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741715399; x=1742320199; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=9RE7FkHXPj3rgd/JOL9Q773Ys4uYomt6iSafrtUCPEA=; b=cdbnUseNE/KeYd4cI7pQvYmPB1Z/KpPlydHbt9ev+7yBeO+5RwQBPb5GBmhFDhou6b 76B2cvU0OBlPOVlFIxyYKvkoaBf5TBCZ60tqn4flbYuOgV74jDHWdEcL/fRZlqfyZz4p kmO+hkFdaUU9qBlYLOrudM84fBLqJKkzcbNuKt+AiscHCBubDtllcp+04Cl9utAjyvfX 5w+XQk1UlP031m5ChUnULlb52uBiGJ1yBplCyHBIFNF9JID+mbOU9FXb4GKq2rnXFPgc T/SewyWNdQX5KqsEYFHyODOHU7B/P+nYS8g4gC9Wx658HjCp1MaQhz/4bc9PGSmyRoz6 BPpQ== X-Forwarded-Encrypted: i=1; AJvYcCUteqAvdD7KJHdJaG312Id7kikLlPa8gMo12Wgok4cEMmMN4L/OVrNGrcFkOhNVgmchhqwUIEbSNw7Rb/E=@vger.kernel.org X-Gm-Message-State: AOJu0YwraBgy2rBLwmO5fq0FeKmQOR2xcuSG00pnsVqDrB09+vNvPwuq JQDgyuBlhVZnuJBs2rZTv+UH75HOt/0pWXZs6R4BqsEByk103lt420N4bg== X-Gm-Gg: ASbGnct4+JCLslQ7+IEphO373zd8zfT8NVYzNs8oBOVGIgM6oONUc8FidAe14wozeHO dEJO22vvaao/N8TlxWXfW5yaxJ84R19gVt9jJ1d2y/+S6lTcf/OnHaEuTNamr5k/194/CDNAMRO CywWdNRsMYahKv7zEvilfTH96Ub5bNmAG/WjTJOAzQ278OCvYDa+Jms3TpdsluA7M8VtF6JZbJK xgYqfOzwIXfwVExT9msAaYs7phwIBxVEQOjEscyrPDH97ZJ5HRbfFi80UMp7d3d3Rz2bzoeTIj/ RQHdlhDhQdzALZbXI6KebGQUcbxLiYPR2UAmWQrUcLuCFP3NHjKuvsv+NAsshUtx7eWcePXH7ZE 08fJT6lFyzKWM5UsfC7cdRA== X-Google-Smtp-Source: AGHT+IG4/njd7PlBm1mpnIVR9OdsVm4WGkJQXiTRSmnS3QRyKrR3ovUI1B0STYMLIlQyY1eNipdRAA== X-Received: by 2002:a19:8c0b:0:b0:549:b13a:5d7f with SMTP id 2adb3069b0e04-549b13a5e20mr216857e87.41.1741715398584; Tue, 11 Mar 2025 10:49:58 -0700 (PDT) Received: from abj-NUC9VXQNX.. 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.49.56 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:49:57 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 07/11] rust: pci: implement the `dma::Device` trait Date: Tue, 11 Mar 2025 19:48:03 +0200 Message-ID: <20250311174930.2348813-8-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Danilo Krummrich The PCI bus is potentially capable of performing DMA, hence implement the `dma:Device` trait for `pci::Device`. Signed-off-by: Danilo Krummrich Signed-off-by: Abdiel Janulgue --- rust/kernel/pci.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs index f7b2743828ae..5839aa5d4098 100644 --- a/rust/kernel/pci.rs +++ b/rust/kernel/pci.rs @@ -432,3 +432,5 @@ fn as_ref(&self) -> &device::Device { &self.0 } } + +impl crate::dma::Device for Device {} --=20 2.43.0 From nobody Sun Feb 8 17:47:44 2026 Received: from mail-lf1-f45.google.com (mail-lf1-f45.google.com [209.85.167.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 753D1262D21; Tue, 11 Mar 2025 17:50:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.45 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715405; cv=none; b=VkGk+G27x7qKj3eBzGVaYVU5E327luzjGIqx0yAlwgR1KiNIUDD6DXMIRkemdGktgqdnvKYsBROSFACeZiuova7zmXhSI/5K1r1pxRVWaZUmvSMTfI1i7EFbksoKPVqSuiQZMD45mSzu0+HYKTGqxBk9VbwkfAkyRehooRLdojo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715405; c=relaxed/simple; bh=DhrwcCKAPl4wQYbKHYYSepNVPu31+4xtNNYqjdxy+Ig=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nEFFL9JVf2f34Uh6ySe95xTm5SKY6VBcERXMsR12svhMgkBAVS7w0NSDjgin7CpUXaKRwUr5kl5PnDoVtCS5E6u4H2yS3XuPolhhmirJKAefSqecwQZoBjLCOjdTl+KQdJoNY3RIrqutrX8Zr90po6ytCSGR70hExLOlfQz+gK8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=mD1GyJsO; arc=none smtp.client-ip=209.85.167.45 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="mD1GyJsO" Received: by mail-lf1-f45.google.com with SMTP id 2adb3069b0e04-54963160818so6550297e87.2; Tue, 11 Mar 2025 10:50:03 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1741715402; x=1742320202; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=bITllDD7zuDX+leMoEvJ9eOhvzTi6bzqiRqTzF92s50=; b=mD1GyJsO531yX6cgGwevwwlDdu3mg0XMoRdv1IdjLOZVIDDf6XYgg4hOglQNOBTbvN JiC58l90m1z+LRYJi45SPma7ID3U29kePN9S6n4J7hauNXlNDgp3BM5Y/oocaHtGcWxs 8kN7XSgoj1eduWcwF6xH5QgG7607wtPnCx3JfQVJ80H6u9eHFCV1hxYOLzTWQ3dnvZA9 Y+tKipcX34gdylC9tjThCwIHsNe7ZCkgUhKiKlW6+ALEjBzb54jGmuCKDNpLzd02xeb7 +fnm4WQqbIhrrQA3uIhfuNAUcqoU3U/1ggGoRsDazGOcjzuE7fYoNzIFr/duaBx4aWxj FAUA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741715402; x=1742320202; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=bITllDD7zuDX+leMoEvJ9eOhvzTi6bzqiRqTzF92s50=; b=IUYh0iN2JHwglMdNX2tXIrsU/UivhXzmzMzB1IWDvXrAk/Fg2NvtD8OtuQaM7f5+zk Sow56um3WVOOKVeYy1+CAamtLYNcpSKmxtX5ZCw0JXtVuQtkGssgPcKrDypt23BafMdB 6QsA/OSZsfVyZmtTx3VPELD67O5l5TzbmO2pzJLBABHbd7u5Mpedg0CmbAUZy3Z9ZsVr XC/QCGSgXlsrCQksPQcf/ImRL4GDeYHxZp3S9XtJ5b4zmk6XV45Rvcyy3ZdS8LhNuxCw MPJdc+JX00pYj794iB3BILZwQ6WrnwTjc7S1LFS5hOdAhFqrNor7lW87MkhLXKJsPB7N EfTw== X-Forwarded-Encrypted: i=1; AJvYcCUyvdFINq/QJYmLo5SHvhC/mrjYKEs+TTd5Qf3gRNKNV8ixDnqrPxq7E35e5VXkXwRs0XBl9ia76u6nbMo=@vger.kernel.org X-Gm-Message-State: AOJu0YwRgqkjLuCfalFZn7LEDxDH1ICIcba4KeudM0y/IVduUqz/J32Z /QjrlPDIXOcBcGdPusPukyEOxe1cTjO/0o7Oi/qd3cjqycULimPKwPs+1w== X-Gm-Gg: ASbGncuUNm0IEol78wZPLMzwEFMNjLBFRJiD8hdTNFncabJ7yKBI4bASZgOMm7iwchg b+QJCE52yaXUCkyJEdDmx2MEFDPs7UzRE99hoVGEMMB/DQlqbeFZqgA5elx8SfIaLDMuDyIBjPi Ja+8ZEVNryq/Q+fSo+kiT49DERf1bHcLA6/W9Sp09Ff3CffM+urqhEKCyZz/c7fokUjc/AL1bq1 XjB+Xf6VXOS6dyK3k7/U4JPCCCoRlHOXXJfHiIU9RAaqNCh5GsCCj37ebp2eG4dHDjFWh8ysQ4j Mt+q5LIevuvMc+Fnkxr+yrDNbRzKxvKME0N2OL9/uUxFbLGskOphnsMZZ+o7NWQhKDhA9D+fCBv X3O4Qh+06WTWdoLNrdTwbDA== X-Google-Smtp-Source: AGHT+IHLqeLrmjCzyXaU21i/GMhrHAYwaPPURUglknBJ5VdO/cQPJy+xrLkGD/iWnJmSh58Q5/RDJQ== X-Received: by 2002:a05:6512:3d15:b0:545:2eca:856 with SMTP id 2adb3069b0e04-54990e2be1fmr5700784e87.9.1741715401504; Tue, 11 Mar 2025 10:50:01 -0700 (PDT) Received: from abj-NUC9VXQNX.. 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.49.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:50:00 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 08/11] rust: platform: implement the `dma::Device` trait Date: Tue, 11 Mar 2025 19:48:04 +0200 Message-ID: <20250311174930.2348813-9-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Danilo Krummrich The platform bus is potentially capable of performing DMA, hence implement the `dma:Device` trait for `platform::Device`. Signed-off-by: Danilo Krummrich Signed-off-by: Abdiel Janulgue --- rust/kernel/platform.rs | 2 ++ 1 file changed, 2 insertions(+) diff --git a/rust/kernel/platform.rs b/rust/kernel/platform.rs index 1297f5292ba9..a7bf3525313e 100644 --- a/rust/kernel/platform.rs +++ b/rust/kernel/platform.rs @@ -198,3 +198,5 @@ fn as_ref(&self) -> &device::Device { &self.0 } } + +impl crate::dma::Device for Device {} --=20 2.43.0 From nobody Sun Feb 8 17:47:44 2026 Received: from mail-lf1-f48.google.com (mail-lf1-f48.google.com [209.85.167.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 49BFB26460E; Tue, 11 Mar 2025 17:50:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.48 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715407; cv=none; b=NA23T6VY5yRIAMiVCx6PujLyFRFyDg67fpSPW7DoxvVVFIjf3m0RQId6xa4mIfePIb44zQjPZWSeQz6KvcVqKTE9HrS7A8ZE7Pj2LOkNyDDqSjYtnnkTNKdyQi/953j0kSukmHWJd/4e+x4OUfZGC7jntheQof5qpJQ4YcwY19A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715407; c=relaxed/simple; bh=jCAxjyGzs4oya9QaR78RpvqzvHqmUmPWVJY26/yTUlo=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=KY/3Ax3xvZokBPkyNfAAm59oZSbap9PzVDRh9HxcV1Z4VGlkL44mcJcW4O7cffhFxCrnhOurWUIx5JsVP3U6jL5I5e8O+ap9CyHw/FXUgifnNa/sdhT5XIle5CC2AHd5hZ2awgzAzGlZlQn3CLUWUwvD31JJy/k8mPvi3BdX2xc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=Cf0OoOSa; arc=none smtp.client-ip=209.85.167.48 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="Cf0OoOSa" Received: by mail-lf1-f48.google.com with SMTP id 2adb3069b0e04-5498c742661so6225348e87.1; Tue, 11 Mar 2025 10:50:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1741715403; x=1742320203; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=a/BcF9+5sRTzvu9Wbc78vwyZ0YSIeBA8i4IVXLbkZM8=; b=Cf0OoOSaitSYpICxLVNpJCMOWMps5QmElF5BUIhoz72a/dx13CNr0Z/19a6Q27+FSw eVNJm9Ceq8vfVZfNLq952OYBLpsOtV0Hb4Pv/Jr/Ek4CU/qS+P5NqZDhVUnu8iZYleQn sn6IIg0SvqFz5F1RLeciN4CuwmK9qbwf1mSlgX/MpYk3Z7LubwhEjCT6jXRrzH8cM94A BLaCCN/VvEpsX5zKFBVjv6FYdJSLxDHBjeuWrlM9b6xK2shZfbL2kdiGqmNAPIRW8xPo xaI4pwjZ4EwQMp4oDWY8W81Mn326z0ku0RECqA2JBM2qbk3fF5/o8r88KO9dqbXO2cBa 9L8g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741715403; x=1742320203; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=a/BcF9+5sRTzvu9Wbc78vwyZ0YSIeBA8i4IVXLbkZM8=; b=SIyFdljm88rKEm8XjVvHWHCpo4I4D8YIhXHr5J3XQA1EjZm30Y800eTykb0nWcZrqX DM9VPvu7H5YulaNL/YwMoaR909kkSVDJjJW+FyejnmI14P65P4TK16r3GmJmGIHz0Wn2 glbaJqPBIwKt+p4gjlzsgcqwICiKCu3P4Jwg1b4ANI67LHOI409gvP/Z2UCffzAfzKnJ yCBj10scAW5SeyxbVwqETliAT5sQyRRn5veOfeBg1oY42EmcLM9nKoWiQHus/ltateR/ QzucvENEtU2AQd12AI4KaASIifJI27PUWS59oVCQHAKCwSKRPND05t/JS9/zznGel4ec se5Q== X-Forwarded-Encrypted: i=1; AJvYcCVlGlGZSQtkS7thHRlIa2szC1mrg+ZorvJPFfkFQ6atLKhguFeLgsOEoChbC8lFqq9DQBwfRdHozU8+YCM=@vger.kernel.org X-Gm-Message-State: AOJu0YzCm0Lv9EM+JNRMcfR/3vXCLoVkZvQ2qeeHn8Il5Jr5LQeklCwk FnTYn85tDIiJheWlxHfv/bo+KVd0/rl83paEErZFAdWRNM+3PkKYNC6bqg== X-Gm-Gg: ASbGnctRUZt4CiTJ/p+65g5oBZr3WehHM/a+v8PP2lfiEdie8M5ZRB2dzmhfnbuEKw7 7NmotKu7o7r42xMkrc345r+4K8I5HtySEaRRPhfimPbZSs4cFCjP1lCVSZbJHhs85z+45KbHdbD Kk753JJHosm0oj++7uX7R9WRJQA0pJLFFBdFQju9A/SjcDrzym88WdVOTQRhbQ9T1jgLaeXIpsZ LuQWGZ3mCuQFm+46GKbhkCqEXt7GtqXdP32jx2at6TkiZNH9KqY50x9P8+6aq/LiED3j6y944PD x12M/ijpIn7DuQZOCqscFQPgPFrpeVLDmmkGU/RmzVv9Q6frtMxBt3IdAkgAebomZ9ASp4jl2rt nFJvn8mHuoN/0+mFLfDViaw== X-Google-Smtp-Source: AGHT+IHblh0TlLPZ43+xMrhkpG+KkUIQT9tbXvVKDpewT/2IX8Y/8KH0Ot/MbNxqkdQ9EYAQ8UxUeA== X-Received: by 2002:a05:6512:3da3:b0:545:296e:ac28 with SMTP id 2adb3069b0e04-54990e67291mr7588998e87.24.1741715403240; Tue, 11 Mar 2025 10:50:03 -0700 (PDT) Received: from abj-NUC9VXQNX.. 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.50.01 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:50:02 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 09/11] rust: dma: use `dma::Device` in `CoherentAllocation` Date: Tue, 11 Mar 2025 19:48:05 +0200 Message-ID: <20250311174930.2348813-10-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Danilo Krummrich Require a `&dyn dma::Device` in `CoherentAllocation`, such that DMA memory can only be allocated with devices on potentially DMA capable busses. Signed-off-by: Danilo Krummrich Signed-off-by: Abdiel Janulgue --- rust/kernel/dma.rs | 16 ++++++++-------- samples/rust/rust_dma.rs | 2 +- 2 files changed, 9 insertions(+), 9 deletions(-) diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index ac3ec0042327..d0c6569cfc70 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -57,10 +57,9 @@ fn dma_set_mask(&mut self, mask: u64) -> Result { /// # Examples /// /// ``` -/// use kernel::device::Device; -/// use kernel::dma::{attrs::*, CoherentAllocation}; +/// use kernel::dma::{attrs::*, Device, CoherentAllocation}; /// -/// # fn test(dev: &Device) -> Result { +/// # fn test(dev: &dyn Device) -> Result { /// let attribs =3D DMA_ATTR_FORCE_CONTIGUOUS | DMA_ATTR_NO_WARN; /// let c: CoherentAllocation =3D /// CoherentAllocation::alloc_attrs(dev, 4, GFP_KERNEL, attribs)?; @@ -178,16 +177,15 @@ impl CoherentAllocation { /// # Examples /// /// ``` - /// use kernel::device::Device; - /// use kernel::dma::{attrs::*, CoherentAllocation}; + /// use kernel::dma::{attrs::*, Device, CoherentAllocation}; /// - /// # fn test(dev: &Device) -> Result { + /// # fn test(dev: &dyn Device) -> Result { /// let c: CoherentAllocation =3D /// CoherentAllocation::alloc_attrs(dev, 4, GFP_KERNEL, DMA_ATTR_N= O_WARN)?; /// # Ok::<(), Error>(()) } /// ``` pub fn alloc_attrs( - dev: &device::Device, + dev: &dyn Device, count: usize, gfp_flags: kernel::alloc::Flags, dma_attrs: Attrs, @@ -197,6 +195,8 @@ pub fn alloc_attrs( "It doesn't make sense for the allocated type to be a ZST" ); =20 + let dev =3D dev.as_ref(); + let size =3D count .checked_mul(core::mem::size_of::()) .ok_or(EOVERFLOW)?; @@ -229,7 +229,7 @@ pub fn alloc_attrs( /// Performs the same functionality as [`CoherentAllocation::alloc_att= rs`], except the /// `dma_attrs` is 0 by default. pub fn alloc_coherent( - dev: &device::Device, + dev: &dyn Device, count: usize, gfp_flags: kernel::alloc::Flags, ) -> Result> { diff --git a/samples/rust/rust_dma.rs b/samples/rust/rust_dma.rs index 1740140faba6..4c7ebf66647a 100644 --- a/samples/rust/rust_dma.rs +++ b/samples/rust/rust_dma.rs @@ -52,7 +52,7 @@ fn probe(pdev: &mut pci::Device, _info: &Self::IdInfo) ->= Result> dev_info!(pdev.as_ref(), "Probe DMA test driver.\n"); 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.50.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:50:04 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 10/11] rust: samples: dma: set DMA mask Date: Tue, 11 Mar 2025 19:48:06 +0200 Message-ID: <20250311174930.2348813-11-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Danilo Krummrich Set a DMA mask for the `pci::Device` in the Rust DMA sample driver. Signed-off-by: Danilo Krummrich Signed-off-by: Abdiel Janulgue --- samples/rust/rust_dma.rs | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-) diff --git a/samples/rust/rust_dma.rs b/samples/rust/rust_dma.rs index 4c7ebf66647a..39b6050aa3b6 100644 --- a/samples/rust/rust_dma.rs +++ b/samples/rust/rust_dma.rs @@ -4,7 +4,12 @@ //! //! To make this driver probe, QEMU must be run with `-device pci-testdev`. =20 -use kernel::{bindings, dma::CoherentAllocation, pci, prelude::*}; +use kernel::{ + bindings, + dma::{CoherentAllocation, Device}, + pci, + prelude::*, +}; =20 struct DmaSampleDriver { pdev: pci::Device, @@ -51,6 +56,8 @@ impl pci::Driver for DmaSampleDriver { fn probe(pdev: &mut pci::Device, _info: &Self::IdInfo) -> Result>> { dev_info!(pdev.as_ref(), "Probe DMA test driver.\n"); =20 + pdev.dma_set_mask_and_coherent(kernel::dma::dma_bit_mask(64))?; + let ca: CoherentAllocation =3D CoherentAllocation::alloc_coherent(pdev, TEST_VALUES.len(), GF= P_KERNEL)?; =20 --=20 2.43.0 From nobody Sun Feb 8 17:47:44 2026 Received: from mail-lf1-f46.google.com (mail-lf1-f46.google.com [209.85.167.46]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 21BD5264A84; Tue, 11 Mar 2025 17:50:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.46 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715410; cv=none; b=sFjOVDCROVwtLJzc3Vs8WX3xRDe1XqhJo/ox4wH0czd1C4AN5I9VEMxJM70yRIUSHNc2RD/tWV47QMjz5PWfrRvLu5K+9SScWrnDhVeIdFgMjxUbEMdRKGbiuWjN3vEfnjfiE/9mp+hpAgi4zFdwjrV8GbiakqzNn61kl8pYv1A= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741715410; c=relaxed/simple; bh=964LyMRqlPXEPxt4dRUtburkX8rzYyxtJ+Zd6YPN9n8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=S7k+3lynup3Xfa5gu6qWnb7Clj1jSPJyn2pajLNMdMx0A4LS/gsTjpV8aWsy1POEjQo1eBjkxZcBAQ7AiJ4f6G3lH3pY/RrzFfeXUdZXRT07PcTa+eXG6LJX1h3pcHCcvv0g6JkLZ28/+7Ow9jj4gYwhdD/5sQOSzja6VkA7yN0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com; spf=pass smtp.mailfrom=gmail.com; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b=QwoAgrlS; arc=none smtp.client-ip=209.85.167.46 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=gmail.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=gmail.com header.i=@gmail.com header.b="QwoAgrlS" Received: by mail-lf1-f46.google.com with SMTP id 2adb3069b0e04-5498d2a8b89so5813146e87.1; Tue, 11 Mar 2025 10:50:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1741715407; x=1742320207; darn=vger.kernel.org; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:from:to:cc:subject:date :message-id:reply-to; bh=Uyciabioh/RTBRWZFgAXOHCv2udpm7yTbk+rfqYhebY=; b=QwoAgrlS0hZTDzA4IQrgJBKr/u1qc8yDiUQtyDY5M0PkyMipQJ5i/541MRi2YKRYJk /MfSK7pQnaIZg1+qV97GYGUbJoKNlHUDiRNYJx9NHIkLmv9yie9u/doFJpKAKlqpmQee /rQFygLrk2mAg+QuaP87rQspajvigs181oF/UBdI0lo8wJrUJDMKVU5grF1QR89vJr5Q DzFOYpduUToa7VlQTjPG4Iz3Ptk941Aqx+vy8vCvtK0rUwf6dAjJIU6lLO1WfbZZJwDX kuWWebeQn/X6p8wFW/CZJf/ETst2xtSN1fU6Lk7SOU/Ovntjulgc+aaBoEW6YF6RFrNh RayA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741715407; x=1742320207; h=content-transfer-encoding:mime-version:references:in-reply-to :message-id:date:subject:cc:to:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=Uyciabioh/RTBRWZFgAXOHCv2udpm7yTbk+rfqYhebY=; b=JnBarR6RM+cjHlwMoBiM/wjho8yA+9SmwFE1hraPZvvbcWG2P+eH7vWxbSOVCBiEjN I36rfx9tctEQ/dwY4N64/omENQTkq0rcAh6LVxgKLmMg1T87OMQJgnmZxVVCR7SczZfP gwHfksY/SL6AiWFn1iFBmdHU/B52woomVaxGCpR6InAjrUfaM43VlKMAFiEwxr0bfUlw g/+PDpNAOFmff49KX2KLbiGmXfJLR3fW+SWlltToV7IrbzOHg2EC+12/5bGAIU5+6Bkw pXtNdfM5xLjEFj762PUUMwZLBx1ApzGBVsf2QAi5K0rUBKc7sl9v0E8mrbyHVK3Q9ITp k46w== X-Forwarded-Encrypted: i=1; AJvYcCVjgYctFh+1FQOR5jezPRFqbUzKUligcRq5j2M4RpGgXoNloOXzznUfpYIDodJ0M5Ht7oD0wboG3bhCj8Q=@vger.kernel.org X-Gm-Message-State: AOJu0YyYigqN6UwFxlfG/aDzmKbTyK4WiAbwNHLJmDHgKKso6WZGwHuV 3l8akpbMJJ5GRLuEE/mXOxNlUnKnhrw+lFz6f+5oe8SPQXPlO4Bw/ZyrnQ== X-Gm-Gg: ASbGnct9ncA6RnzI8buOgq/1lVJmF2TbvsyiVIiVhb5Pf71FsT61D0Ok9ASQX/3+Mrh 4/z4ZEbrIWUQGgtGT10ZKxaX7GBxSpVhBFKemM+sXbT/c15TwrwHB5PQLh/zaJMIsa2+ohaOoRz Hibuc1NQU0FBpNCbnEHyQ/TZYCmQKHGnn1jq8et1HBCxwujj3Ygu0hJMyFRoL26Q/nxgUV1Dd3V cSSjxSm9zhkbOdPhrHcmyIJh2SCC8U8TZT6Sa2YLsFUSm8e9tjyNk36/tgVawRFH4X5T4JOPFos etxpJF72NRRAr1l+n94dSL1VF1mcNkNFFzpixTU5/icJf3w+PmYNOUBWzyQS4ZneN9NUnqeUkwk 3+SBRQZMAO/XygTVOK3WeLw== X-Google-Smtp-Source: AGHT+IEJad4gl+z0QS4ewlzZ4karifVvk4Su2qy2hDsPEF00+XFLaO/pmT6m2hKmYpP7qT9AMIlM2A== X-Received: by 2002:a05:6512:2393:b0:545:2950:5360 with SMTP id 2adb3069b0e04-54990e5e2a1mr6250883e87.22.1741715406926; Tue, 11 Mar 2025 10:50:06 -0700 (PDT) Received: from abj-NUC9VXQNX.. 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[84.248.220.251]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498ae4465fsm1921728e87.26.2025.03.11.10.50.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 10:50:05 -0700 (PDT) From: Abdiel Janulgue To: rust-for-linux@vger.kernel.org, daniel.almeida@collabora.com, dakr@kernel.org, robin.murphy@arm.com, aliceryhl@google.com Cc: Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?UTF-8?q?Bj=C3=B6rn=20Roy=20Baron?= , Benno Lossin , Andreas Hindborg , Trevor Gross , Valentin Obst , linux-kernel@vger.kernel.org (open list), Christoph Hellwig , Marek Szyprowski , airlied@redhat.com, iommu@lists.linux.dev (open list:DMA MAPPING HELPERS), Abdiel Janulgue Subject: [PATCH v14 11/11] rust: dma: add as_slice/write functions for CoherentAllocation Date: Tue, 11 Mar 2025 19:48:07 +0200 Message-ID: <20250311174930.2348813-12-abdiel.janulgue@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> References: <20250311174930.2348813-1-abdiel.janulgue@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add unsafe accessors for the region for reading or writing large blocks of data. Signed-off-by: Abdiel Janulgue --- rust/kernel/dma.rs | 87 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 87 insertions(+) diff --git a/rust/kernel/dma.rs b/rust/kernel/dma.rs index d0c6569cfc70..514fbb27c607 100644 --- a/rust/kernel/dma.rs +++ b/rust/kernel/dma.rs @@ -253,6 +253,93 @@ pub fn dma_handle(&self) -> bindings::dma_addr_t { self.dma_handle } =20 + /// Returns the data from the region starting from `offset` as a slice. + /// `offset` and `count` are in units of `T`, not the number of bytes. + /// + /// Due to the safety requirements of slice, the caller should conside= r that the region could + /// be modified by the device at anytime. For ringbuffer type of r/w a= ccess or use-cases where + /// the pointer to the live data is needed, `start_ptr()` or `start_pt= r_mut()` could be + /// used instead. + /// + /// # Safety + /// + /// * Callers must ensure that no hardware operations that involve the= buffer are currently + /// taking place while the returned slice is live. + /// * Callers must ensure that this call does not race with a write to= the same region while + /// while the returned slice is live. + pub unsafe fn as_slice(&self, offset: usize, count: usize) -> Result<&= [T]> { + let end =3D offset.checked_add(count).ok_or(EOVERFLOW)?; + if end >=3D self.count { + return Err(EINVAL); + } + // SAFETY: + // - The pointer is valid due to type invariant on `CoherentAlloca= tion`, + // we've just checked that the range and index is within bounds. T= he immutability of the + // of data is also guaranteed by the safety requirements of the fu= nction. + // - `offset` can't overflow since it is smaller than `self.count`= and we've checked + // that `self.count` won't overflow early in the constructor. + Ok(unsafe { core::slice::from_raw_parts(self.cpu_addr.add(offset),= count) }) + } + + /// Performs the same functionality as [`CoherentAllocation::as_slice`= ], except that a mutable + /// slice is returned. + /// + /// # Safety + /// + /// * Callers must ensure that no hardware operations that involve the= buffer are currently + /// taking place while the returned slice is live. + /// * Callers must ensure that this call does not race with a read or = write to the same region + /// while the returned slice is live. + pub unsafe fn as_slice_mut(&self, offset: usize, count: usize) -> Resu= lt<&mut [T]> { + let end =3D offset.checked_add(count).ok_or(EOVERFLOW)?; + if end >=3D self.count { + return Err(EINVAL); + } + // SAFETY: + // - The pointer is valid due to type invariant on `CoherentAlloca= tion`, + // we've just checked that the range and index is within bounds. T= he immutability of the + // of data is also guaranteed by the safety requirements of the fu= nction. + // - `offset` can't overflow since it is smaller than `self.count`= and we've checked + // that `self.count` won't overflow early in the constructor. + Ok(unsafe { core::slice::from_raw_parts_mut(self.cpu_addr.add(offs= et), count) }) + } + + /// Writes data to the region starting from `offset`. `offset` is in u= nits of `T`, not the + /// number of bytes. + /// + /// # Safety + /// + /// * Callers must ensure that no hardware operations that involve the= buffer overlaps with + /// this write. + /// * Callers must ensure that this call does not race with a read or = write to the same region + /// that overlaps with this write. + /// + /// # Examples + /// + /// ``` + /// # fn test(alloc: &mut kernel::dma::CoherentAllocation) -> Resu= lt { + /// let somedata: [u8; 4] =3D [0xf; 4]; + /// let buf: &[u8] =3D &somedata; + /// // SAFETY: No hw operation on the device and no other r/w access t= o the region at this point. + /// unsafe { alloc.write(buf, 0)?; } + /// # Ok::<(), Error>(()) } + /// ``` + pub unsafe fn write(&self, src: &[T], offset: usize) -> Result { + let end =3D offset.checked_add(src.len()).ok_or(EOVERFLOW)?; + if end >=3D self.count { + return Err(EINVAL); + } + // SAFETY: + // - The pointer is valid due to type invariant on `CoherentAlloca= tion` + // and we've just checked that the range and index is within bound= s. + // - `offset` can't overflow since it is smaller than `self.count`= and we've checked + // that `self.count` won't overflow early in the constructor. + unsafe { + core::ptr::copy_nonoverlapping(src.as_ptr(), self.cpu_addr.add= (offset), src.len()) + }; + Ok(()) + } + /// Returns a pointer to an element from the region with bounds checki= ng. `offset` is in /// units of `T`, not the number of bytes. /// --=20 2.43.0