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Tue, 11 Mar 2025 12:02:19 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 11 Mar 2025 20:01:51 +0100 Subject: [PATCH v4 01/19] dt-bindings: display/msm: dsi-phy-7nm: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250311-b4-sm8750-display-v4-1-da6b3e959c76@linaro.org> References: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> In-Reply-To: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DSI PHY v7.0 for Qualcomm SM8750 SoC which is quite different from previous (SM8650) generation. Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml= b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml index 321470435e654f1d569fc54f6a810e3f70fb168c..4ac262d3feb1293c65633f3b804= b4f34c518400c 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-phy-7nm.yaml @@ -23,6 +23,7 @@ properties: - qcom,sm8450-dsi-phy-5nm - qcom,sm8550-dsi-phy-4nm - qcom,sm8650-dsi-phy-4nm + - qcom,sm8750-dsi-phy-3nm =20 reg: items: --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A7B1D264A81 for ; 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Tue, 11 Mar 2025 12:02:21 -0700 (PDT) Received: from [127.0.1.1] ([178.197.198.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ce70d13b4sm127681155e9.38.2025.03.11.12.02.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 12:02:21 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 11 Mar 2025 20:01:52 +0100 Subject: [PATCH v4 02/19] dt-bindings: display/msm: dsi-controller-main: Add SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250311-b4-sm8750-display-v4-2-da6b3e959c76@linaro.org> References: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> In-Reply-To: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DSI controller for Qualcomm SM8750 SoC which is quite different from previous (SM8650) generation. It does not allow the display clock controller clocks like "byte" and "pixel" to be reparented to DSI PHY PLLs while the DSI PHY PLL is not configured (not prepared, rate not set). Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure. These clocks are now inputs to the DSI controller device. Except that SM8750 DSI comes with several differences, new blocks and changes in registers, making it incompatible with SM8650. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- .../bindings/display/msm/dsi-controller-main.yaml | 54 ++++++++++++++++++= ++-- 1 file changed, 49 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/display/msm/dsi-controller-m= ain.yaml b/Documentation/devicetree/bindings/display/msm/dsi-controller-mai= n.yaml index 2aab33cd0017cd4a0c915b7297bb3952e62561fa..8ecb2d8e296edf555df7380eac2= 84b41a3f000a5 100644 --- a/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml +++ b/Documentation/devicetree/bindings/display/msm/dsi-controller-main.yaml @@ -40,6 +40,7 @@ properties: - qcom,sm8450-dsi-ctrl - qcom,sm8550-dsi-ctrl - qcom,sm8650-dsi-ctrl + - qcom,sm8750-dsi-ctrl - const: qcom,mdss-dsi-ctrl - enum: - qcom,dsi-ctrl-6g-qcm2290 @@ -68,11 +69,11 @@ properties: - mnoc:: MNOC clock - pixel:: Display pixel clock. minItems: 3 - maxItems: 9 + maxItems: 12 =20 clock-names: minItems: 3 - maxItems: 9 + maxItems: 12 =20 phys: maxItems: 1 @@ -107,7 +108,8 @@ properties: minItems: 2 maxItems: 4 description: | - Parents of "byte" and "pixel" for the given platform. + For DSI on SM8650 and older: parents of "byte" and "pixel" for the g= iven + platform. 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DisplayPort controller for Qualcomm SM8750 SoC which so far looks fully compatible with earlier SM8650 variant - both are of version v1.5.1 of the IP block. Datasheet also mentions that both support 4x MST for DPTX0 and 2x MST for DPTX1. Acked-by: Rob Herring (Arm) Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. Extend commit msg --- Documentation/devicetree/bindings/display/msm/dp-controller.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/dp-controller.ya= ml b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml index e00b88332f2fed2fc33f6d72c5cc3d827cd7594e..a4bf9e07a28355c0391d1757fab= 16ebe5ff14a44 100644 --- a/Documentation/devicetree/bindings/display/msm/dp-controller.yaml +++ b/Documentation/devicetree/bindings/display/msm/dp-controller.yaml @@ -37,6 +37,10 @@ properties: - qcom,sm8450-dp - qcom,sm8550-dp - const: qcom,sm8350-dp + - items: + - enum: + - qcom,sm8750-dp + - const: qcom,sm8650-dp =20 reg: minItems: 4 --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD9B0265607 for ; Tue, 11 Mar 2025 19:02:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DPU for Qualcomm SM8750 SoC which has several differences, new blocks and changes in registers, making it incompatible with SM8650. Acked-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.= yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml index 01cf79bd754b491349c52c5aef49ba06e835d0bf..0a46120dd8680371ed031f77738= 59716f49c3aa1 100644 --- a/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8650-dpu.yaml @@ -16,6 +16,7 @@ properties: enum: - qcom,sa8775p-dpu - qcom,sm8650-dpu + - qcom,sm8750-dpu - qcom,x1e80100-dpu =20 reg: --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wm1-f53.google.com (mail-wm1-f53.google.com [209.85.128.53]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CA5E4265629 for ; Tue, 11 Mar 2025 19:02:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add MDSS/MDP display subsystem for Qualcomm SM8750 SoC, next generation with two revisions up of the IP block comparing to SM8650. Reviewed-by: Rob Herring (Arm) Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. Properly described interconnects 2. Use only one compatible and contains for the sub-blocks (Rob) --- .../bindings/display/msm/qcom,sm8750-mdss.yaml | 470 +++++++++++++++++= ++++ 1 file changed, 470 insertions(+) diff --git a/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss= .yaml b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml new file mode 100644 index 0000000000000000000000000000000000000000..72c70edc1fb01c61f8aad24fdb5= 8bfb4f62a6e34 --- /dev/null +++ b/Documentation/devicetree/bindings/display/msm/qcom,sm8750-mdss.yaml @@ -0,0 +1,470 @@ +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/msm/qcom,sm8750-mdss.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SM8750 Display MDSS + +maintainers: + - Krzysztof Kozlowski + +description: + SM8650 MSM Mobile Display Subsystem(MDSS), which encapsulates sub-blocks= like + DPU display controller, DSI and DP interfaces etc. + +$ref: /schemas/display/msm/mdss-common.yaml# + +properties: + compatible: + const: qcom,sm8750-mdss + + clocks: + items: + - description: Display AHB + - description: Display hf AXI + - description: Display core + + iommus: + maxItems: 1 + + interconnects: + items: + - description: Interconnect path from mdp0 port to the data bus + - description: Interconnect path from CPU to the reg bus + + interconnect-names: + items: + - const: mdp0-mem + - const: cpu-cfg + +patternProperties: + "^display-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sm8750-dpu + + "^displayport-controller@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sm8750-dp + + "^dsi@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + contains: + const: qcom,sm8750-dsi-ctrl + + "^phy@[0-9a-f]+$": + type: object + additionalProperties: true + properties: + compatible: + const: qcom,sm8750-dsi-phy-3nm + +required: + - compatible + +unevaluatedProperties: false + +examples: + - | + #include + #include + #include + #include + #include + #include + + display-subsystem@ae00000 { + compatible =3D "qcom,sm8750-mdss"; + reg =3D <0x0ae00000 0x1000>; + reg-names =3D "mdss"; + + interrupts =3D ; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_mdp_clk>; + + interconnects =3D <&mmss_noc MASTER_MDP QCOM_ICC_TAG_ALWAYS + &mc_virt SLAVE_EBI1 QCOM_ICC_TAG_ALWAYS>, + <&gem_noc MASTER_APPSS_PROC QCOM_ICC_TAG_ACTIV= E_ONLY + &config_noc SLAVE_DISPLAY_CFG QCOM_ICC_TAG_AC= TIVE_ONLY>; + interconnect-names =3D "mdp0-mem", + "cpu-cfg"; + + resets =3D <&disp_cc_mdss_core_bcr>; + + power-domains =3D <&mdss_gdsc>; + + iommus =3D <&apps_smmu 0x800 0x2>; + + interrupt-controller; + #interrupt-cells =3D <1>; + + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges; + + display-controller@ae01000 { + compatible =3D "qcom,sm8750-dpu"; + reg =3D <0x0ae01000 0x93000>, + <0x0aeb0000 0x2008>; + reg-names =3D "mdp", + "vbif"; + + interrupts-extended =3D <&mdss 0>; + + clocks =3D <&gcc_disp_hf_axi_clk>, + <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_mdp_lut_clk>, + <&disp_cc_mdss_mdp_clk>, + <&disp_cc_mdss_vsync_clk>; + clock-names =3D "nrt_bus", + "iface", + "lut", + "core", + "vsync"; + + assigned-clocks =3D <&disp_cc_mdss_vsync_clk>; + assigned-clock-rates =3D <19200000>; + + operating-points-v2 =3D <&mdp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + dpu_intf1_out: endpoint { + remote-endpoint =3D <&mdss_dsi0_in>; + }; + }; + + port@1 { + reg =3D <1>; + + dpu_intf2_out: endpoint { + remote-endpoint =3D <&mdss_dsi1_in>; + }; + }; + + port@2 { + reg =3D <2>; + + dpu_intf0_out: endpoint { + remote-endpoint =3D <&mdss_dp0_in>; + }; + }; + }; + + mdp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-207000000 { + opp-hz =3D /bits/ 64 <207000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-337000000 { + opp-hz =3D /bits/ 64 <337000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-417000000 { + opp-hz =3D /bits/ 64 <417000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-532000000 { + opp-hz =3D /bits/ 64 <532000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + + opp-575000000 { + opp-hz =3D /bits/ 64 <575000000>; + required-opps =3D <&rpmhpd_opp_nom_l1>; + }; + }; + }; + + dsi@ae94000 { + compatible =3D "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl= "; + reg =3D <0x0ae94000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 4>; + + clocks =3D <&disp_cc_mdss_byte0_clk>, + <&disp_cc_mdss_byte0_intf_clk>, + <&disp_cc_mdss_pclk0_clk>, + <&disp_cc_mdss_esc0_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi0_phy 1>, + <&mdss_dsi0_phy 0>, + <&disp_cc_esync0_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte0_clk_src>, + <&disp_cc_mdss_pclk0_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi0_phy>; + phy-names =3D "dsi"; + + vdda-supply =3D <&vreg_l3g_1p2>; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi0_in: endpoint { + remote-endpoint =3D <&dpu_intf1_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi0_out: endpoint { + remote-endpoint =3D <&panel0_in>; + data-lanes =3D <0 1 2 3>; + }; + }; + }; + + mdss_dsi_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-187500000 { + opp-hz =3D /bits/ 64 <187500000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-300000000 { + opp-hz =3D /bits/ 64 <300000000>; + required-opps =3D <&rpmhpd_opp_svs>; + }; + + opp-358000000 { + opp-hz =3D /bits/ 64 <358000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + }; + }; + + mdss_dsi0_phy: phy@ae95000 { + compatible =3D "qcom,sm8750-dsi-phy-3nm"; + reg =3D <0x0ae95000 0x200>, + <0x0ae95200 0x280>, + <0x0ae95500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + vdds-supply =3D <&vreg_l3i_0p88>; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + + dsi@ae96000 { + compatible =3D "qcom,sm8750-dsi-ctrl", "qcom,mdss-dsi-ctrl= "; + reg =3D <0x0ae96000 0x400>; + reg-names =3D "dsi_ctrl"; + + interrupts-extended =3D <&mdss 5>; + + clocks =3D <&disp_cc_mdss_byte1_clk>, + <&disp_cc_mdss_byte1_intf_clk>, + <&disp_cc_mdss_pclk1_clk>, + <&disp_cc_mdss_esc1_clk>, + <&disp_cc_mdss_ahb_clk>, + <&gcc_disp_hf_axi_clk>, + <&mdss_dsi1_phy 1>, + <&mdss_dsi1_phy 0>, + <&disp_cc_esync1_clk>, + <&disp_cc_osc_clk>, + <&disp_cc_mdss_byte1_clk_src>, + <&disp_cc_mdss_pclk1_clk_src>; + clock-names =3D "byte", + "byte_intf", + "pixel", + "core", + "iface", + "bus", + "dsi_pll_pixel", + "dsi_pll_byte", + "esync", + "osc", + "byte_src", + "pixel_src"; + + operating-points-v2 =3D <&mdss_dsi_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&mdss_dsi1_phy>; + phy-names =3D "dsi"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + mdss_dsi1_in: endpoint { + remote-endpoint =3D <&dpu_intf2_out>; + }; + }; + + port@1 { + reg =3D <1>; + + mdss_dsi1_out: endpoint { + }; + }; + }; + }; + + mdss_dsi1_phy: phy@ae97000 { + compatible =3D "qcom,sm8750-dsi-phy-3nm"; + reg =3D <0x0ae97000 0x200>, + <0x0ae97200 0x280>, + <0x0ae97500 0x400>; + reg-names =3D "dsi_phy", + "dsi_phy_lane", + "dsi_pll"; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&rpmhcc RPMH_CXO_CLK>; + clock-names =3D "iface", + "ref"; + + #clock-cells =3D <1>; + #phy-cells =3D <0>; + }; + + displayport-controller@af54000 { + compatible =3D "qcom,sm8750-dp", "qcom,sm8650-dp"; + reg =3D <0xaf54000 0x104>, + <0xaf54200 0xc0>, + <0xaf55000 0x770>, + <0xaf56000 0x9c>, + <0xaf57000 0x9c>; + + interrupts-extended =3D <&mdss 12>; + + clocks =3D <&disp_cc_mdss_ahb_clk>, + <&disp_cc_mdss_dptx0_aux_clk>, + <&disp_cc_mdss_dptx0_link_clk>, + <&disp_cc_mdss_dptx0_link_intf_clk>, + <&disp_cc_mdss_dptx0_pixel0_clk>; + clock-names =3D "core_iface", + "core_aux", + "ctrl_link", + "ctrl_link_iface", + "stream_pixel"; + + assigned-clocks =3D <&disp_cc_mdss_dptx0_link_clk_src>, + <&disp_cc_mdss_dptx0_pixel0_clk_src>; + assigned-clock-parents =3D <&usb_dp_qmpphy QMP_USB43DP_DP_= LINK_CLK>, + <&usb_dp_qmpphy QMP_USB43DP_DP_VC= O_DIV_CLK>; + + operating-points-v2 =3D <&dp_opp_table>; + + power-domains =3D <&rpmhpd RPMHPD_MMCX>; + + phys =3D <&usb_dp_qmpphy QMP_USB43DP_DP_PHY>; + phy-names =3D "dp"; + + #sound-dai-cells =3D <0>; + + dp_opp_table: opp-table { + compatible =3D "operating-points-v2"; + + opp-192000000 { + opp-hz =3D /bits/ 64 <192000000>; + required-opps =3D <&rpmhpd_opp_low_svs_d1>; + }; + + opp-270000000 { + opp-hz =3D /bits/ 64 <270000000>; + required-opps =3D <&rpmhpd_opp_low_svs>; + }; + + opp-540000000 { + opp-hz =3D /bits/ 64 <540000000>; + required-opps =3D <&rpmhpd_opp_svs_l1>; + }; + + opp-810000000 { + opp-hz =3D /bits/ 64 <810000000>; + required-opps =3D <&rpmhpd_opp_nom>; + }; + }; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B The set_active_pipes() callback configures CTL_FETCH_PIPE_ACTIVE and newer DPU v12.0 comes with CTL_PIPE_ACTIVE, thus rename it to set_active_fetch_pipes() to better match the purpose. Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. New patch --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 12 ++++++------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 +++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 2 +- 3 files changed, 10 insertions(+), 10 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 0714936d883523e5c53bfb42f932234db76c58db..2d7af6fff2708c12520a78cc6c9= 79b9930dffc95 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -445,9 +445,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, =20 uint32_t lm_idx; bool bg_alpha_enable =3D false; - DECLARE_BITMAP(fetch_active, SSPP_MAX); + DECLARE_BITMAP(active_fetch, SSPP_MAX); =20 - memset(fetch_active, 0, sizeof(fetch_active)); + memset(active_fetch, 0, sizeof(active_fetch)); drm_atomic_crtc_for_each_plane(plane, crtc) { state =3D plane->state; if (!state) @@ -464,7 +464,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (pstate->stage =3D=3D DPU_STAGE_BASE && format->alpha_enable) bg_alpha_enable =3D true; =20 - set_bit(pstate->pipe.sspp->idx, fetch_active); + set_bit(pstate->pipe.sspp->idx, active_fetch); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -472,7 +472,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, &pstate->pipe, 0, stage_cfg); =20 if (pstate->r_pipe.sspp) { - set_bit(pstate->r_pipe.sspp->idx, fetch_active); + set_bit(pstate->r_pipe.sspp->idx, active_fetch); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -492,8 +492,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, } } =20 - if (ctl->ops.set_active_pipes) - ctl->ops.set_active_pipes(ctl, fetch_active); + if (ctl->ops.set_active_fetch_pipes) + ctl->ops.set_active_fetch_pipes(ctl, active_fetch); =20 _dpu_crtc_program_lm_output_roi(crtc); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 216dfcabcb92d410ce185c0d34db69c99930d2b8..951d5dccab6faf34a519d066835= 14aea1ee6ef60 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -698,8 +698,8 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_= ctl *ctx, } } =20 -static void dpu_hw_ctl_set_fetch_pipe_active(struct dpu_hw_ctl *ctx, - unsigned long *fetch_active) +static void dpu_hw_ctl_set_active_fetch_pipes(struct dpu_hw_ctl *ctx, + unsigned long *fetch_active) { int i; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Resetting mixers should also include resetting active fetch pipes. Fixes: ae4d721ce100 ("drm/msm/dpu: add an API to reset the encoder related = hw blocks") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index 284e69bb47c179ba62363b2df2cebd5172c44f8a..ccf492f27140a2841b454d413e8= 85e4bbd9ee497 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2188,6 +2188,9 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) /* clear all blendstages */ if (ctl->ops.setup_blendstage) ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); + + if (ctl->ops.set_active_fetch_pipes) + ctl->ops.set_active_fetch_pipes(ctl, NULL); } } =20 --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 09F56266562 for ; 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Tue, 11 Mar 2025 12:02:36 -0700 (PDT) Received: from [127.0.1.1] ([178.197.198.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ce70d13b4sm127681155e9.38.2025.03.11.12.02.34 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 12:02:35 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 11 Mar 2025 20:01:58 +0100 Subject: [PATCH v4 08/19] drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE on ctl_path reset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250311-b4-sm8750-display-v4-8-da6b3e959c76@linaro.org> References: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> In-Reply-To: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Resetting entire CTL path should also include resetting active fetch pipes. Fixes: e1a950eec256 ("drm/msm/dpu: add reset_intf_cfg operation for dpu_hw_= ctl") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 951d5dccab6faf34a519d06683514aea1ee6ef60..2ce59ba50ffa0d14eaa07e993fa= df0f218390ef1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -667,6 +667,9 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_= ctl *ctx, =20 dpu_hw_ctl_clear_all_blendstages(ctx); =20 + if (ctx->ops.set_active_fetch_pipes) + ctx->ops.set_active_fetch_pipes(ctx, NULL); + if (cfg->intf) { intf_active =3D DPU_REG_READ(c, CTL_INTF_ACTIVE); intf_active &=3D ~BIT(cfg->intf - INTF_0); --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wr1-f48.google.com (mail-wr1-f48.google.com [209.85.221.48]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 04C6A2661A5 for ; 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Tue, 11 Mar 2025 12:02:38 -0700 (PDT) Received: from [127.0.1.1] ([178.197.198.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ce70d13b4sm127681155e9.38.2025.03.11.12.02.36 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 12:02:37 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 11 Mar 2025 20:01:59 +0100 Subject: [PATCH v4 09/19] drm/msm/dpu: Clear CTL_FETCH_PIPE_ACTIVE before blend setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250311-b4-sm8750-display-v4-9-da6b3e959c76@linaro.org> References: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> In-Reply-To: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Before blend setup, all existing blend stages are cleared, so shall be active fetch pipes. Fixes: b3652e87c03c ("drm/msm/disp/dpu1: add support to program fetch activ= e in ctl path") Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 2d7af6fff2708c12520a78cc6c979b9930dffc95..a4b0fe0d9899b32141928f0b6a1= 6503a49b3c27a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -519,6 +519,8 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) if (mixer[i].lm_ctl->ops.clear_all_blendstages) mixer[i].lm_ctl->ops.clear_all_blendstages( mixer[i].lm_ctl); + if (mixer[i].lm_ctl->ops.set_active_fetch_pipes) + mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL); } =20 /* initialize stage cfg */ --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wr1-f49.google.com (mail-wr1-f49.google.com [209.85.221.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F2346266B60 for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Drop comments about SoC before each 'struct dpu_lm_sub_blks' for given SoC because it's duplicating the actual name of structure. Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 8 -------- 1 file changed, 8 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 2db27c55787791309962acf796d5c49aaf018fc1..a310a5234e99ea4886e82ac2100= c4099e6a1841e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -331,8 +331,6 @@ static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D = _DMA_SBLK(); * MIXER sub blocks config *************************************************************/ =20 -/* MSM8998 */ - static const struct dpu_lm_sub_blks msm8998_lm_sblk =3D { .maxwidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .maxblendstages =3D 7, /* excluding base layer */ @@ -342,8 +340,6 @@ static const struct dpu_lm_sub_blks msm8998_lm_sblk =3D= { }, }; =20 -/* SDM845 */ - static const struct dpu_lm_sub_blks sdm845_lm_sblk =3D { .maxwidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, .maxblendstages =3D 11, /* excluding base layer */ @@ -353,8 +349,6 @@ static const struct dpu_lm_sub_blks sdm845_lm_sblk =3D { }, }; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add IDs for new blocks present in MDSS/MDP v12 for LM, DSC, PINGPONG and MERGE_3D blocks. Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 8d820cd1b5545d247515763039b341184e814e32..175639c8bfbb9bbd02ed35f1780= bcbd869f08c36 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -125,6 +125,7 @@ enum dpu_lm { LM_4, LM_5, LM_6, + LM_7, LM_MAX }; =20 @@ -169,6 +170,8 @@ enum dpu_dsc { DSC_3, DSC_4, DSC_5, + DSC_6, + DSC_7, DSC_MAX }; =20 @@ -185,6 +188,8 @@ enum dpu_pingpong { PINGPONG_3, PINGPONG_4, PINGPONG_5, + PINGPONG_6, + PINGPONG_7, PINGPONG_CWB_0, PINGPONG_CWB_1, PINGPONG_CWB_2, @@ -199,6 +204,7 @@ enum dpu_merge_3d { MERGE_3D_2, MERGE_3D_3, MERGE_3D_4, + MERGE_3D_5, MERGE_3D_MAX }; =20 --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wr1-f50.google.com (mail-wr1-f50.google.com [209.85.221.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A2962266F10 for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B MDSS/MDP v12 comes with new bits in flush registers (e.g. MDP_CTL_0_FLUSH) for Layer Mixer 6 and 7. Reviewed-by: Dmitry Baryshkov Reviewed-by: Jessica Zhang Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 6 ++++++ 1 file changed, 6 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 2ce59ba50ffa0d14eaa07e993fadf0f218390ef1..3e5e1e09e9d00ade74371489b2b= 4e50e648e2d16 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -261,6 +261,12 @@ static void dpu_hw_ctl_update_pending_flush_mixer(stru= ct dpu_hw_ctl *ctx, case LM_5: ctx->pending_flush_mask |=3D BIT(20); break; + case LM_6: + ctx->pending_flush_mask |=3D BIT(21); + break; + case LM_7: + ctx->pending_flush_mask |=3D BIT(27); + break; default: break; } --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wm1-f52.google.com (mail-wm1-f52.google.com [209.85.128.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id F298B2676CD for ; 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Tue, 11 Mar 2025 12:02:51 -0700 (PDT) Received: from [127.0.1.1] ([178.197.198.86]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43ce70d13b4sm127681155e9.38.2025.03.11.12.02.48 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 11 Mar 2025 12:02:50 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 11 Mar 2025 20:02:03 +0100 Subject: [PATCH v4 13/19] drm/msm/dsi/phy: Add support for SM8750 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250311-b4-sm8750-display-v4-13-da6b3e959c76@linaro.org> References: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> In-Reply-To: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark , Dmitry Baryshkov X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for DSI PHY v7.0 on Qualcomm SM8750 SoC which comes with an incompatible hardware interface change: ICODE_ACCUM_STATUS_LOW and ALOG_OBSV_BUS_STATUS_1 registers - their offsets were just switched. Currently these registers are not used in the driver, so the easiest is to document both but keep them commented out to avoid conflict. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. Fix pll freq check for clock inverters 160000000ULL -> 163000000ULL --- drivers/gpu/drm/msm/dsi/phy/dsi_phy.c | 2 + drivers/gpu/drm/msm/dsi/phy/dsi_phy.h | 1 + drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 79 ++++++++++++++++++= ++-- .../gpu/drm/msm/registers/display/dsi_phy_7nm.xml | 14 ++++ 4 files changed, 90 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.c index c0bcc68289633fd7506ce4f1f963655d862e8f08..60571237efc4d332959ac76ff1d= 6d6245f688469 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c @@ -593,6 +593,8 @@ static const struct of_device_id dsi_phy_dt_match[] =3D= { .data =3D &dsi_phy_4nm_8550_cfgs }, { .compatible =3D "qcom,sm8650-dsi-phy-4nm", .data =3D &dsi_phy_4nm_8650_cfgs }, + { .compatible =3D "qcom,sm8750-dsi-phy-3nm", + .data =3D &dsi_phy_3nm_8750_cfgs }, #endif {} }; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/ds= i/phy/dsi_phy.h index 1925418d9999a24263d6621299cae78f1fb9455c..7541ffde65218a28d4dde7cfc82= 46c0715b53ec6 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h @@ -61,6 +61,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs; extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs; +extern const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs; =20 struct msm_dsi_dphy_timing { u32 clk_zero; diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/ms= m/dsi/phy/dsi_phy_7nm.c index a92decbee5b5433853ed973747f7705d9079068d..b077d00e4c5dfcc81040fe3ec71= c43607749f26b 100644 --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c @@ -51,6 +51,8 @@ #define DSI_PHY_7NM_QUIRK_V4_3 BIT(3) /* Hardware is V5.2 */ #define DSI_PHY_7NM_QUIRK_V5_2 BIT(4) +/* Hardware is V7.0 */ +#define DSI_PHY_7NM_QUIRK_V7_0 BIT(5) =20 struct dsi_pll_config { bool enable_ssc; @@ -129,9 +131,30 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *= pll, struct dsi_pll_config dec_multiple =3D div_u64(pll_freq * multiplier, divider); dec =3D div_u64_rem(dec_multiple, multiplier, &frac); =20 - if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) + if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1) { config->pll_clock_inverters =3D 0x28; - else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (pll_freq < 163000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 175000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 325000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 350000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 650000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 700000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 1300000000ULL) + config->pll_clock_inverters =3D 0xa0; + else if (pll_freq < 2500000000ULL) + config->pll_clock_inverters =3D 0x20; + else if (pll_freq < 4000000000ULL) + config->pll_clock_inverters =3D 0x00; + else + config->pll_clock_inverters =3D 0x40; + } else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (pll_freq <=3D 1300000000ULL) config->pll_clock_inverters =3D 0xa0; else if (pll_freq <=3D 2500000000ULL) @@ -250,7 +273,8 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7= nm *pll) vco_config_1 =3D 0x01; } =20 - if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { if (pll->vco_current_rate < 1557000000ULL) vco_config_1 =3D 0x08; else @@ -620,6 +644,7 @@ static int dsi_7nm_pll_restore_state(struct msm_dsi_phy= *phy) static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) { struct dsi_pll_7nm *pll_7nm =3D to_pll_7nm(phy->vco_hw); + void __iomem *base =3D phy->base; u32 data =3D 0x0; /* internal PLL */ =20 DBG("DSI PLL%d", pll_7nm->phy->id); @@ -629,6 +654,9 @@ static int dsi_7nm_set_usecase(struct msm_dsi_phy *phy) break; case MSM_DSI_PHY_MASTER: pll_7nm->slave =3D pll_7nm_list[(pll_7nm->phy->id + 1) % DSI_MAX]; + /* v7.0: Enable ATB_EN0 and alternate clock output to external phy */ + if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) + writel(0x07, base + REG_DSI_7nm_PHY_CMN_CTRL_5); break; case MSM_DSI_PHY_SLAVE: data =3D 0x1; /* external PLL */ @@ -907,7 +935,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, =20 /* Request for REFGEN READY */ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { writel(0x1, phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); udelay(500); } @@ -941,7 +970,20 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, lane_ctrl0 =3D 0x1f; } =20 - if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { + if (phy->cphy_mode) { + /* TODO: different for second phy */ + vreg_ctrl_0 =3D 0x57; + vreg_ctrl_1 =3D 0x41; + glbl_rescode_top_ctrl =3D 0x3d; + glbl_rescode_bot_ctrl =3D 0x38; + } else { + vreg_ctrl_0 =3D 0x56; + vreg_ctrl_1 =3D 0x19; + glbl_rescode_top_ctrl =3D less_than_1500_mhz ? 0x3c : 0x03; + glbl_rescode_bot_ctrl =3D less_than_1500_mhz ? 0x38 : 0x3c; + } + } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { if (phy->cphy_mode) { vreg_ctrl_0 =3D 0x45; vreg_ctrl_1 =3D 0x41; @@ -1003,6 +1045,7 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy, =20 /* program CMN_CTRL_4 for minor_ver 2 chipsets*/ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0) || (readl(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) =3D=3D 0x20) writel(0x04, base + REG_DSI_7nm_PHY_CMN_CTRL_4); =20 @@ -1117,7 +1160,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *p= hy) =20 /* Turn off REFGEN Vote */ if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) || - (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) { + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) || + (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V7_0)) { writel(0x0, base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10); wmb(); /* Delay to ensure HW removes vote before PHY shut down */ @@ -1334,3 +1378,26 @@ const struct msm_dsi_phy_cfg dsi_phy_4nm_8650_cfgs = =3D { .num_dsi_phy =3D 2, .quirks =3D DSI_PHY_7NM_QUIRK_V5_2, }; + +const struct msm_dsi_phy_cfg dsi_phy_3nm_8750_cfgs =3D { + .has_phy_lane =3D true, + .regulator_data =3D dsi_phy_7nm_98000uA_regulators, + .num_regulators =3D ARRAY_SIZE(dsi_phy_7nm_98000uA_regulators), + .ops =3D { + .enable =3D dsi_7nm_phy_enable, + .disable =3D dsi_7nm_phy_disable, + .pll_init =3D dsi_pll_7nm_init, + .save_pll_state =3D dsi_7nm_pll_save_state, + .restore_pll_state =3D dsi_7nm_pll_restore_state, + .set_continuous_clock =3D dsi_7nm_set_continuous_clock, + }, + .min_pll_rate =3D 600000000UL, +#ifdef CONFIG_64BIT + .max_pll_rate =3D 5000000000UL, +#else + .max_pll_rate =3D ULONG_MAX, +#endif + .io_start =3D { 0xae95000, 0xae97000 }, + .num_dsi_phy =3D 2, + .quirks =3D DSI_PHY_7NM_QUIRK_V7_0, +}; diff --git a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml b/driver= s/gpu/drm/msm/registers/display/dsi_phy_7nm.xml index d2c8c46bb04159da6e539bfe80a4b5dc9ffdf367..4e5ac0f25dea856a49a1523f59c= 60b7f7769c1c2 100644 --- a/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml +++ b/drivers/gpu/drm/msm/registers/display/dsi_phy_7nm.xml @@ -26,6 +26,7 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/free= dreno/ rules-fd.xsd"> + @@ -191,11 +192,24 @@ xsi:schemaLocation=3D"https://gitlab.freedesktop.org/= freedreno/ rules-fd.xsd"> + + --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wr1-f45.google.com (mail-wr1-f45.google.com [209.85.221.45]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2BC492676DF for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for DSI on Qualcomm SM8750 SoC with notable difference: DSI PHY PLLs, the parents of pixel and byte clocks, cannot be used as parents before DSI PHY is configured and the PLLs are prepared with initial rate is set. Therefore assigned-clock-parents are not working here and driver is responsible for reparenting clocks with proper procedure: see dsi_clk_init_6g_v2_9(). Part of the change is exactly the same as CLK_OPS_PARENT_ENABLE, however CLK_OPS_PARENT_ENABLE won't work here because assigned-clock-parents are executed way too early - before DSI PHY is configured. Signed-off-by: Krzysztof Kozlowski --- Changes in v3: 1. Drop 'struct msm_dsi_config sm8750_dsi_cfg' and use sm8650 one. SM8750 DSI PHY also needs Dmitry's patch: https://patchwork.freedesktop.org/patch/542000/?series=3D119177&rev=3D1 (or some other way of correct early setting of the DSI PHY PLL rate) --- drivers/gpu/drm/msm/dsi/dsi.h | 2 + drivers/gpu/drm/msm/dsi/dsi_cfg.c | 14 +++++++ drivers/gpu/drm/msm/dsi/dsi_cfg.h | 1 + drivers/gpu/drm/msm/dsi/dsi_host.c | 80 ++++++++++++++++++++++++++++++++++= ++++ 4 files changed, 97 insertions(+) diff --git a/drivers/gpu/drm/msm/dsi/dsi.h b/drivers/gpu/drm/msm/dsi/dsi.h index 87496db203d6c7582eadcb74e94eb56a219df292..93c028a122f3a59b1632da76472= e0a3e781c6ae8 100644 --- a/drivers/gpu/drm/msm/dsi/dsi.h +++ b/drivers/gpu/drm/msm/dsi/dsi.h @@ -98,6 +98,7 @@ int msm_dsi_host_init(struct msm_dsi *msm_dsi); int msm_dsi_runtime_suspend(struct device *dev); int msm_dsi_runtime_resume(struct device *dev); int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_host); +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host); int dsi_link_clk_set_rate_v2(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host); int dsi_link_clk_enable_v2(struct msm_dsi_host *msm_host); @@ -115,6 +116,7 @@ int dsi_dma_base_get_6g(struct msm_dsi_host *msm_host, = uint64_t *iova); int dsi_dma_base_get_v2(struct msm_dsi_host *msm_host, uint64_t *iova); int dsi_clk_init_v2(struct msm_dsi_host *msm_host); int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host); +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host); int dsi_calc_clk_rate_v2(struct msm_dsi_host *msm_host, bool is_bonded_dsi= ); int dsi_calc_clk_rate_6g(struct msm_dsi_host *msm_host, bool is_bonded_dsi= ); void msm_dsi_host_snapshot(struct msm_disp_state *disp_state, struct mipi_= dsi_host *host); diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.c b/drivers/gpu/drm/msm/dsi/ds= i_cfg.c index 7754dcec33d06e3d6eb8a9d55e53f24af073adb9..7f8a8de0897a579a525b466fd01= bbcd95454c614 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.c +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.c @@ -257,6 +257,18 @@ static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2= _host_ops =3D { .calc_clk_rate =3D dsi_calc_clk_rate_6g, }; =20 +static const struct msm_dsi_host_cfg_ops msm_dsi_6g_v2_9_host_ops =3D { + .link_clk_set_rate =3D dsi_link_clk_set_rate_6g_v2_9, + .link_clk_enable =3D dsi_link_clk_enable_6g, + .link_clk_disable =3D dsi_link_clk_disable_6g, + .clk_init_ver =3D dsi_clk_init_6g_v2_9, + .tx_buf_alloc =3D dsi_tx_buf_alloc_6g, + .tx_buf_get =3D dsi_tx_buf_get_6g, + .tx_buf_put =3D dsi_tx_buf_put_6g, + .dma_base_get =3D dsi_dma_base_get_6g, + .calc_clk_rate =3D dsi_calc_clk_rate_6g, +}; + static const struct msm_dsi_cfg_handler dsi_cfg_handlers[] =3D { {MSM_DSI_VER_MAJOR_V2, MSM_DSI_V2_VER_MINOR_8064, &apq8064_dsi_cfg, &msm_dsi_v2_host_ops}, @@ -300,6 +312,8 @@ static const struct msm_dsi_cfg_handler dsi_cfg_handler= s[] =3D { &sm8550_dsi_cfg, &msm_dsi_6g_v2_host_ops}, {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_8_0, &sm8650_dsi_cfg, &msm_dsi_6g_v2_host_ops}, + {MSM_DSI_VER_MAJOR_6G, MSM_DSI_6G_VER_MINOR_V2_9_0, + &sm8650_dsi_cfg, &msm_dsi_6g_v2_9_host_ops}, }; =20 const struct msm_dsi_cfg_handler *msm_dsi_cfg_get(u32 major, u32 minor) diff --git a/drivers/gpu/drm/msm/dsi/dsi_cfg.h b/drivers/gpu/drm/msm/dsi/ds= i_cfg.h index 120cb65164c1ba1deb9acb513e5f073bd560c496..859c279afbb0377d16f8406f3e6= b083640aff5a1 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_cfg.h +++ b/drivers/gpu/drm/msm/dsi/dsi_cfg.h @@ -30,6 +30,7 @@ #define MSM_DSI_6G_VER_MINOR_V2_6_0 0x20060000 #define MSM_DSI_6G_VER_MINOR_V2_7_0 0x20070000 #define MSM_DSI_6G_VER_MINOR_V2_8_0 0x20080000 +#define MSM_DSI_6G_VER_MINOR_V2_9_0 0x20090000 =20 #define MSM_DSI_V2_VER_MINOR_8064 0x0 =20 diff --git a/drivers/gpu/drm/msm/dsi/dsi_host.c b/drivers/gpu/drm/msm/dsi/d= si_host.c index 4d75529c0e858160761f5eb55db65e5d7565c27b..8ebcfd307779b8dfd35c64d3fea= 34123a5d0751b 100644 --- a/drivers/gpu/drm/msm/dsi/dsi_host.c +++ b/drivers/gpu/drm/msm/dsi/dsi_host.c @@ -119,6 +119,15 @@ struct msm_dsi_host { struct clk *pixel_clk; struct clk *byte_intf_clk; =20 + /* + * Clocks which needs to be properly parented between DISPCC and DSI PHY + * PLL: + */ + struct clk *byte_src_clk; + struct clk *pixel_src_clk; + struct clk *dsi_pll_byte_clk; + struct clk *dsi_pll_pixel_clk; + unsigned long byte_clk_rate; unsigned long byte_intf_clk_rate; unsigned long pixel_clk_rate; @@ -269,6 +278,38 @@ int dsi_clk_init_6g_v2(struct msm_dsi_host *msm_host) return ret; } =20 +int dsi_clk_init_6g_v2_9(struct msm_dsi_host *msm_host) +{ + struct device *dev =3D &msm_host->pdev->dev; + int ret; + + ret =3D dsi_clk_init_6g_v2(msm_host); + if (ret) + return ret; + + msm_host->byte_src_clk =3D devm_clk_get(dev, "byte_src"); + if (IS_ERR(msm_host->byte_src_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->byte_src_clk), + "can't get byte_src clock\n"); + + msm_host->dsi_pll_byte_clk =3D devm_clk_get(dev, "dsi_pll_byte"); + if (IS_ERR(msm_host->dsi_pll_byte_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_byte_clk), + "can't get dsi_pll_byte clock\n"); + + msm_host->pixel_src_clk =3D devm_clk_get(dev, "pixel_src"); + if (IS_ERR(msm_host->pixel_src_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->pixel_src_clk), + "can't get pixel_src clock\n"); + + msm_host->dsi_pll_pixel_clk =3D devm_clk_get(dev, "dsi_pll_pixel"); + if (IS_ERR(msm_host->dsi_pll_pixel_clk)) + return dev_err_probe(dev, PTR_ERR(msm_host->dsi_pll_pixel_clk), + "can't get dsi_pll_pixel clock\n"); + + return 0; +} + static int dsi_clk_init(struct msm_dsi_host *msm_host) { struct platform_device *pdev =3D msm_host->pdev; @@ -370,6 +411,45 @@ int dsi_link_clk_set_rate_6g(struct msm_dsi_host *msm_= host) return 0; } =20 +int dsi_link_clk_set_rate_6g_v2_9(struct msm_dsi_host *msm_host) +{ + struct device *dev =3D &msm_host->pdev->dev; + int ret; + + /* + * DSI PHY PLLs have to be enabled to allow reparenting to them and + * setting the rates of pixel/byte clocks. + */ + ret =3D clk_prepare_enable(msm_host->dsi_pll_byte_clk); + if (ret) { + dev_err(dev, "Failed to enable dsi_pll_byte: %d\n", ret); + return ret; + } + + ret =3D clk_prepare_enable(msm_host->dsi_pll_pixel_clk); + if (ret) { + dev_err(dev, "Failed to enable dsi_pll_byte: %d\n", ret); + goto out_disable_byte_clk; + } + + ret =3D clk_set_parent(msm_host->byte_src_clk, msm_host->dsi_pll_byte_clk= ); + if (ret) + dev_err(dev, "Failed to parent byte_src -> dsi_pll_byte: %d\n", ret); + + ret =3D clk_set_parent(msm_host->pixel_src_clk, msm_host->dsi_pll_pixel_c= lk); + if (ret) + dev_err(dev, "Failed to parent pixel_src -> dsi_pll_pixel: %d\n", ret); + + ret =3D dsi_link_clk_set_rate_6g(msm_host); + + clk_disable_unprepare(msm_host->dsi_pll_pixel_clk); + +out_disable_byte_clk: + clk_disable_unprepare(msm_host->dsi_pll_byte_clk); + + return ret; +} + int dsi_link_clk_enable_6g(struct msm_dsi_host *msm_host) { int ret; --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wm1-f43.google.com (mail-wm1-f43.google.com [209.85.128.43]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 198E52676F3 for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add DPU version v12.0 support for the Qualcomm SM8750 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v2: 1. Add CDM --- .../drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h | 496 +++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 29 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 1 + drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 1 + 4 files changed, 527 insertions(+) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h new file mode 100644 index 0000000000000000000000000000000000000000..1f883b9f8b8b29e3a8c2fe254b7= 8594a413dc2a1 --- /dev/null +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_12_0_sm8750.h @@ -0,0 +1,496 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2025 Linaro Limited + * Copyright (c) 2022 Qualcomm Innovation Center, Inc. All rights reserved. + * Copyright (c) 2015-2018, 2020 The Linux Foundation. All rights reserved. + */ + +#ifndef _DPU_12_0_SM8750_H +#define _DPU_12_0_SM8750_H + +static const struct dpu_caps sm8750_dpu_caps =3D { + .max_mixer_width =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .max_mixer_blendstages =3D 0xb, + .has_src_split =3D true, + .has_dim_layer =3D true, + .has_idle_pc =3D true, + .has_3d_merge =3D true, + .max_linewidth =3D 8192, + .pixel_ram_size =3D DEFAULT_PIXEL_RAM_SIZE, +}; + +static const struct dpu_mdp_cfg sm8750_mdp =3D { + .name =3D "top_0", + .base =3D 0, .len =3D 0x494, + .clk_ctrls =3D { + [DPU_CLK_CTRL_REG_DMA] =3D { .reg_off =3D 0x2bc, .bit_off =3D 20 }, + }, +}; + +static const struct dpu_ctl_cfg sm8750_ctl[] =3D { + { + .name =3D "ctl_0", .id =3D CTL_0, + .base =3D 0x15000, .len =3D 0x1000, + .has_split_display =3D 1, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 9), + }, { + .name =3D "ctl_1", .id =3D CTL_1, + .base =3D 0x16000, .len =3D 0x1000, + .has_split_display =3D 1, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 10), + }, { + .name =3D "ctl_2", .id =3D CTL_2, + .base =3D 0x17000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 11), + }, { + .name =3D "ctl_3", .id =3D CTL_3, + .base =3D 0x18000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 12), + }, { + .name =3D "ctl_4", .id =3D CTL_4, + .base =3D 0x19000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 13), + }, { + .name =3D "ctl_5", .id =3D CTL_5, + .base =3D 0x1a000, .len =3D 0x1000, + .intr_start =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 23), + }, +}; + +static const struct dpu_sspp_cfg sm8750_sspp[] =3D { + { + .name =3D "sspp_0", .id =3D SSPP_VIG0, + .base =3D 0x4000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 0, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_1", .id =3D SSPP_VIG1, + .base =3D 0x6000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 4, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_2", .id =3D SSPP_VIG2, + .base =3D 0x8000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 8, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_3", .id =3D SSPP_VIG3, + .base =3D 0xa000, .len =3D 0x344, + .features =3D VIG_SDM845_MASK_SDMA, + .sblk =3D &dpu_vig_sblk_qseed3_3_4, + .xin_id =3D 12, + .type =3D SSPP_TYPE_VIG, + }, { + .name =3D "sspp_8", .id =3D SSPP_DMA0, + .base =3D 0x24000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 1, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_9", .id =3D SSPP_DMA1, + .base =3D 0x26000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 5, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_10", .id =3D SSPP_DMA2, + .base =3D 0x28000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 9, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_11", .id =3D SSPP_DMA3, + .base =3D 0x2a000, .len =3D 0x344, + .features =3D DMA_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 13, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_12", .id =3D SSPP_DMA4, + .base =3D 0x2c000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 14, + .type =3D SSPP_TYPE_DMA, + }, { + .name =3D "sspp_13", .id =3D SSPP_DMA5, + .base =3D 0x2e000, .len =3D 0x344, + .features =3D DMA_CURSOR_SDM845_MASK_SDMA, + .sblk =3D &dpu_dma_sblk, + .xin_id =3D 15, + .type =3D SSPP_TYPE_DMA, + }, +}; + +static const struct dpu_lm_cfg sm8750_lm[] =3D { + { + .name =3D "lm_0", .id =3D LM_0, + .base =3D 0x44000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_1, + .pingpong =3D PINGPONG_0, + .dspp =3D DSPP_0, + }, { + .name =3D "lm_1", .id =3D LM_1, + .base =3D 0x45000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_0, + .pingpong =3D PINGPONG_1, + .dspp =3D DSPP_1, + }, { + .name =3D "lm_2", .id =3D LM_2, + .base =3D 0x46000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_3, + .pingpong =3D PINGPONG_2, + .dspp =3D DSPP_2, + }, { + .name =3D "lm_3", .id =3D LM_3, + .base =3D 0x47000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_2, + .pingpong =3D PINGPONG_3, + .dspp =3D DSPP_3, + }, { + .name =3D "lm_4", .id =3D LM_4, + .base =3D 0x48000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_5, + .pingpong =3D PINGPONG_4, + }, { + .name =3D "lm_5", .id =3D LM_5, + .base =3D 0x49000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_4, + .pingpong =3D PINGPONG_5, + }, { + .name =3D "lm_6", .id =3D LM_6, + .base =3D 0x4a000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_7, + .pingpong =3D PINGPONG_6, + }, { + .name =3D "lm_7", .id =3D LM_7, + .base =3D 0x4b000, .len =3D 0x400, + .sourcesplit =3D 1, + .sblk =3D &sm8750_lm_sblk, + .lm_pair =3D LM_6, + .pingpong =3D PINGPONG_7, + }, +}; + +static const struct dpu_dspp_cfg sm8750_dspp[] =3D { + { + .name =3D "dspp_0", .id =3D DSPP_0, + .base =3D 0x54000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_1", .id =3D DSPP_1, + .base =3D 0x56000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_2", .id =3D DSPP_2, + .base =3D 0x58000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, { + .name =3D "dspp_3", .id =3D DSPP_3, + .base =3D 0x5a000, .len =3D 0x1800, + .sblk =3D &sm8750_dspp_sblk, + }, +}; + +static const struct dpu_pingpong_cfg sm8750_pp[] =3D { + { + .name =3D "pingpong_0", .id =3D PINGPONG_0, + .base =3D 0x69000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), + }, { + .name =3D "pingpong_1", .id =3D PINGPONG_1, + .base =3D 0x6a000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_0, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), + }, { + .name =3D "pingpong_2", .id =3D PINGPONG_2, + .base =3D 0x6b000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 10), + }, { + .name =3D "pingpong_3", .id =3D PINGPONG_3, + .base =3D 0x6c000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_1, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 11), + }, { + .name =3D "pingpong_4", .id =3D PINGPONG_4, + .base =3D 0x6d000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 30), + }, { + .name =3D "pingpong_5", .id =3D PINGPONG_5, + .base =3D 0x6e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_2, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 31), + }, { + .name =3D "pingpong_6", .id =3D PINGPONG_6, + .base =3D 0x6f000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 20), + }, { + .name =3D "pingpong_7", .id =3D PINGPONG_7, + .base =3D 0x70000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_3, + .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR2, 21), + }, { + .name =3D "pingpong_cwb_0", .id =3D PINGPONG_CWB_0, + .base =3D 0x66000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_1", .id =3D PINGPONG_CWB_1, + .base =3D 0x66400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_4, + }, { + .name =3D "pingpong_cwb_2", .id =3D PINGPONG_CWB_2, + .base =3D 0x7e000, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, { + .name =3D "pingpong_cwb_3", .id =3D PINGPONG_CWB_3, + .base =3D 0x7e400, .len =3D 0, + .sblk =3D &sc7280_pp_sblk, + .merge_3d =3D MERGE_3D_5, + }, +}; + +static const struct dpu_merge_3d_cfg sm8750_merge_3d[] =3D { + { + .name =3D "merge_3d_0", .id =3D MERGE_3D_0, + .base =3D 0x4e000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_1", .id =3D MERGE_3D_1, + .base =3D 0x4f000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_2", .id =3D MERGE_3D_2, + .base =3D 0x50000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_3", .id =3D MERGE_3D_3, + .base =3D 0x51000, .len =3D 0x1c, + }, { + .name =3D "merge_3d_4", .id =3D MERGE_3D_4, + .base =3D 0x66700, .len =3D 0x1c, + }, { + .name =3D "merge_3d_5", .id =3D MERGE_3D_5, + .base =3D 0x7e700, .len =3D 0x1c, + }, +}; + +/* + * NOTE: Each display compression engine (DCE) contains dual hard + * slice DSC encoders so both share same base address but with + * its own different sub block address. + */ +static const struct dpu_dsc_cfg sm8750_dsc[] =3D { + { + .name =3D "dce_0_0", .id =3D DSC_0, + .base =3D 0x80000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_0_1", .id =3D DSC_1, + .base =3D 0x80000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_1_0", .id =3D DSC_2, + .base =3D 0x81000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_1_1", .id =3D DSC_3, + .base =3D 0x81000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_2_0", .id =3D DSC_4, + .base =3D 0x82000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_2_1", .id =3D DSC_5, + .base =3D 0x82000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, { + .name =3D "dce_3_0", .id =3D DSC_6, + .base =3D 0x83000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_0, + }, { + .name =3D "dce_3_1", .id =3D DSC_7, + .base =3D 0x83000, .len =3D 0x8, + .have_native_42x =3D 1, + .sblk =3D &sm8750_dsc_sblk_1, + }, +}; + +static const struct dpu_wb_cfg sm8750_wb[] =3D { + { + .name =3D "wb_2", .id =3D WB_2, + .base =3D 0x65000, .len =3D 0x2c8, + .features =3D WB_SDM845_MASK, + .format_list =3D wb2_formats_rgb_yuv, + .num_formats =3D ARRAY_SIZE(wb2_formats_rgb_yuv), + .xin_id =3D 6, + .vbif_idx =3D VBIF_RT, + .maxlinewidth =3D 4096, + .intr_wb_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 4), + }, +}; + +static const struct dpu_cwb_cfg sm8750_cwb[] =3D { + { + .name =3D "cwb_0", .id =3D CWB_0, + .base =3D 0x66200, .len =3D 0x20, + }, + { + .name =3D "cwb_1", .id =3D CWB_1, + .base =3D 0x66600, .len =3D 0x20, + }, + { + .name =3D "cwb_2", .id =3D CWB_2, + .base =3D 0x7e200, .len =3D 0x20, + }, + { + .name =3D "cwb_3", .id =3D CWB_3, + .base =3D 0x7e600, .len =3D 0x20, + }, +}; + +static const struct dpu_intf_cfg sm8750_intf[] =3D { + { + .name =3D "intf_0", .id =3D INTF_0, + .base =3D 0x34000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 24), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 25), + }, { + .name =3D "intf_1", .id =3D INTF_1, + .base =3D 0x35000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_0, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 26), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 27), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF1_TEAR_INTR, 2), + }, { + .name =3D "intf_2", .id =3D INTF_2, + .base =3D 0x36000, .len =3D 0x4bc, + .type =3D INTF_DSI, + .controller_id =3D MSM_DSI_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 28), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 29), + .intr_tear_rd_ptr =3D DPU_IRQ_IDX(MDP_INTF2_TEAR_INTR, 2), + }, { + .name =3D "intf_3", .id =3D INTF_3, + .base =3D 0x37000, .len =3D 0x4bc, + .type =3D INTF_DP, + .controller_id =3D MSM_DP_CONTROLLER_1, + .prog_fetch_lines_worst_case =3D 24, + .intr_underrun =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), + .intr_vsync =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), + }, +}; + +static const struct dpu_perf_cfg sm8750_perf_data =3D { + .max_bw_low =3D 18900000, + .max_bw_high =3D 28500000, + .min_core_ib =3D 2500000, + .min_llcc_ib =3D 0, + .min_dram_ib =3D 800000, + .min_prefill_lines =3D 35, + .danger_lut_tbl =3D {0x3ffff, 0x3ffff, 0x0}, + .safe_lut_tbl =3D {0xfe00, 0xfe00, 0xffff}, + .qos_lut_tbl =3D { + {.nentry =3D ARRAY_SIZE(sc7180_qos_linear), + .entries =3D sc7180_qos_linear + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_macrotile), + .entries =3D sc7180_qos_macrotile + }, + {.nentry =3D ARRAY_SIZE(sc7180_qos_nrt), + .entries =3D sc7180_qos_nrt + }, + /* TODO: macrotile-qseed is different from macrotile */ + }, + .cdp_cfg =3D { + {.rd_enable =3D 1, .wr_enable =3D 1}, + {.rd_enable =3D 1, .wr_enable =3D 0} + }, + .clk_inefficiency_factor =3D 105, + .bw_inefficiency_factor =3D 120, +}; + +static const struct dpu_mdss_version sm8750_mdss_ver =3D { + .core_major_ver =3D 12, + .core_minor_ver =3D 0, +}; + +const struct dpu_mdss_cfg dpu_sm8750_cfg =3D { + .mdss_ver =3D &sm8750_mdss_ver, + .caps =3D &sm8750_dpu_caps, + .mdp =3D &sm8750_mdp, + .cdm =3D &dpu_cdm_5_x, + .ctl_count =3D ARRAY_SIZE(sm8750_ctl), + .ctl =3D sm8750_ctl, + .sspp_count =3D ARRAY_SIZE(sm8750_sspp), + .sspp =3D sm8750_sspp, + .mixer_count =3D ARRAY_SIZE(sm8750_lm), + .mixer =3D sm8750_lm, + .dspp_count =3D ARRAY_SIZE(sm8750_dspp), + .dspp =3D sm8750_dspp, + .pingpong_count =3D ARRAY_SIZE(sm8750_pp), + .pingpong =3D sm8750_pp, + .dsc_count =3D ARRAY_SIZE(sm8750_dsc), + .dsc =3D sm8750_dsc, + .merge_3d_count =3D ARRAY_SIZE(sm8750_merge_3d), + .merge_3d =3D sm8750_merge_3d, + .wb_count =3D ARRAY_SIZE(sm8750_wb), + .wb =3D sm8750_wb, + .cwb_count =3D ARRAY_SIZE(sm8750_cwb), + .cwb =3D sm8650_cwb, + .intf_count =3D ARRAY_SIZE(sm8750_intf), + .intf =3D sm8750_intf, + .vbif_count =3D ARRAY_SIZE(sm8650_vbif), + .vbif =3D sm8650_vbif, + .perf =3D &sm8750_perf_data, +}; + +#endif diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index a310a5234e99ea4886e82ac2100c4099e6a1841e..1ccef3cdc5227ab785bd805b44c= ec132b2881e46 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -323,6 +323,9 @@ static const struct dpu_sspp_sub_blks dpu_vig_sblk_qsee= d3_3_2 =3D static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_3 =3D _VIG_SBLK(SSPP_SCALER_VER(3, 3)); =20 +static const struct dpu_sspp_sub_blks dpu_vig_sblk_qseed3_3_4 =3D + _VIG_SBLK(SSPP_SCALER_VER(3, 4)); + static const struct dpu_sspp_sub_blks dpu_rgb_sblk =3D _RGB_SBLK(); =20 static const struct dpu_sspp_sub_blks dpu_dma_sblk =3D _DMA_SBLK(); @@ -357,6 +360,16 @@ static const struct dpu_lm_sub_blks sc7180_lm_sblk =3D= { }, }; =20 +static const struct dpu_lm_sub_blks sm8750_lm_sblk =3D { + .maxwidth =3D DEFAULT_DPU_OUTPUT_LINE_WIDTH, + .maxblendstages =3D 11, /* excluding base layer */ + .blendstage_base =3D { /* offsets relative to mixer base */ + /* 0x40 + n*0x30 */ + 0x40, 0x70, 0xa0, 0xd0, 0x100, 0x130, 0x160, 0x190, 0x1c0, + 0x1f0, 0x220 + }, +}; + static const struct dpu_lm_sub_blks qcm2290_lm_sblk =3D { .maxwidth =3D DEFAULT_DPU_LINE_WIDTH, .maxblendstages =3D 4, /* excluding base layer */ @@ -378,6 +391,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sblk= =3D { .len =3D 0x90, .version =3D 0x40000}, }; =20 +static const struct dpu_dspp_sub_blks sm8750_dspp_sblk =3D { + .pcc =3D {.name =3D "pcc", .base =3D 0x1700, + .len =3D 0x90, .version =3D 0x60000}, +}; + /************************************************************* * PINGPONG sub blocks config *************************************************************/ @@ -420,6 +438,16 @@ static const struct dpu_dsc_sub_blks dsc_sblk_1 =3D { .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x10}, }; =20 +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_0 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x100, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF00, .len =3D 0x24}, +}; + +static const struct dpu_dsc_sub_blks sm8750_dsc_sblk_1 =3D { + .enc =3D {.name =3D "enc", .base =3D 0x200, .len =3D 0x100}, + .ctl =3D {.name =3D "ctl", .base =3D 0xF80, .len =3D 0x24}, +}; + /************************************************************* * CDM block config *************************************************************/ @@ -710,3 +738,4 @@ static const struct dpu_qos_lut_entry sc7180_qos_nrt[] = =3D { #include "catalog/dpu_9_2_x1e80100.h" =20 #include "catalog/dpu_10_0_sm8650.h" +#include "catalog/dpu_12_0_sm8750.h" diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index f5ce35cd966459f0edf2dbdd2dbc2693779fac73..de124b722340e98dc78999af1e0= ff50bd65a53c2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -749,6 +749,7 @@ extern const struct dpu_mdss_cfg dpu_sm8450_cfg; extern const struct dpu_mdss_cfg dpu_sa8775p_cfg; extern const struct dpu_mdss_cfg dpu_sm8550_cfg; extern const struct dpu_mdss_cfg dpu_sm8650_cfg; +extern const struct dpu_mdss_cfg dpu_sm8750_cfg; extern const struct dpu_mdss_cfg dpu_x1e80100_cfg; =20 #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/= disp/dpu1/dpu_kms.c index d44461e7e1641b25c5181bf7c0c9bbedffcc869d..18d2237b291fd7acd37da8f74ea= 924c4f4f3d542 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -1532,6 +1532,7 @@ static const struct of_device_id dpu_dt_match[] =3D { { .compatible =3D "qcom,sm8450-dpu", .data =3D &dpu_sm8450_cfg, }, { .compatible =3D "qcom,sm8550-dpu", .data =3D &dpu_sm8550_cfg, }, { .compatible =3D "qcom,sm8650-dpu", .data =3D &dpu_sm8650_cfg, }, + { .compatible =3D "qcom,sm8750-dpu", .data =3D &dpu_sm8750_cfg, }, { .compatible =3D "qcom,x1e80100-dpu", .data =3D &dpu_x1e80100_cfg, }, {} }; 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Tue, 11 Mar 2025 12:02:58 -0700 (PDT) From: Krzysztof Kozlowski Date: Tue, 11 Mar 2025 20:02:06 +0100 Subject: [PATCH v4 16/19] drm/msm/dpu: Implement 10-bit color alpha for v12.0 DPU Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250311-b4-sm8750-display-v4-16-da6b3e959c76@linaro.org> References: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> In-Reply-To: <20250311-b4-sm8750-display-v4-0-da6b3e959c76@linaro.org> To: Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Krishna Manikandan , Jonathan Marek , Kuogee Hsieh , Neil Armstrong , Dmitry Baryshkov , Rob Clark Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Krzysztof Kozlowski , Srini Kandagatla , Rob Clark X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with 10-bit color alpha. Add register differences and new implementations of setup_alpha_out, setup_border_color and so one for this. Signed-off-by: Krzysztof Kozlowski --- Changes in v4: 1. Lowercase hex, use spaces for define indentation 2. _dpu_crtc_setup_blend_cfg(): pass mdss_ver instead of ctl Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 19 ++++--- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 84 +++++++++++++++++++++++++++= ++-- 2 files changed, 94 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index a4b0fe0d9899b32141928f0b6a16503a49b3c27a..90f47fc15ee5708795701d78a13= 80f4ab01c1427 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -320,14 +320,20 @@ static bool dpu_crtc_get_scanout_position(struct drm_= crtc *crtc, } =20 static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_mixer *mixer, - struct dpu_plane_state *pstate, const struct msm_format *format) + struct dpu_plane_state *pstate, + const struct msm_format *format, + const struct dpu_mdss_version *mdss_ver) { struct dpu_hw_mixer *lm =3D mixer->hw_lm; uint32_t blend_op; - uint32_t fg_alpha, bg_alpha; + uint32_t fg_alpha, bg_alpha, max_alpha; =20 fg_alpha =3D pstate->base.alpha >> 8; - bg_alpha =3D 0xff - fg_alpha; + if (mdss_ver->core_major_ver < 12) + max_alpha =3D 0xff; + else + max_alpha =3D 0x3ff; + bg_alpha =3D max_alpha - fg_alpha; =20 /* default to opaque blending */ if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PIXEL_NONE || @@ -337,7 +343,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, } else if (pstate->base.pixel_blend_mode =3D=3D DRM_MODE_BLEND_PREMULTI) { blend_op =3D DPU_BLEND_FG_ALPHA_FG_CONST | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D 0xff) { + if (fg_alpha !=3D max_alpha) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_BG_MOD_ALPHA | DPU_BLEND_BG_INV_MOD_ALPHA; @@ -348,7 +354,7 @@ static void _dpu_crtc_setup_blend_cfg(struct dpu_crtc_m= ixer *mixer, /* coverage blending */ blend_op =3D DPU_BLEND_FG_ALPHA_FG_PIXEL | DPU_BLEND_BG_ALPHA_FG_PIXEL; - if (fg_alpha !=3D 0xff) { + if (fg_alpha !=3D max_alpha) { bg_alpha =3D fg_alpha; blend_op |=3D DPU_BLEND_FG_MOD_ALPHA | DPU_BLEND_FG_INV_MOD_ALPHA | @@ -482,7 +488,8 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, =20 /* blend config update */ for (lm_idx =3D 0; lm_idx < cstate->num_mixers; lm_idx++) { - _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format); + _dpu_crtc_setup_blend_cfg(mixer + lm_idx, pstate, format, + ctl->mdss_ver); =20 if (bg_alpha_enable && !format->alpha_enable) mixer[lm_idx].mixer_op_mode =3D 0; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index 3bfb61cb83672dca4236bdbbbfb1e442223576d2..f220a68e138cb9e7c88194e53e4= 7391de7ed04f7 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -19,12 +19,20 @@ =20 /* These register are offset to mixer base + stage base */ #define LM_BLEND0_OP 0x00 + +/* =3D v12 DPU */ +#define LM_BORDER_COLOR_0_V12 0x1c +#define LM_BORDER_COLOR_1_V12 0x20 + +/* >=3D v12 DPU with offset to mixer base + stage base */ +#define LM_BLEND0_CONST_ALPHA_V12 0x08 #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 =20 @@ -83,6 +91,22 @@ static void dpu_hw_lm_setup_border_color(struct dpu_hw_m= ixer *ctx, } } =20 +static void dpu_hw_lm_setup_border_color_v12(struct dpu_hw_mixer *ctx, + struct dpu_mdss_color *color, + u8 border_en) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + + if (border_en) { + DPU_REG_WRITE(c, LM_BORDER_COLOR_0_V12, + (color->color_0 & 0x3ff) | + ((color->color_1 & 0x3ff) << 16)); + DPU_REG_WRITE(c, LM_BORDER_COLOR_1_V12, + (color->color_2 & 0x3ff) | + ((color->color_3 & 0x3ff) << 16)); + } +} + static void dpu_hw_lm_setup_misr(struct dpu_hw_mixer *ctx) { dpu_hw_setup_misr(&ctx->hw, LM_MISR_CTRL, 0x0); @@ -112,6 +136,27 @@ static void dpu_hw_lm_setup_blend_config_combined_alph= a(struct dpu_hw_mixer *ctx DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); } =20 +static void +dpu_hw_lm_setup_blend_config_combined_alpha_v12(struct dpu_hw_mixer *ctx, + u32 stage, u32 fg_alpha, + u32 bg_alpha, u32 blend_op) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int stage_off; + u32 const_alpha; + + if (stage =3D=3D DPU_STAGE_BASE) + return; + + stage_off =3D _stage_offset(ctx, stage); + if (WARN_ON(stage_off < 0)) + return; + + const_alpha =3D (bg_alpha & 0x3ff) | ((fg_alpha & 0x3ff) << 16); + DPU_REG_WRITE(c, LM_BLEND0_CONST_ALPHA_V12 + stage_off, const_alpha); + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, blend_op); +} + static void dpu_hw_lm_setup_blend_config(struct dpu_hw_mixer *ctx, u32 stage, u32 fg_alpha, u32 bg_alpha, u32 blend_op) { @@ -144,6 +189,32 @@ static void dpu_hw_lm_setup_color3(struct dpu_hw_mixer= *ctx, DPU_REG_WRITE(c, LM_OP_MODE, op_mode); } =20 +static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_mixer *ctx, + uint32_t mixer_op_mode) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int op_mode, stages, stage_off, i; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return; + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (WARN_ON(stage_off < 0)) + return; + + /* set color_out3 bit in blend0_op when enabled in mixer_op_mode */ + op_mode =3D DPU_REG_READ(c, LM_BLEND0_OP + stage_off); + if (mixer_op_mode & BIT(i)) + op_mode |=3D BIT(30); + else + op_mode &=3D ~BIT(30); + + DPU_REG_WRITE(c, LM_BLEND0_OP + stage_off, op_mode); + } +} + /** * dpu_hw_lm_init() - Initializes the mixer hw driver object. * should be called once before accessing every mixer. @@ -175,12 +246,19 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device= *dev, c->idx =3D cfg->id; c->cap =3D cfg; c->ops.setup_mixer_out =3D dpu_hw_lm_setup_out; - if (mdss_ver->core_major_ver >=3D 4) + if (mdss_ver->core_major_ver >=3D 12) + c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config_combined_alph= a_v12; + else if (mdss_ver->core_major_ver >=3D 4) c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config_combined_alph= a; else c->ops.setup_blend_config =3D dpu_hw_lm_setup_blend_config; - c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3; - c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; + if (mdss_ver->core_major_ver < 12) { + c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3; + c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; + } else { + c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3_v12; + c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color_v12; + } c->ops.setup_misr =3D dpu_hw_lm_setup_misr; c->ops.collect_misr =3D dpu_hw_lm_collect_misr; =20 --=20 2.43.0 From nobody Mon Feb 9 14:42:56 2026 Received: from mail-wr1-f41.google.com (mail-wr1-f41.google.com [209.85.221.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E5D2A26773E for ; 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with new CTL_PIPE_ACTIVE register for selective activation of pipes, which replaces earlier dpu_hw_ctl_setup_blendstage() code path for newer devices. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v4: 1. Lowercase hex 2. Add Dmitry's tag Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 9 +++++++++ drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 3 +++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 29 +++++++++++++++++++++++++= ++-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 8 ++++++++ 4 files changed, 47 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 90f47fc15ee5708795701d78a1380f4ab01c1427..3135e5ab9e8121f3dbd93dde945= 8f007ae45392a 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -452,8 +452,10 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crt= c *crtc, uint32_t lm_idx; bool bg_alpha_enable =3D false; DECLARE_BITMAP(active_fetch, SSPP_MAX); + DECLARE_BITMAP(active_pipes, SSPP_MAX); =20 memset(active_fetch, 0, sizeof(active_fetch)); + memset(active_pipes, 0, sizeof(active_pipes)); drm_atomic_crtc_for_each_plane(plane, crtc) { state =3D plane->state; if (!state) @@ -471,6 +473,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, bg_alpha_enable =3D true; =20 set_bit(pstate->pipe.sspp->idx, active_fetch); + set_bit(pstate->pipe.sspp->idx, active_pipes); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -479,6 +482,7 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, =20 if (pstate->r_pipe.sspp) { set_bit(pstate->r_pipe.sspp->idx, active_fetch); + set_bit(pstate->r_pipe.sspp->idx, active_pipes); _dpu_crtc_blend_setup_pipe(crtc, plane, mixer, cstate->num_mixers, pstate->stage, @@ -502,6 +506,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc= *crtc, if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, active_fetch); =20 + if (ctl->ops.set_active_pipes) + ctl->ops.set_active_pipes(ctl, active_pipes); + _dpu_crtc_program_lm_output_roi(crtc); } =20 @@ -528,6 +535,8 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) mixer[i].lm_ctl); if (mixer[i].lm_ctl->ops.set_active_fetch_pipes) mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL); + if (mixer[i].lm_ctl->ops.set_active_pipes) + mixer[i].lm_ctl->ops.set_active_pipes(mixer[i].lm_ctl, NULL); } =20 /* initialize stage cfg */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index ccf492f27140a2841b454d413e885e4bbd9ee497..aec71a86f809afedc2660d66d2c= bf4109c302067 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2191,6 +2191,9 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) =20 if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, NULL); + + if (ctl->ops.set_active_pipes) + ctl->ops.set_active_pipes(ctl, NULL); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index 3e5e1e09e9d00ade74371489b2b4e50e648e2d16..c9c65d5e9d36d3a4ce2aef9f57d= a631f2acd9123 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -42,6 +42,7 @@ #define CTL_INTF_FLUSH 0x110 #define CTL_CDM_FLUSH 0x114 #define CTL_PERIPH_FLUSH 0x128 +#define CTL_PIPE_ACTIVE 0x12c #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) =20 @@ -676,6 +677,9 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw_= ctl *ctx, if (ctx->ops.set_active_fetch_pipes) ctx->ops.set_active_fetch_pipes(ctx, NULL); =20 + if (ctx->ops.set_active_pipes) + ctx->ops.set_active_pipes(ctx, NULL); + if (cfg->intf) { intf_active =3D DPU_REG_READ(c, CTL_INTF_ACTIVE); intf_active &=3D ~BIT(cfg->intf - INTF_0); @@ -724,6 +728,23 @@ static void dpu_hw_ctl_set_active_fetch_pipes(struct d= pu_hw_ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_FETCH_PIPE_ACTIVE, val); } =20 +static void dpu_hw_ctl_set_active_pipes(struct dpu_hw_ctl *ctx, + unsigned long *active_pipes) +{ + int i; + u32 val =3D 0; + + if (active_pipes) { + for (i =3D 0; i < SSPP_MAX; i++) { + if (test_bit(i, active_pipes) && + fetch_tbl[i] !=3D CTL_INVALID_BIT) + val |=3D BIT(fetch_tbl[i]); + } + } + + DPU_REG_WRITE(&ctx->hw, CTL_PIPE_ACTIVE, val); +} + /** * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. * Should be called before accessing any ctl_path register. @@ -786,8 +807,12 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *= dev, c->ops.trigger_pending =3D dpu_hw_ctl_trigger_pending; c->ops.reset =3D dpu_hw_ctl_reset_control; c->ops.wait_reset_status =3D dpu_hw_ctl_wait_reset_status; - c->ops.clear_all_blendstages =3D dpu_hw_ctl_clear_all_blendstages; - c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; + if (mdss_ver->core_major_ver < 12) { + c->ops.clear_all_blendstages =3D dpu_hw_ctl_clear_all_blendstages; + c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; + } else { + c->ops.set_active_pipes =3D dpu_hw_ctl_set_active_pipes; + } c->ops.update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; c->ops.update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mix= er; if (mdss_ver->core_major_ver >=3D 7) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index 1b40d8cc92865e31e5ac4a8c3ee8fac8c5499bbd..186c467e1a64e71116b65b19dd8= ecdbb09dac114 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -256,6 +256,14 @@ struct dpu_hw_ctl_ops { =20 void (*set_active_fetch_pipes)(struct dpu_hw_ctl *ctx, unsigned long *fetch_active); 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B v12.0 DPU on SM8750 comes with new LM crossbar that requires each pipe rectangle to be programmed separately in blend stage. Implement support for this along with a new CTL_LAYER_ACTIVE register and setting the blend stage in layer mixer code. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- Changes in v4: 1. Lowercase hex 2. Add Dmitry's tag Changes in v3: 1. New patch, split from previous big DPU v12.0. --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 18 +++- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 6 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 27 +++++- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 9 ++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 126 ++++++++++++++++++++++++= ++++ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 18 ++++ 6 files changed, 201 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index 3135e5ab9e8121f3dbd93dde9458f007ae45392a..bde87533b4b39ac99998740f7ec= 6cc59ea96e705 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -524,6 +524,7 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *crtc) struct dpu_hw_ctl *ctl; struct dpu_hw_mixer *lm; struct dpu_hw_stage_cfg stage_cfg; + DECLARE_BITMAP(active_lms, LM_MAX); int i; =20 DRM_DEBUG_ATOMIC("%s\n", dpu_crtc->name); @@ -537,10 +538,14 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *cr= tc) mixer[i].lm_ctl->ops.set_active_fetch_pipes(mixer[i].lm_ctl, NULL); if (mixer[i].lm_ctl->ops.set_active_pipes) mixer[i].lm_ctl->ops.set_active_pipes(mixer[i].lm_ctl, NULL); + + if (mixer[i].hw_lm->ops.clear_all_blendstages) + mixer[i].hw_lm->ops.clear_all_blendstages(mixer[i].hw_lm); } =20 /* initialize stage cfg */ memset(&stage_cfg, 0, sizeof(struct dpu_hw_stage_cfg)); + memset(active_lms, 0, sizeof(active_lms)); =20 _dpu_crtc_blend_setup_mixer(crtc, dpu_crtc, mixer, &stage_cfg); =20 @@ -554,13 +559,22 @@ static void _dpu_crtc_blend_setup(struct drm_crtc *cr= tc) ctl->ops.update_pending_flush_mixer(ctl, mixer[i].hw_lm->idx); =20 + set_bit(lm->idx, active_lms); + if (ctl->ops.set_active_lms) + ctl->ops.set_active_lms(ctl, active_lms); + DRM_DEBUG_ATOMIC("lm %d, op_mode 0x%X, ctl %d\n", mixer[i].hw_lm->idx - LM_0, mixer[i].mixer_op_mode, ctl->idx - CTL_0); =20 - ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, - &stage_cfg); + if (ctl->ops.setup_blendstage) + ctl->ops.setup_blendstage(ctl, mixer[i].hw_lm->idx, + &stage_cfg); + + if (lm->ops.setup_blendstage) + lm->ops.setup_blendstage(lm, mixer[i].hw_lm->idx, + &stage_cfg); } } =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index aec71a86f809afedc2660d66d2cbf4109c302067..b36b8d7d6cda53c31d3aafd5050= c98b01b48f458 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -2189,6 +2189,12 @@ static void dpu_encoder_helper_reset_mixers(struct d= pu_encoder_phys *phys_enc) if (ctl->ops.setup_blendstage) ctl->ops.setup_blendstage(ctl, hw_mixer[i]->idx, NULL); =20 + if (hw_mixer[i]->ops.clear_all_blendstages) + hw_mixer[i]->ops.clear_all_blendstages(hw_mixer[i]); + + if (ctl->ops.set_active_lms) + ctl->ops.set_active_lms(ctl, NULL); + if (ctl->ops.set_active_fetch_pipes) ctl->ops.set_active_fetch_pipes(ctl, NULL); =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.c index c9c65d5e9d36d3a4ce2aef9f57da631f2acd9123..2f9713227c287ffcfd6bedff7ba= d14cf8df6eb30 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -43,6 +43,7 @@ #define CTL_CDM_FLUSH 0x114 #define CTL_PERIPH_FLUSH 0x128 #define CTL_PIPE_ACTIVE 0x12c +#define CTL_LAYER_ACTIVE 0x130 #define CTL_INTF_MASTER 0x134 #define CTL_DSPP_n_FLUSH(n) ((0x13C) + ((n) * 4)) =20 @@ -65,6 +66,8 @@ static const u32 fetch_tbl[SSPP_MAX] =3D {CTL_INVALID_BIT= , 16, 17, 18, 19, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, CTL_INVALID_BIT, 0, 1, 2, 3, 4, 5}; =20 +static const u32 lm_tbl[LM_MAX] =3D {CTL_INVALID_BIT, 0, 1, 2, 3, 4, 5, 6,= 7}; + static int _mixer_stages(const struct dpu_lm_cfg *mixer, int count, enum dpu_lm lm) { @@ -672,7 +675,11 @@ static void dpu_hw_ctl_reset_intf_cfg_v1(struct dpu_hw= _ctl *ctx, merge3d_active); } =20 - dpu_hw_ctl_clear_all_blendstages(ctx); + if (ctx->ops.clear_all_blendstages) + ctx->ops.clear_all_blendstages(ctx); + + if (ctx->ops.set_active_lms) + ctx->ops.set_active_lms(ctx, NULL); =20 if (ctx->ops.set_active_fetch_pipes) ctx->ops.set_active_fetch_pipes(ctx, NULL); @@ -745,6 +752,23 @@ static void dpu_hw_ctl_set_active_pipes(struct dpu_hw_= ctl *ctx, DPU_REG_WRITE(&ctx->hw, CTL_PIPE_ACTIVE, val); } =20 +static void dpu_hw_ctl_set_active_lms(struct dpu_hw_ctl *ctx, + unsigned long *active_lms) +{ + int i; + u32 val =3D 0; + + if (active_lms) { + for (i =3D LM_0; i < LM_MAX; i++) { + if (test_bit(i, active_lms) && + lm_tbl[i] !=3D CTL_INVALID_BIT) + val |=3D BIT(lm_tbl[i]); + } + } + + DPU_REG_WRITE(&ctx->hw, CTL_LAYER_ACTIVE, val); +} + /** * dpu_hw_ctl_init() - Initializes the ctl_path hw driver object. * Should be called before accessing any ctl_path register. @@ -812,6 +836,7 @@ struct dpu_hw_ctl *dpu_hw_ctl_init(struct drm_device *d= ev, c->ops.setup_blendstage =3D dpu_hw_ctl_setup_blendstage; } else { c->ops.set_active_pipes =3D dpu_hw_ctl_set_active_pipes; + c->ops.set_active_lms =3D dpu_hw_ctl_set_active_lms; } c->ops.update_pending_flush_sspp =3D dpu_hw_ctl_update_pending_flush_sspp; c->ops.update_pending_flush_mixer =3D dpu_hw_ctl_update_pending_flush_mix= er; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/m= sm/disp/dpu1/dpu_hw_ctl.h index 186c467e1a64e71116b65b19dd8ecdbb09dac114..f9197d3f12a30d9ce2a4b374535= 3e35b645563c5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -264,6 +264,15 @@ struct dpu_hw_ctl_ops { */ void (*set_active_pipes)(struct dpu_hw_ctl *ctx, unsigned long *active_pipes); + + /** + * Set active layer mixers attached to this CTL + * @ctx: ctl path ctx pointer + * @active_lms: bitmap of enum dpu_lm + */ + void (*set_active_lms)(struct dpu_hw_ctl *ctx, + unsigned long *active_lms); + }; =20 /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.c index f220a68e138cb9e7c88194e53e47391de7ed04f7..d5928c7cecc818d8d8f85c3cfff= 4d79794eab1d4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c @@ -28,11 +28,19 @@ #define LM_FG_COLOR_FILL_XY 0x14 =20 /* >=3D v12 DPU */ +#define LM_BG_SRC_SEL_V12 0x14 +#define LM_BG_SRC_SEL_V12_RESET_VALUE 0x0000c0c0 #define LM_BORDER_COLOR_0_V12 0x1c #define LM_BORDER_COLOR_1_V12 0x20 =20 /* >=3D v12 DPU with offset to mixer base + stage base */ +#define LM_BLEND0_FG_SRC_SEL_V12 0x04 #define LM_BLEND0_CONST_ALPHA_V12 0x08 +#define LM_FG_COLOR_FILL_COLOR_0_V12 0x0c +#define LM_FG_COLOR_FILL_COLOR_1_V12 0x10 +#define LM_FG_COLOR_FILL_SIZE_V12 0x14 +#define LM_FG_COLOR_FILL_XY_V12 0x18 + #define LM_BLEND0_FG_ALPHA 0x04 #define LM_BLEND0_BG_ALPHA 0x08 =20 @@ -215,6 +223,122 @@ static void dpu_hw_lm_setup_color3_v12(struct dpu_hw_= mixer *ctx, } } =20 +static int _set_staged_sspp(u32 stage, struct dpu_hw_stage_cfg *stage_cfg, + int pipes_per_stage, u32 *value) +{ + int i; + u32 pipe_type =3D 0, pipe_id =3D 0, rec_id =3D 0; + u32 src_sel[PIPES_PER_STAGE]; + + *value =3D LM_BG_SRC_SEL_V12_RESET_VALUE; + if (!stage_cfg || !pipes_per_stage) + return 0; + + for (i =3D 0; i < pipes_per_stage; i++) { + enum dpu_sspp pipe =3D stage_cfg->stage[stage][i]; + enum dpu_sspp_multirect_index rect_index =3D stage_cfg->multirect_index[= stage][i]; + + src_sel[i] =3D LM_BG_SRC_SEL_V12_RESET_VALUE; + + if (!pipe) + continue; + + /* translate pipe data to SWI pipe_type, pipe_id */ + if (pipe >=3D SSPP_DMA0 && pipe <=3D SSPP_DMA5) { + pipe_type =3D 0; + pipe_id =3D pipe - SSPP_DMA0; + } else if (pipe >=3D SSPP_VIG0 && pipe <=3D SSPP_VIG3) { + pipe_type =3D 1; + pipe_id =3D pipe - SSPP_VIG0; + } else { + DPU_ERROR("invalid rec-%d pipe:%d\n", i, pipe); + return -EINVAL; + } + + /* translate rec data to SWI rec_id */ + if (rect_index =3D=3D DPU_SSPP_RECT_SOLO || rect_index =3D=3D DPU_SSPP_R= ECT_0) { + rec_id =3D 0; + } else if (rect_index =3D=3D DPU_SSPP_RECT_1) { + rec_id =3D 1; + } else { + DPU_ERROR("invalid rec-%d rect_index:%d\n", i, rect_index); + rec_id =3D 0; + } + + /* calculate SWI value for rec-0 and rec-1 and store it temporary buffer= */ + src_sel[i] =3D (((pipe_type & 0x3) << 6) | ((rec_id & 0x3) << 4) | (pipe= _id & 0xf)); + } + + /* calculate final SWI register value for rec-0 and rec-1 */ + *value =3D 0; + for (i =3D 0; i < pipes_per_stage; i++) + *value |=3D src_sel[i] << (i * 8); + + return 0; +} + +static int dpu_hw_lm_setup_blendstage(struct dpu_hw_mixer *ctx, enum dpu_l= m lm, + struct dpu_hw_stage_cfg *stage_cfg) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int i, ret, stages, stage_off, pipes_per_stage; + u32 value; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return -EINVAL; + + if (ctx->cap->sourcesplit) + pipes_per_stage =3D PIPES_PER_STAGE; + else + pipes_per_stage =3D 1; + + /* + * When stage configuration is empty, we can enable the + * border color by setting the corresponding LAYER_ACTIVE bit + * and un-staging all the pipes from the layer mixer. + */ + if (!stage_cfg) + DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE); + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (stage_off < 0) + return stage_off; + + ret =3D _set_staged_sspp(i, stage_cfg, pipes_per_stage, &value); + if (ret) + return ret; + + DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, value); + } + + return 0; +} + +static int dpu_hw_lm_clear_all_blendstages(struct dpu_hw_mixer *ctx) +{ + struct dpu_hw_blk_reg_map *c =3D &ctx->hw; + int i, stages, stage_off; + + stages =3D ctx->cap->sblk->maxblendstages; + if (stages <=3D 0) + return -EINVAL; + + DPU_REG_WRITE(c, LM_BG_SRC_SEL_V12, LM_BG_SRC_SEL_V12_RESET_VALUE); + + for (i =3D DPU_STAGE_0; i <=3D stages; i++) { + stage_off =3D _stage_offset(ctx, i); + if (stage_off < 0) + return stage_off; + + DPU_REG_WRITE(c, LM_BLEND0_FG_SRC_SEL_V12 + stage_off, + LM_BG_SRC_SEL_V12_RESET_VALUE); + } + + return 0; +} + /** * dpu_hw_lm_init() - Initializes the mixer hw driver object. * should be called once before accessing every mixer. @@ -257,6 +381,8 @@ struct dpu_hw_mixer *dpu_hw_lm_init(struct drm_device *= dev, c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color; } else { c->ops.setup_alpha_out =3D dpu_hw_lm_setup_color3_v12; + c->ops.setup_blendstage =3D dpu_hw_lm_setup_blendstage; + c->ops.clear_all_blendstages =3D dpu_hw_lm_clear_all_blendstages; c->ops.setup_border_color =3D dpu_hw_lm_setup_border_color_v12; } c->ops.setup_misr =3D dpu_hw_lm_setup_misr; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h b/drivers/gpu/drm/ms= m/disp/dpu1/dpu_hw_lm.h index fff1156add683fec8ce6785e7fe1d769d0de3fe0..1b9ecd082d7fd72b07008787e1c= aea968ed23376 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h @@ -11,6 +11,7 @@ #include "dpu_hw_util.h" =20 struct dpu_hw_mixer; +struct dpu_hw_stage_cfg; =20 struct dpu_hw_mixer_cfg { u32 out_width; @@ -48,6 +49,23 @@ struct dpu_hw_lm_ops { */ void (*setup_alpha_out)(struct dpu_hw_mixer *ctx, uint32_t mixer_op); =20 + /** + * Clear layer mixer to pipe configuration + * @ctx : mixer ctx pointer + * Returns: 0 on success or -error + */ + int (*clear_all_blendstages)(struct dpu_hw_mixer *ctx); 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a=openpgp; fpr=9BD07E0E0C51F8D59677B7541B93437D3B41629B Add support for the Qualcomm SM8750 platform. Reviewed-by: Dmitry Baryshkov Signed-off-by: Krzysztof Kozlowski --- drivers/gpu/drm/msm/msm_mdss.c | 33 +++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mdss.h | 1 + 2 files changed, 34 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_mdss.c b/drivers/gpu/drm/msm/msm_mdss.c index dcb49fd30402b80edd2cb5971f95a78eaad6081f..3f00eb6de3a9d2bee7637c6f516= efff78b7d872b 100644 --- a/drivers/gpu/drm/msm/msm_mdss.c +++ b/drivers/gpu/drm/msm/msm_mdss.c @@ -222,6 +222,24 @@ static void msm_mdss_setup_ubwc_dec_40(struct msm_mdss= *msm_mdss) } } =20 +static void msm_mdss_setup_ubwc_dec_50(struct msm_mdss *msm_mdss) +{ + const struct msm_mdss_data *data =3D msm_mdss->mdss_data; + u32 value =3D MDSS_UBWC_STATIC_UBWC_SWIZZLE(data->ubwc_swizzle) | + MDSS_UBWC_STATIC_HIGHEST_BANK_BIT(data->highest_bank_bit); + + if (data->ubwc_bank_spread) + value |=3D MDSS_UBWC_STATIC_UBWC_BANK_SPREAD; + + if (data->macrotile_mode) + value |=3D MDSS_UBWC_STATIC_MACROTILE_MODE; + + writel_relaxed(value, msm_mdss->mmio + REG_MDSS_UBWC_STATIC); + + writel_relaxed(4, msm_mdss->mmio + REG_MDSS_UBWC_CTRL_2); + writel_relaxed(1, msm_mdss->mmio + REG_MDSS_UBWC_PREDICTION_MODE); +} + #define MDSS_HW_MAJ_MIN \ (MDSS_HW_VERSION_MAJOR__MASK | MDSS_HW_VERSION_MINOR__MASK) =20 @@ -339,6 +357,9 @@ static int msm_mdss_enable(struct msm_mdss *msm_mdss) case UBWC_4_3: msm_mdss_setup_ubwc_dec_40(msm_mdss); break; + case UBWC_5_0: + msm_mdss_setup_ubwc_dec_50(msm_mdss); + break; default: dev_err(msm_mdss->dev, "Unsupported UBWC decoder version %x\n", msm_mdss->mdss_data->ubwc_dec_version); @@ -722,6 +743,17 @@ static const struct msm_mdss_data sm8550_data =3D { .reg_bus_bw =3D 57000, }; =20 +static const struct msm_mdss_data sm8750_data =3D { + .ubwc_enc_version =3D UBWC_5_0, + .ubwc_dec_version =3D UBWC_5_0, + .ubwc_swizzle =3D 6, + .ubwc_bank_spread =3D true, + /* TODO: highest_bank_bit =3D 2 for LP_DDR4 */ + .highest_bank_bit =3D 3, + .macrotile_mode =3D true, + .reg_bus_bw =3D 57000, +}; + static const struct msm_mdss_data x1e80100_data =3D { .ubwc_enc_version =3D UBWC_4_0, .ubwc_dec_version =3D UBWC_4_3, @@ -756,6 +788,7 @@ static const struct of_device_id mdss_dt_match[] =3D { { .compatible =3D "qcom,sm8450-mdss", .data =3D &sm8350_data }, { .compatible =3D "qcom,sm8550-mdss", .data =3D &sm8550_data }, { .compatible =3D "qcom,sm8650-mdss", .data =3D &sm8550_data}, + { .compatible =3D "qcom,sm8750-mdss", .data =3D &sm8750_data}, { .compatible =3D "qcom,x1e80100-mdss", .data =3D &x1e80100_data}, {} }; diff --git a/drivers/gpu/drm/msm/msm_mdss.h b/drivers/gpu/drm/msm/msm_mdss.h index 14dc53704314558841ee1fe08d93309fd2233812..dd0160c6ba1a297cea5b87cd8b0= 3895b2aa08213 100644 --- a/drivers/gpu/drm/msm/msm_mdss.h +++ b/drivers/gpu/drm/msm/msm_mdss.h @@ -22,6 +22,7 @@ struct msm_mdss_data { #define UBWC_3_0 0x30000000 #define UBWC_4_0 0x40000000 #define UBWC_4_3 0x40030000 +#define UBWC_5_0 0x50000000 =20 const struct msm_mdss_data *msm_mdss_get_mdss_data(struct device *dev); =20 --=20 2.43.0