From nobody Mon Feb 9 23:42:40 2026 Received: from mx08-00376f01.pphosted.com (mx08-00376f01.pphosted.com [91.207.212.86]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F615227BB9; Mon, 10 Mar 2025 13:20:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.86 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741612843; cv=none; b=WPChbw4tKuXlCOWHBqydtTi2bwCP7pVPh4SKsTBcfkV3Vvsa2D0ZWBBKYzGkPWpoqTDwWn8kRzk9hWK99iPdkZN5tdtxODDQsTzAl3fqiOp4o8HKkKD9GxJOmOfC4FQ+igvivqiu1jivY7ky2BK9Y0SXfTcTpsWxZYoxGpEoEbE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741612843; c=relaxed/simple; bh=0aAy3lx4xJkC3E9Cd63Ve1a6BcqvYVGktGJkeezfx+k=; h=From:Date:Subject:MIME-Version:Content-Type:Message-ID:References: In-Reply-To:To:CC; b=rW1KlI/7o0KdDuaxnHz9jZWr54R+0bker/msur21xA+Hy3bZwyxantxdD88U+t5TQ1uuoqyIi0FG/aam9fMnRJrdk0vFp7J1qrnu8B3yOe8uRuXtECKItwnzthPO6ntAcub+KQX6oST9l+rlbnsPepkk9dxo7zr2v8wVk/ki8P0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com; spf=pass smtp.mailfrom=imgtec.com; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b=FFHMnZrC; arc=none smtp.client-ip=91.207.212.86 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=imgtec.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=imgtec.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=imgtec.com header.i=@imgtec.com header.b="FFHMnZrC" Received: from pps.filterd (m0168888.ppops.net [127.0.0.1]) by mx08-00376f01.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 52A7nW1j015329; Mon, 10 Mar 2025 13:10:52 GMT DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=imgtec.com; h=cc :content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=dk201812; bh=8 /EUoXyBm6cHGSTMYecQTdr7cNf+/afjOP6sdNTj7Ys=; b=FFHMnZrC4ts79rN8j sfYcAnJsVQ0DqAVMMaN9zxiPPGfvxUDBa0N7c953YWCj1/s4OuAwo6xFX7GUlb1q krkSr9jCT+O2CgGpFRElyynN+rd9K5MryoC+dte4QMwF/ntGsutc8yNA5FcLdHgl 4dlmstDmE4GuFUgYNvSxPSwsivZhjsT6vyq2vm7czTXQqFyOeKosl5Z9W+JVfy7L aAga6w8hNBZz6UgRRGekBfPXB8zhHBtl4IMxnodZ8CjI+U6TFbaMCw/wowIEJxuP HP0fbl5FJpmJDpWanw6GFbmdY7yUumE6+FQDqVT5OfGCwox7Brc9bdZbUYC/7AMQ NZrKA== Received: from hhmail05.hh.imgtec.org (83-244-153-141.cust-83.exponential-e.net [83.244.153.141]) by mx08-00376f01.pphosted.com (PPS) with ESMTPS id 458d1wha4r-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128 verify=NOT); Mon, 10 Mar 2025 13:10:52 +0000 (GMT) Received: from Matts-MacBook-Pro.local (172.25.0.133) by HHMAIL05.hh.imgtec.org (10.100.10.120) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.44; Mon, 10 Mar 2025 13:10:50 +0000 From: Matt Coster Date: Mon, 10 Mar 2025 13:10:34 +0000 Subject: [PATCH v3 10/18] drm/imagination: Make has_fixed_data_addr a value Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-ID: <20250310-sets-bxs-4-64-patch-v1-v3-10-143b3dbef02f@imgtec.com> References: <20250310-sets-bxs-4-64-patch-v1-v3-0-143b3dbef02f@imgtec.com> In-Reply-To: <20250310-sets-bxs-4-64-patch-v1-v3-0-143b3dbef02f@imgtec.com> To: Frank Binns , Matt Coster , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Nishanth Menon , "Vignesh Raghavendra" , Tero Kristo CC: , , , , Randolph Sapp , Darren Etheridge , "Alessio Belle" , Alexandru Dadu X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=4962; i=matt.coster@imgtec.com; h=from:subject:message-id; bh=0aAy3lx4xJkC3E9Cd63Ve1a6BcqvYVGktGJkeezfx+k=; b=owGbwMvMwCFWuUfy8817WRsYT6slMaSfe3Lxbf+lGgkxu1Ohmqp7Ozev8kg45sLUqKg8M7sth PnizbTlHaUsDGIcDLJiiiw7VliuUPujpiVx41cxzBxWJpAhDFycAjCRy8sZ/mn9izG+3nr+Yn2M egLHstO3Qh9EnK5Z412ecPjX6h2bM8wYGdpnlRoJPatdVLE7zSVXyUzyWcVxZzFV8fcB59W27W3 nYgIA X-Developer-Key: i=matt.coster@imgtec.com; a=openpgp; fpr=05A40CFCE7269D61D97100A1747F0A9036F90DFA X-EXCLAIMER-MD-CONFIG: 15a78312-3e47-46eb-9010-2e54d84a9631 X-Proofpoint-ORIG-GUID: dzPObRdYR2knv7jfZ1aTigmpgYO65JjU X-Proofpoint-GUID: dzPObRdYR2knv7jfZ1aTigmpgYO65JjU X-Authority-Analysis: v=2.4 cv=U8+SDfru c=1 sm=1 tr=0 ts=67cee4dc cx=c_pps a=AKOq//PuzOIrVTIF9yBwbA==:117 a=AKOq//PuzOIrVTIF9yBwbA==:17 a=ETbM1kImDFEA:10 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=VwQbUJbxAAAA:8 a=r_1tXGB3AAAA:8 a=_sBYpape5WJv0mR81mQA:9 a=QEXdDO2ut3YA:10 a=t8nPyN_e6usw4ciXM-Pk:22 This is currently a callback function which takes no parameters; there's no reason for this so let's make it a straightforward value in pvr_fw_defs. Signed-off-by: Matt Coster --- Changes in v3: - None - Link to v2: https://lore.kernel.org/r/20241118-sets-bxs-4-64-patch-v1-v2-= 11-3fd45d9fb0cf@imgtec.com Changes in v2: - None - Link to v1: https://lore.kernel.org/r/20241105-sets-bxs-4-64-patch-v1-v1-= 12-4ed30e865892@imgtec.com --- drivers/gpu/drm/imagination/pvr_fw.c | 2 +- drivers/gpu/drm/imagination/pvr_fw.h | 23 ++++++++--------------- drivers/gpu/drm/imagination/pvr_fw_meta.c | 8 +------- drivers/gpu/drm/imagination/pvr_fw_mips.c | 8 +------- 4 files changed, 11 insertions(+), 30 deletions(-) diff --git a/drivers/gpu/drm/imagination/pvr_fw.c b/drivers/gpu/drm/imagina= tion/pvr_fw.c index 9147c70edc0ef4e86d0b24c3568a43efbafb6bd8..c331d6001550a0b1d9cfbda2cd6= 629533ab6ee33 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.c +++ b/drivers/gpu/drm/imagination/pvr_fw.c @@ -666,7 +666,7 @@ pvr_fw_process(struct pvr_device *pvr_dev) return PTR_ERR(fw_code_ptr); } =20 - if (pvr_dev->fw_dev.defs->has_fixed_data_addr()) { + if (pvr_dev->fw_dev.defs->has_fixed_data_addr) { u32 base_addr =3D private_data->base_addr & pvr_dev->fw_dev.fw_heap_info= .offset_mask; =20 fw_data_ptr =3D diff --git a/drivers/gpu/drm/imagination/pvr_fw.h b/drivers/gpu/drm/imagina= tion/pvr_fw.h index eead744835726712622d5aba9b3480fe264a089f..180d310074e3585c641e540a9e2= 576b5ab2a5705 100644 --- a/drivers/gpu/drm/imagination/pvr_fw.h +++ b/drivers/gpu/drm/imagination/pvr_fw.h @@ -166,21 +166,6 @@ struct pvr_fw_defs { */ int (*wrapper_init)(struct pvr_device *pvr_dev); =20 - /** - * @has_fixed_data_addr: - * - * Called to check if firmware fixed data must be loaded at the address g= iven by the - * firmware layout table. - * - * This function is mandatory. - * - * Returns: - * * %true if firmware fixed data must be loaded at the address given by= the firmware - * layout table. - * * %false otherwise. - */ - bool (*has_fixed_data_addr)(void); - /** * @irq: FW Interrupt information. * @@ -205,6 +190,14 @@ struct pvr_fw_defs { /** @clear_mask: Value to write to the clear_reg in order to clear FW IR= Qs. */ u32 clear_mask; } irq; + + /** + * @has_fixed_data_addr: Specify whether the firmware fixed data must be = loaded at the + * address given by the firmware layout table. + * + * This value is mandatory. + */ + bool has_fixed_data_addr; }; =20 /** diff --git a/drivers/gpu/drm/imagination/pvr_fw_meta.c b/drivers/gpu/drm/im= agination/pvr_fw_meta.c index cf86701ca8f14920329ccb4c2811424b0c394b14..4433b04e0adb3684b86a4e90f63= d670a81ecd826 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_meta.c +++ b/drivers/gpu/drm/imagination/pvr_fw_meta.c @@ -531,12 +531,6 @@ pvr_meta_vm_unmap(struct pvr_device *pvr_dev, struct p= vr_fw_object *fw_obj) fw_obj->fw_mm_node.size); } =20 -static bool -pvr_meta_has_fixed_data_addr(void) -{ - return false; -} - const struct pvr_fw_defs pvr_fw_defs_meta =3D { .init =3D pvr_meta_init, .fw_process =3D pvr_meta_fw_process, @@ -544,11 +538,11 @@ const struct pvr_fw_defs pvr_fw_defs_meta =3D { .vm_unmap =3D pvr_meta_vm_unmap, .get_fw_addr_with_offset =3D pvr_meta_get_fw_addr_with_offset, .wrapper_init =3D pvr_meta_wrapper_init, - .has_fixed_data_addr =3D pvr_meta_has_fixed_data_addr, .irq =3D { .status_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .clear_reg =3D ROGUE_CR_META_SP_MSLVIRQSTATUS, .status_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_EN, .clear_mask =3D ROGUE_CR_META_SP_MSLVIRQSTATUS_TRIGVECT2_CLRMSK, }, + .has_fixed_data_addr =3D false, }; diff --git a/drivers/gpu/drm/imagination/pvr_fw_mips.c b/drivers/gpu/drm/im= agination/pvr_fw_mips.c index f195c602bb112066e88210d0106cb5ffc0a9abc6..2c3172841886b70eb7a9992ec38= 51f18adcad8d5 100644 --- a/drivers/gpu/drm/imagination/pvr_fw_mips.c +++ b/drivers/gpu/drm/imagination/pvr_fw_mips.c @@ -227,12 +227,6 @@ pvr_mips_get_fw_addr_with_offset(struct pvr_fw_object = *fw_obj, u32 offset) ROGUE_FW_HEAP_MIPS_BASE; } =20 -static bool -pvr_mips_has_fixed_data_addr(void) -{ - return true; -} - const struct pvr_fw_defs pvr_fw_defs_mips =3D { .init =3D pvr_mips_init, .fini =3D pvr_mips_fini, @@ -241,11 +235,11 @@ const struct pvr_fw_defs pvr_fw_defs_mips =3D { .vm_unmap =3D pvr_vm_mips_unmap, .get_fw_addr_with_offset =3D pvr_mips_get_fw_addr_with_offset, .wrapper_init =3D pvr_mips_wrapper_init, - .has_fixed_data_addr =3D pvr_mips_has_fixed_data_addr, .irq =3D { .status_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS, .clear_reg =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR, .status_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_STATUS_EVENT_EN, .clear_mask =3D ROGUE_CR_MIPS_WRAPPER_IRQ_CLEAR_EVENT_EN, }, + .has_fixed_data_addr =3D true, }; --=20 2.48.1