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Mon, 10 Mar 2025 05:40:26 -0700 (PDT) From: Bartosz Golaszewski Date: Mon, 10 Mar 2025 13:40:15 +0100 Subject: [PATCH 01/15] gpio: bcm-kona: use lock guards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250310-gpiochip-set-conversion-v1-1-03798bb833eb@linaro.org> References: <20250310-gpiochip-set-conversion-v1-0-03798bb833eb@linaro.org> In-Reply-To: <20250310-gpiochip-set-conversion-v1-0-03798bb833eb@linaro.org> To: Ray Jui , Broadcom internal kernel review list , Linus Walleij , Bartosz Golaszewski , Florian Fainelli , Scott Branden , Matti Vaittinen , Marek Vasut , Michael Buesch , Thomas Richard , Eugeniy Paltsev , Benson Leung , Guenter Roeck , Andy Shevchenko , Support Opensource Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, chrome-platform@lists.linux.dev, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Reduce the code complexity by using automatic lock guards with the raw spinlock. Signed-off-by: Bartosz Golaszewski --- drivers/gpio/gpio-bcm-kona.c | 64 +++++++++++++---------------------------= ---- 1 file changed, 18 insertions(+), 46 deletions(-) diff --git a/drivers/gpio/gpio-bcm-kona.c b/drivers/gpio/gpio-bcm-kona.c index 64908f1a5e7f..a7390b1f1173 100644 --- a/drivers/gpio/gpio-bcm-kona.c +++ b/drivers/gpio/gpio-bcm-kona.c @@ -7,6 +7,7 @@ */ =20 #include +#include #include #include #include @@ -100,7 +101,6 @@ static void bcm_kona_gpio_lock_gpio(struct bcm_kona_gpi= o *kona_gpio, unsigned gpio) { u32 val; - unsigned long flags; int bank_id =3D GPIO_BANK(gpio); int bit =3D GPIO_BIT(gpio); struct bcm_kona_gpio_bank *bank =3D &kona_gpio->banks[bank_id]; @@ -112,13 +112,11 @@ static void bcm_kona_gpio_lock_gpio(struct bcm_kona_g= pio *kona_gpio, } =20 if (--bank->gpio_unlock_count[bit] =3D=3D 0) { - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); val |=3D BIT(bit); bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); - - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); } } =20 @@ -126,19 +124,16 @@ static void bcm_kona_gpio_unlock_gpio(struct bcm_kona= _gpio *kona_gpio, unsigned gpio) { u32 val; - unsigned long flags; int bank_id =3D GPIO_BANK(gpio); int bit =3D GPIO_BIT(gpio); struct bcm_kona_gpio_bank *bank =3D &kona_gpio->banks[bank_id]; =20 if (bank->gpio_unlock_count[bit] =3D=3D 0) { - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(kona_gpio->reg_base + GPIO_PWD_STATUS(bank_id)); val &=3D ~BIT(bit); bcm_kona_gpio_write_lock_regs(kona_gpio->reg_base, bank_id, val); - - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); } =20 ++bank->gpio_unlock_count[bit]; @@ -161,24 +156,21 @@ static void bcm_kona_gpio_set(struct gpio_chip *chip,= unsigned gpio, int value) int bank_id =3D GPIO_BANK(gpio); int bit =3D GPIO_BIT(gpio); u32 val, reg_offset; - unsigned long flags; =20 kona_gpio =3D gpiochip_get_data(chip); reg_base =3D kona_gpio->reg_base; - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 /* this function only applies to output pin */ if (bcm_kona_gpio_get_dir(chip, gpio) =3D=3D GPIO_LINE_DIRECTION_IN) - goto out; + return; =20 reg_offset =3D value ? GPIO_OUT_SET(bank_id) : GPIO_OUT_CLEAR(bank_id); =20 val =3D readl(reg_base + reg_offset); val |=3D BIT(bit); writel(val, reg_base + reg_offset); - -out: - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); } =20 static int bcm_kona_gpio_get(struct gpio_chip *chip, unsigned gpio) @@ -188,11 +180,11 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, = unsigned gpio) int bank_id =3D GPIO_BANK(gpio); int bit =3D GPIO_BIT(gpio); u32 val, reg_offset; - unsigned long flags; =20 kona_gpio =3D gpiochip_get_data(chip); reg_base =3D kona_gpio->reg_base; - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 if (bcm_kona_gpio_get_dir(chip, gpio) =3D=3D GPIO_LINE_DIRECTION_IN) reg_offset =3D GPIO_IN_STATUS(bank_id); @@ -202,8 +194,6 @@ static int bcm_kona_gpio_get(struct gpio_chip *chip, un= signed gpio) /* read the GPIO bank status */ val =3D readl(reg_base + reg_offset); =20 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); - /* return the specified bit status */ return !!(val & BIT(bit)); } @@ -228,19 +218,17 @@ static int bcm_kona_gpio_direction_input(struct gpio_= chip *chip, unsigned gpio) struct bcm_kona_gpio *kona_gpio; void __iomem *reg_base; u32 val; - unsigned long flags; =20 kona_gpio =3D gpiochip_get_data(chip); reg_base =3D kona_gpio->reg_base; - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(reg_base + GPIO_CONTROL(gpio)); val &=3D ~GPIO_GPCTR0_IOTR_MASK; val |=3D GPIO_GPCTR0_IOTR_CMD_INPUT; writel(val, reg_base + GPIO_CONTROL(gpio)); =20 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); - return 0; } =20 @@ -252,11 +240,11 @@ static int bcm_kona_gpio_direction_output(struct gpio= _chip *chip, int bank_id =3D GPIO_BANK(gpio); int bit =3D GPIO_BIT(gpio); u32 val, reg_offset; - unsigned long flags; =20 kona_gpio =3D gpiochip_get_data(chip); reg_base =3D kona_gpio->reg_base; - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(reg_base + GPIO_CONTROL(gpio)); val &=3D ~GPIO_GPCTR0_IOTR_MASK; @@ -268,8 +256,6 @@ static int bcm_kona_gpio_direction_output(struct gpio_c= hip *chip, val |=3D BIT(bit); writel(val, reg_base + reg_offset); =20 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); - return 0; } =20 @@ -289,7 +275,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip = *chip, unsigned gpio, struct bcm_kona_gpio *kona_gpio; void __iomem *reg_base; u32 val, res; - unsigned long flags; =20 kona_gpio =3D gpiochip_get_data(chip); reg_base =3D kona_gpio->reg_base; @@ -312,7 +297,7 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip = *chip, unsigned gpio, } =20 /* spin lock for read-modify-write of the GPIO register */ - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(reg_base + GPIO_CONTROL(gpio)); val &=3D ~GPIO_GPCTR0_DBR_MASK; @@ -327,8 +312,6 @@ static int bcm_kona_gpio_set_debounce(struct gpio_chip = *chip, unsigned gpio, =20 writel(val, reg_base + GPIO_CONTROL(gpio)); =20 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); - return 0; } =20 @@ -367,17 +350,15 @@ static void bcm_kona_gpio_irq_ack(struct irq_data *d) int bank_id =3D GPIO_BANK(gpio); int bit =3D GPIO_BIT(gpio); u32 val; - unsigned long flags; =20 kona_gpio =3D irq_data_get_irq_chip_data(d); reg_base =3D kona_gpio->reg_base; - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(reg_base + GPIO_INT_STATUS(bank_id)); val |=3D BIT(bit); writel(val, reg_base + GPIO_INT_STATUS(bank_id)); - - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); } =20 static void bcm_kona_gpio_irq_mask(struct irq_data *d) @@ -388,19 +369,16 @@ static void bcm_kona_gpio_irq_mask(struct irq_data *d) int bank_id =3D GPIO_BANK(gpio); int bit =3D GPIO_BIT(gpio); u32 val; - unsigned long flags; =20 kona_gpio =3D irq_data_get_irq_chip_data(d); reg_base =3D kona_gpio->reg_base; =20 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(reg_base + GPIO_INT_MASK(bank_id)); val |=3D BIT(bit); writel(val, reg_base + GPIO_INT_MASK(bank_id)); gpiochip_disable_irq(&kona_gpio->gpio_chip, gpio); - - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); } =20 static void bcm_kona_gpio_irq_unmask(struct irq_data *d) @@ -411,19 +389,16 @@ static void bcm_kona_gpio_irq_unmask(struct irq_data = *d) int bank_id =3D GPIO_BANK(gpio); int bit =3D GPIO_BIT(gpio); u32 val; - unsigned long flags; =20 kona_gpio =3D irq_data_get_irq_chip_data(d); reg_base =3D kona_gpio->reg_base; =20 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(reg_base + GPIO_INT_MSKCLR(bank_id)); val |=3D BIT(bit); writel(val, reg_base + GPIO_INT_MSKCLR(bank_id)); gpiochip_enable_irq(&kona_gpio->gpio_chip, gpio); - - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); } =20 static int bcm_kona_gpio_irq_set_type(struct irq_data *d, unsigned int typ= e) @@ -433,7 +408,6 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data *= d, unsigned int type) unsigned gpio =3D d->hwirq; u32 lvl_type; u32 val; - unsigned long flags; =20 kona_gpio =3D irq_data_get_irq_chip_data(d); reg_base =3D kona_gpio->reg_base; @@ -459,15 +433,13 @@ static int bcm_kona_gpio_irq_set_type(struct irq_data= *d, unsigned int type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&kona_gpio->lock, flags); + guard(raw_spinlock_irqsave)(&kona_gpio->lock); =20 val =3D readl(reg_base + GPIO_CONTROL(gpio)); val &=3D ~GPIO_GPCTR0_ITR_MASK; val |=3D lvl_type << GPIO_GPCTR0_ITR_SHIFT; writel(val, reg_base + GPIO_CONTROL(gpio)); =20 - raw_spin_unlock_irqrestore(&kona_gpio->lock, flags); - return 0; } =20 --=20 2.45.2