From nobody Mon Feb 9 16:17:22 2026 Received: from smtp.forwardemail.net (smtp.forwardemail.net [121.127.44.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66063221F2C for ; Sun, 9 Mar 2025 23:26:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=121.127.44.59 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741562809; cv=none; b=nL1K92nDrgU95cf7s3djNps1Spuih8L2tsKB/t+wDW8sqmiPGDG8eu2kPIAIh8tcAn7/5P6SFNVfgihcDRxGAlUsCerERfJ8NM8eLVXqExe7pBxnZe6y/D/xOtsphFUstZQ0HbeSltsW0z607mdsx8YAoSTudFClepxh6JijZHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741562809; c=relaxed/simple; bh=Ye1w4Xf7ZWApiDedQEpp21B/luCwhlOObLVIDQkyMvI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oJBpasy/Tdc8UcecoZPfkzCYIZR0M7hudbqvpvUykUAeRa6mQvAKqH50e0tDOpLIh9Sawov7KISa0xhR1WMsNea/PTy+2OffjPoNKR/nRKAsIOdfo2z2e0qtUkPg+LTEoIRelFG4Rxv9QYQtvSpinnPeuFNw1roy7dY5v8pD3i4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kwiboo.se; spf=pass smtp.mailfrom=fe-bounces.kwiboo.se; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b=irGSPVqI; arc=none smtp.client-ip=121.127.44.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fe-bounces.kwiboo.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b="irGSPVqI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1741562801; bh=2jP79B1Ed/lOppu7HCdq/Ku7htiNFELnS+0Jz8AUjPk=; b=irGSPVqIOD3cp/eveJe5byzw8IqL+m/C3Fp4mNFaf9R8ZUl5fKXwg6VuOoPaMg7jYXD/uW7Re +5HSF92HsVDHn4JcyacpCwKyf/a12SQkcmPMHttv9pdpldDTT4q8tPOOEHxFJ21W1CBZ8IP+ZRB /TVChz1SnbYII5ye5rszt/5zFaTiqwRQh6k93FsTJcyeUyiwSeI1CUFszs2RGHzeRkcuk6T1y2H B0b+T/TC/BG7UPmAcXCNFrF1FKcUNp/OR+N/qv80K/CbjQyp8/VRk9aiFqAogp1U8C2ZWTUsLk3 +iey/plPzeth2PX1/aSWKLhrc/mptvPwa/OQcwRn2T2w== X-Forward-Email-ID: 67ce23ae5209992d7c670e83 X-Forward-Email-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 121.127.44.59 X-Forward-Email-Version: 0.4.40 X-Forward-Email-Website: https://forwardemail.net X-Complaints-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Report-Abuse-To: abuse@forwardemail.net From: Jonas Karlman To: Heiko Stuebner , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Wu , Yao Zi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 2/5] net: stmmac: dwmac-rk: Add GMAC support for RK3528 Date: Sun, 9 Mar 2025 23:26:12 +0000 Message-ID: <20250309232622.1498084-3-jonas@kwiboo.se> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309232622.1498084-1-jonas@kwiboo.se> References: <20250309232622.1498084-1-jonas@kwiboo.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: David Wu Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add initial support for the RK3528 GMAC variant. Signed-off-by: David Wu Signed-off-by: Jonas Karlman --- Changes in v2: - None Power up/down of the integrated PHY is added in a separate patch. --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/e= thernet/stmicro/stmmac/dwmac-rk.c index 342463587d06..03ea9368ffbb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -828,6 +828,137 @@ static const struct rk_gmac_ops rk3399_ops =3D { .set_rmii_speed =3D rk3399_set_rmii_speed, }; =20 +#define RK3528_VO_GRF_GMAC_CON 0x0018 +#define RK3528_VO_GRF_MACPHY_CON0 0x001c +#define RK3528_VO_GRF_MACPHY_CON1 0x0020 +#define RK3528_VPU_GRF_GMAC_CON5 0x0018 +#define RK3528_VPU_GRF_GMAC_CON6 0x001c + +#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) +#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) +#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) +#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) + +#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) +#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) + +#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) +#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) +#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) + +#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) +#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) + +#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) +#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) +#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) +#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) + +#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) +#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) +#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) + +#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) +#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) +#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) +#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) + +static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) +{ + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_PHY_INTF_SEL_RGMII); + + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + DELAY_ENABLE(RK3528, tx_delay, rx_delay)); + + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, + RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | + RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); +} + +static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) +{ + if (bsp_priv->id =3D=3D 1) + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_PHY_INTF_SEL_RMII); + else + regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, + RK3528_GMAC0_PHY_INTF_SEL_RMII | + RK3528_GMAC0_CLK_RMII_DIV2); +} + +static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int spee= d) +{ + struct device *dev =3D &bsp_priv->pdev->dev; + + if (speed =3D=3D 10) + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_CLK_RGMII_DIV50); + else if (speed =3D=3D 100) + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_CLK_RGMII_DIV5); + else if (speed =3D=3D 1000) + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_CLK_RGMII_DIV1); + else + dev_err(dev, "unknown speed value for RGMII! speed=3D%d", speed); +} + +static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) +{ + struct device *dev =3D &bsp_priv->pdev->dev; + unsigned int reg, val; + + if (speed =3D=3D 10) + val =3D bsp_priv->id =3D=3D 1 ? RK3528_GMAC1_CLK_RMII_DIV20 : + RK3528_GMAC0_CLK_RMII_DIV20; + else if (speed =3D=3D 100) + val =3D bsp_priv->id =3D=3D 1 ? RK3528_GMAC1_CLK_RMII_DIV2 : + RK3528_GMAC0_CLK_RMII_DIV2; + else { + dev_err(dev, "unknown speed value for RMII! speed=3D%d", speed); + return; + } + + reg =3D bsp_priv->id =3D=3D 1 ? RK3528_VPU_GRF_GMAC_CON5 : + RK3528_VO_GRF_GMAC_CON; + + regmap_write(bsp_priv->grf, reg, val); +} + +static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, + bool input, bool enable) +{ + unsigned int val; + + if (bsp_priv->id =3D=3D 1) { + val =3D input ? RK3528_GMAC1_CLK_SELECT_IO : + RK3528_GMAC1_CLK_SELECT_CRU; + val |=3D enable ? RK3528_GMAC1_CLK_RMII_NOGATE : + RK3528_GMAC1_CLK_RMII_GATE; + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); + } else { + val =3D enable ? RK3528_GMAC0_CLK_RMII_NOGATE : + RK3528_GMAC0_CLK_RMII_GATE; + regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); + } +} + +static const struct rk_gmac_ops rk3528_ops =3D { + .set_to_rgmii =3D rk3528_set_to_rgmii, + .set_to_rmii =3D rk3528_set_to_rmii, + .set_rgmii_speed =3D rk3528_set_rgmii_speed, + .set_rmii_speed =3D rk3528_set_rmii_speed, + .set_clock_selection =3D rk3528_set_clock_selection, + .regs_valid =3D true, + .regs =3D { + 0xffbd0000, /* gmac0 */ + 0xffbe0000, /* gmac1 */ + 0x0, /* sentinel */ + }, +}; + #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 @@ -1816,6 +1947,7 @@ static const struct of_device_id rk_gmac_dwmac_match[= ] =3D { { .compatible =3D "rockchip,rk3366-gmac", .data =3D &rk3366_ops }, { .compatible =3D "rockchip,rk3368-gmac", .data =3D &rk3368_ops }, { .compatible =3D "rockchip,rk3399-gmac", .data =3D &rk3399_ops }, + { .compatible =3D "rockchip,rk3528-gmac", .data =3D &rk3528_ops }, { .compatible =3D "rockchip,rk3568-gmac", .data =3D &rk3568_ops }, { .compatible =3D "rockchip,rk3576-gmac", .data =3D &rk3576_ops }, { .compatible =3D "rockchip,rk3588-gmac", .data =3D &rk3588_ops }, --=20 2.48.1