From nobody Sun Feb 8 13:32:42 2026 Received: from smtp.forwardemail.net (smtp.forwardemail.net [121.127.44.73]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 99ACF1CAA6C for ; Sun, 9 Mar 2025 23:26:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=121.127.44.73 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741562804; cv=none; b=KCU74aSaL4lLUSO+919C0BLTYe4S+0DFQd6xJkliV2pHZhaAZ09/7nJjSA6Sp4Q9Mb3k+7Yh0iEKDBgKb+hDa2zoLnGPnEcGTU8qpqhksFnAquI8AOrW4JV2QkfZviW/WGKoepAD6GiutT17vJU3U/JuvmQ39juaQfu75ZGExOE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741562804; c=relaxed/simple; bh=QgHqKYOvWVyGVZtvyCcc5NYc2fqYBSJeW421CpGLeBk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=ciRZ32gAyV7qXYCdY6W93cPpX/26o9lxg/hvizsxPXF1IIRRPNsKhVm1F5f5oyKeaWNg+xKWYOIQOtqKB7UO69LcmTVzMUBHNObqaLmPdB5SpAPtZCh+/FusphJN1Ba0Pa3PsUaxuzeNY42/0IId2Lx5pP8bTzW8gdM7BQlkVME= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kwiboo.se; spf=pass smtp.mailfrom=fe-bounces.kwiboo.se; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b=CJsfeSeB; arc=none smtp.client-ip=121.127.44.73 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fe-bounces.kwiboo.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b="CJsfeSeB" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1741562796; bh=Fvsg997oISgjqp0W2TJFAP7RLXkppIq9T5s0bg5qC1I=; b=CJsfeSeBhoF+LbwG4joLkIws7INvvldZH/GyQhk/F9f4d2yWXMAbZLNKOuKtFQnnJYnUi7Y+5 mjWvPdI8kIisZXuTodNaKZylyMNOfgUY9QJ15Pgylq9921AWXwyFd6xYDv7R4eE0rSRLv0deSDj IvGqxaWTq55nzOjKj+r7UsOXQ2RrbSMagbIfoc4wsKHBb1Kh4pscAtOuL1gu4rhTfTjK1e6wtDK VgYDXQS+k9B5Z7bR8Sz+6Y7iy/NvctWsEoe/SYsQN9P5oQ3k+rFOQWg/aLeH6shoZQQc2QDrv7Y YVwVIi0pNySL1znCSBIAttqIOJZb0lHAkLVuBz+gQGwQ== X-Forward-Email-ID: 67ce23a95209992d7c670e6e X-Forward-Email-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 121.127.44.73 X-Forward-Email-Version: 0.4.40 X-Forward-Email-Website: https://forwardemail.net X-Complaints-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Report-Abuse-To: abuse@forwardemail.net From: Jonas Karlman To: Heiko Stuebner , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Wu Cc: Yao Zi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman Subject: [PATCH v2 1/5] dt-bindings: net: rockchip-dwmac: Add compatible string for RK3528 Date: Sun, 9 Mar 2025 23:26:11 +0000 Message-ID: <20250309232622.1498084-2-jonas@kwiboo.se> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309232622.1498084-1-jonas@kwiboo.se> References: <20250309232622.1498084-1-jonas@kwiboo.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add compatible string for the RK3528 variant. Signed-off-by: Jonas Karlman Reviewed-by: Rob Herring (Arm) --- Changes in v2: - Restrict the minItems: 4 change to rockchip,rk3528-gmac The enum will be extended in a future patch, Pending RK3562 and a future RK3506 variant also only have 4 clocks. Because snps,dwmac-4.20a is already listed in snps,dwmac.yaml adding the rockchip,rk3528-gmac compatible did not seem necessary. --- .../devicetree/bindings/net/rockchip-dwmac.yaml | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml b/Do= cumentation/devicetree/bindings/net/rockchip-dwmac.yaml index 8dd870f0214d..fe417c19b597 100644 --- a/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml +++ b/Documentation/devicetree/bindings/net/rockchip-dwmac.yaml @@ -24,6 +24,7 @@ select: - rockchip,rk3366-gmac - rockchip,rk3368-gmac - rockchip,rk3399-gmac + - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac @@ -49,6 +50,7 @@ properties: - rockchip,rv1108-gmac - items: - enum: + - rockchip,rk3528-gmac - rockchip,rk3568-gmac - rockchip,rk3576-gmac - rockchip,rk3588-gmac @@ -56,7 +58,7 @@ properties: - const: snps,dwmac-4.20a =20 clocks: - minItems: 5 + minItems: 4 maxItems: 8 =20 clock-names: @@ -130,6 +132,18 @@ allOf: properties: rockchip,php-grf: false =20 + - if: + not: + properties: + compatible: + contains: + enum: + - rockchip,rk3528-gmac + then: + properties: + clocks: + minItems: 5 + unevaluatedProperties: false =20 examples: --=20 2.48.1 From nobody Sun Feb 8 13:32:42 2026 Received: from smtp.forwardemail.net (smtp.forwardemail.net [121.127.44.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 66063221F2C for ; Sun, 9 Mar 2025 23:26:47 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=121.127.44.59 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741562809; cv=none; b=nL1K92nDrgU95cf7s3djNps1Spuih8L2tsKB/t+wDW8sqmiPGDG8eu2kPIAIh8tcAn7/5P6SFNVfgihcDRxGAlUsCerERfJ8NM8eLVXqExe7pBxnZe6y/D/xOtsphFUstZQ0HbeSltsW0z607mdsx8YAoSTudFClepxh6JijZHU= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741562809; c=relaxed/simple; bh=Ye1w4Xf7ZWApiDedQEpp21B/luCwhlOObLVIDQkyMvI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=oJBpasy/Tdc8UcecoZPfkzCYIZR0M7hudbqvpvUykUAeRa6mQvAKqH50e0tDOpLIh9Sawov7KISa0xhR1WMsNea/PTy+2OffjPoNKR/nRKAsIOdfo2z2e0qtUkPg+LTEoIRelFG4Rxv9QYQtvSpinnPeuFNw1roy7dY5v8pD3i4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kwiboo.se; spf=pass smtp.mailfrom=fe-bounces.kwiboo.se; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b=irGSPVqI; arc=none smtp.client-ip=121.127.44.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fe-bounces.kwiboo.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b="irGSPVqI" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1741562801; bh=2jP79B1Ed/lOppu7HCdq/Ku7htiNFELnS+0Jz8AUjPk=; b=irGSPVqIOD3cp/eveJe5byzw8IqL+m/C3Fp4mNFaf9R8ZUl5fKXwg6VuOoPaMg7jYXD/uW7Re +5HSF92HsVDHn4JcyacpCwKyf/a12SQkcmPMHttv9pdpldDTT4q8tPOOEHxFJ21W1CBZ8IP+ZRB /TVChz1SnbYII5ye5rszt/5zFaTiqwRQh6k93FsTJcyeUyiwSeI1CUFszs2RGHzeRkcuk6T1y2H B0b+T/TC/BG7UPmAcXCNFrF1FKcUNp/OR+N/qv80K/CbjQyp8/VRk9aiFqAogp1U8C2ZWTUsLk3 +iey/plPzeth2PX1/aSWKLhrc/mptvPwa/OQcwRn2T2w== X-Forward-Email-ID: 67ce23ae5209992d7c670e83 X-Forward-Email-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 121.127.44.59 X-Forward-Email-Version: 0.4.40 X-Forward-Email-Website: https://forwardemail.net X-Complaints-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Report-Abuse-To: abuse@forwardemail.net From: Jonas Karlman To: Heiko Stuebner , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Wu , Yao Zi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 2/5] net: stmmac: dwmac-rk: Add GMAC support for RK3528 Date: Sun, 9 Mar 2025 23:26:12 +0000 Message-ID: <20250309232622.1498084-3-jonas@kwiboo.se> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309232622.1498084-1-jonas@kwiboo.se> References: <20250309232622.1498084-1-jonas@kwiboo.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: David Wu Rockchip RK3528 has two Ethernet controllers based on Synopsys DWC Ethernet QoS IP. Add initial support for the RK3528 GMAC variant. Signed-off-by: David Wu Signed-off-by: Jonas Karlman --- Changes in v2: - None Power up/down of the integrated PHY is added in a separate patch. --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 132 ++++++++++++++++++ 1 file changed, 132 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/e= thernet/stmicro/stmmac/dwmac-rk.c index 342463587d06..03ea9368ffbb 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -828,6 +828,137 @@ static const struct rk_gmac_ops rk3399_ops =3D { .set_rmii_speed =3D rk3399_set_rmii_speed, }; =20 +#define RK3528_VO_GRF_GMAC_CON 0x0018 +#define RK3528_VO_GRF_MACPHY_CON0 0x001c +#define RK3528_VO_GRF_MACPHY_CON1 0x0020 +#define RK3528_VPU_GRF_GMAC_CON5 0x0018 +#define RK3528_VPU_GRF_GMAC_CON6 0x001c + +#define RK3528_GMAC_RXCLK_DLY_ENABLE GRF_BIT(15) +#define RK3528_GMAC_RXCLK_DLY_DISABLE GRF_CLR_BIT(15) +#define RK3528_GMAC_TXCLK_DLY_ENABLE GRF_BIT(14) +#define RK3528_GMAC_TXCLK_DLY_DISABLE GRF_CLR_BIT(14) + +#define RK3528_GMAC_CLK_RX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 8) +#define RK3528_GMAC_CLK_TX_DL_CFG(val) HIWORD_UPDATE(val, 0xFF, 0) + +#define RK3528_GMAC0_PHY_INTF_SEL_RMII GRF_BIT(1) +#define RK3528_GMAC1_PHY_INTF_SEL_RGMII GRF_CLR_BIT(8) +#define RK3528_GMAC1_PHY_INTF_SEL_RMII GRF_BIT(8) + +#define RK3528_GMAC1_CLK_SELECT_CRU GRF_CLR_BIT(12) +#define RK3528_GMAC1_CLK_SELECT_IO GRF_BIT(12) + +#define RK3528_GMAC0_CLK_RMII_DIV2 GRF_BIT(3) +#define RK3528_GMAC0_CLK_RMII_DIV20 GRF_CLR_BIT(3) +#define RK3528_GMAC1_CLK_RMII_DIV2 GRF_BIT(10) +#define RK3528_GMAC1_CLK_RMII_DIV20 GRF_CLR_BIT(10) + +#define RK3528_GMAC1_CLK_RGMII_DIV1 (GRF_CLR_BIT(11) | GRF_CLR_BIT(10)) +#define RK3528_GMAC1_CLK_RGMII_DIV5 (GRF_BIT(11) | GRF_BIT(10)) +#define RK3528_GMAC1_CLK_RGMII_DIV50 (GRF_BIT(11) | GRF_CLR_BIT(10)) + +#define RK3528_GMAC0_CLK_RMII_GATE GRF_BIT(2) +#define RK3528_GMAC0_CLK_RMII_NOGATE GRF_CLR_BIT(2) +#define RK3528_GMAC1_CLK_RMII_GATE GRF_BIT(9) +#define RK3528_GMAC1_CLK_RMII_NOGATE GRF_CLR_BIT(9) + +static void rk3528_set_to_rgmii(struct rk_priv_data *bsp_priv, + int tx_delay, int rx_delay) +{ + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_PHY_INTF_SEL_RGMII); + + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + DELAY_ENABLE(RK3528, tx_delay, rx_delay)); + + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON6, + RK3528_GMAC_CLK_RX_DL_CFG(rx_delay) | + RK3528_GMAC_CLK_TX_DL_CFG(tx_delay)); +} + +static void rk3528_set_to_rmii(struct rk_priv_data *bsp_priv) +{ + if (bsp_priv->id =3D=3D 1) + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_PHY_INTF_SEL_RMII); + else + regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, + RK3528_GMAC0_PHY_INTF_SEL_RMII | + RK3528_GMAC0_CLK_RMII_DIV2); +} + +static void rk3528_set_rgmii_speed(struct rk_priv_data *bsp_priv, int spee= d) +{ + struct device *dev =3D &bsp_priv->pdev->dev; + + if (speed =3D=3D 10) + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_CLK_RGMII_DIV50); + else if (speed =3D=3D 100) + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_CLK_RGMII_DIV5); + else if (speed =3D=3D 1000) + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, + RK3528_GMAC1_CLK_RGMII_DIV1); + else + dev_err(dev, "unknown speed value for RGMII! speed=3D%d", speed); +} + +static void rk3528_set_rmii_speed(struct rk_priv_data *bsp_priv, int speed) +{ + struct device *dev =3D &bsp_priv->pdev->dev; + unsigned int reg, val; + + if (speed =3D=3D 10) + val =3D bsp_priv->id =3D=3D 1 ? RK3528_GMAC1_CLK_RMII_DIV20 : + RK3528_GMAC0_CLK_RMII_DIV20; + else if (speed =3D=3D 100) + val =3D bsp_priv->id =3D=3D 1 ? RK3528_GMAC1_CLK_RMII_DIV2 : + RK3528_GMAC0_CLK_RMII_DIV2; + else { + dev_err(dev, "unknown speed value for RMII! speed=3D%d", speed); + return; + } + + reg =3D bsp_priv->id =3D=3D 1 ? RK3528_VPU_GRF_GMAC_CON5 : + RK3528_VO_GRF_GMAC_CON; + + regmap_write(bsp_priv->grf, reg, val); +} + +static void rk3528_set_clock_selection(struct rk_priv_data *bsp_priv, + bool input, bool enable) +{ + unsigned int val; + + if (bsp_priv->id =3D=3D 1) { + val =3D input ? RK3528_GMAC1_CLK_SELECT_IO : + RK3528_GMAC1_CLK_SELECT_CRU; + val |=3D enable ? RK3528_GMAC1_CLK_RMII_NOGATE : + RK3528_GMAC1_CLK_RMII_GATE; + regmap_write(bsp_priv->grf, RK3528_VPU_GRF_GMAC_CON5, val); + } else { + val =3D enable ? RK3528_GMAC0_CLK_RMII_NOGATE : + RK3528_GMAC0_CLK_RMII_GATE; + regmap_write(bsp_priv->grf, RK3528_VO_GRF_GMAC_CON, val); + } +} + +static const struct rk_gmac_ops rk3528_ops =3D { + .set_to_rgmii =3D rk3528_set_to_rgmii, + .set_to_rmii =3D rk3528_set_to_rmii, + .set_rgmii_speed =3D rk3528_set_rgmii_speed, + .set_rmii_speed =3D rk3528_set_rmii_speed, + .set_clock_selection =3D rk3528_set_clock_selection, + .regs_valid =3D true, + .regs =3D { + 0xffbd0000, /* gmac0 */ + 0xffbe0000, /* gmac1 */ + 0x0, /* sentinel */ + }, +}; + #define RK3568_GRF_GMAC0_CON0 0x0380 #define RK3568_GRF_GMAC0_CON1 0x0384 #define RK3568_GRF_GMAC1_CON0 0x0388 @@ -1816,6 +1947,7 @@ static const struct of_device_id rk_gmac_dwmac_match[= ] =3D { { .compatible =3D "rockchip,rk3366-gmac", .data =3D &rk3366_ops }, { .compatible =3D "rockchip,rk3368-gmac", .data =3D &rk3368_ops }, { .compatible =3D "rockchip,rk3399-gmac", .data =3D &rk3399_ops }, + { .compatible =3D "rockchip,rk3528-gmac", .data =3D &rk3528_ops }, { .compatible =3D "rockchip,rk3568-gmac", .data =3D &rk3568_ops }, { .compatible =3D "rockchip,rk3576-gmac", .data =3D &rk3576_ops }, { .compatible =3D "rockchip,rk3588-gmac", .data =3D &rk3588_ops }, --=20 2.48.1 From nobody Sun Feb 8 13:32:42 2026 Received: from smtp.forwardemail.net (smtp.forwardemail.net [121.127.44.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 46B061CAA6C for ; Sun, 9 Mar 2025 23:26:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=121.127.44.59 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741562809; cv=none; b=UJ5Nd8Xxv5vOsv7n74jaa8LNy+DtbvjxIJAgIB630mGLW6khluC/2ybuX0eX74c+TZV+Ir8RzkJh+6gwrKSgi1lGpQBaWEvmNRVMGkBgr04zfMYda36ryI5O9/mB6viYCxTDTMCcJuuRcMzeK6XWNmX4vdLVmrGeEi0HLf43h28= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741562809; c=relaxed/simple; bh=1KwXe9PoxEReMydTX2qSnybaHlsL4TT8cuxNZbn6vKE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=g0oh2jkY5UzrHTvOLKHOD91DfX+N3pmRHl62XQ9L51rD3m21UYxlN05D9GaZVDdXgHF4xYRaPjIVO1CcPXLwIbdV4k8mqsaQ3bxRJG6dlMVY7RAPJ8cZ5mL0APWFh1FRopeu7bAD64XdnZNj1SiEKfOXsXZpTH3LqT1kokLms44= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kwiboo.se; spf=pass smtp.mailfrom=fe-bounces.kwiboo.se; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b=FFbjU5gY; arc=none smtp.client-ip=121.127.44.59 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=kwiboo.se Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=fe-bounces.kwiboo.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b="FFbjU5gY" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1741562806; bh=L3Wm/7k4UnB9TXY856GOytFcdaOKPaHZ6TKBq1pbNtA=; b=FFbjU5gYETSaZjPXHkV5/mQP3a3rkAmFOjT6FsJi2mBasdF5mdnCdsd3P9r54+2kbTK5ktQ9a zdHdUAIFNYp/XtEtkg2rg878zi4yMUmwExd1Ka4srbCFam7ZcnAfM+aaUi6kwSXQdV+MeV50GXA VgEND9Euv7uq32/m8xUYU95t9bKqxPKqtM+ITYNS62Bp2d4uSRrG/81Eu2TQllqesW0bWW64sL0 3SWPjOsAWzF0xEvFn8CynPJyCbm6LfZNZDcVVy82j8bi1Bsyn5CwxwwKTe/Q8l50d0P0sJ7R6Tm CW4tpR3Mt/frt4OFw29Fc82eW/0WGM/Do1CNe5L6TERg== X-Forward-Email-ID: 67ce23b35209992d7c670e98 X-Forward-Email-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 121.127.44.59 X-Forward-Email-Version: 0.4.40 X-Forward-Email-Website: https://forwardemail.net X-Complaints-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Report-Abuse-To: abuse@forwardemail.net From: Jonas Karlman To: Heiko Stuebner , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Philipp Zabel Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Wu , Yao Zi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 3/5] net: stmmac: dwmac-rk: Move integrated_phy_powerup/down functions Date: Sun, 9 Mar 2025 23:26:13 +0000 Message-ID: <20250309232622.1498084-4-jonas@kwiboo.se> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309232622.1498084-1-jonas@kwiboo.se> References: <20250309232622.1498084-1-jonas@kwiboo.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rockchip RK3528 (and RV1106) has a different integrated PHY compared to the integrated PHY on RK3228/RK3328. Current powerup/down operation is not compatible with the integrated PHY found in these SoCs. Move the rk_gmac_integrated_phy_powerup/down functions to top of the file to prepare for them to be called directly by a GMAC variant specific powerup/down operation. Signed-off-by: Jonas Karlman --- Changes in v2: - New patch --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 88 +++++++++---------- 1 file changed, 44 insertions(+), 44 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/e= thernet/stmicro/stmmac/dwmac-rk.c index 03ea9368ffbb..31f4b7eb3718 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -92,6 +92,50 @@ struct rk_priv_data { (((tx) ? soc##_GMAC_TXCLK_DLY_ENABLE : soc##_GMAC_TXCLK_DLY_DISABLE) | \ ((rx) ? soc##_GMAC_RXCLK_DLY_ENABLE : soc##_GMAC_RXCLK_DLY_DISABLE)) =20 +#define RK_GRF_MACPHY_CON0 0xb00 +#define RK_GRF_MACPHY_CON1 0xb04 +#define RK_GRF_MACPHY_CON2 0xb08 +#define RK_GRF_MACPHY_CON3 0xb0c + +#define RK_MACPHY_ENABLE GRF_BIT(0) +#define RK_MACPHY_DISABLE GRF_CLR_BIT(0) +#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) +#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) +#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) +#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) + +static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) +{ + if (priv->ops->integrated_phy_powerup) + priv->ops->integrated_phy_powerup(priv); + + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); + + regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); + regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); + + if (priv->phy_reset) { + /* PHY needs to be disabled before trying to reset it */ + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); + if (priv->phy_reset) + reset_control_assert(priv->phy_reset); + usleep_range(10, 20); + if (priv->phy_reset) + reset_control_deassert(priv->phy_reset); + usleep_range(10, 20); + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); + msleep(30); + } +} + +static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) +{ + regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); + if (priv->phy_reset) + reset_control_assert(priv->phy_reset); +} + #define PX30_GRF_GMAC_CON1 0x0904 =20 /* PX30_GRF_GMAC_CON1 */ @@ -1463,50 +1507,6 @@ static const struct rk_gmac_ops rv1126_ops =3D { .set_rmii_speed =3D rv1126_set_rmii_speed, }; =20 -#define RK_GRF_MACPHY_CON0 0xb00 -#define RK_GRF_MACPHY_CON1 0xb04 -#define RK_GRF_MACPHY_CON2 0xb08 -#define RK_GRF_MACPHY_CON3 0xb0c - -#define RK_MACPHY_ENABLE GRF_BIT(0) -#define RK_MACPHY_DISABLE GRF_CLR_BIT(0) -#define RK_MACPHY_CFG_CLK_50M GRF_BIT(14) -#define RK_GMAC2PHY_RMII_MODE (GRF_BIT(6) | GRF_CLR_BIT(7)) -#define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) -#define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) - -static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) -{ - if (priv->ops->integrated_phy_powerup) - priv->ops->integrated_phy_powerup(priv); - - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); - - regmap_write(priv->grf, RK_GRF_MACPHY_CON2, RK_GRF_CON2_MACPHY_ID); - regmap_write(priv->grf, RK_GRF_MACPHY_CON3, RK_GRF_CON3_MACPHY_ID); - - if (priv->phy_reset) { - /* PHY needs to be disabled before trying to reset it */ - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); - if (priv->phy_reset) - reset_control_assert(priv->phy_reset); - usleep_range(10, 20); - if (priv->phy_reset) - reset_control_deassert(priv->phy_reset); - usleep_range(10, 20); - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_ENABLE); - msleep(30); - } -} - -static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) -{ - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); - if (priv->phy_reset) - reset_control_assert(priv->phy_reset); -} - static int rk_gmac_clk_init(struct plat_stmmacenet_data *plat) { struct rk_priv_data *bsp_priv =3D plat->bsp_priv; --=20 2.48.1 From nobody Sun Feb 8 13:32:42 2026 Received: from smtp.forwardemail.net (smtp.forwardemail.net [121.127.44.59]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BFE962222C3 for ; Sun, 9 Mar 2025 23:26:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=121.127.44.59 ARC-Seal: i=1; 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spf=pass smtp.mailfrom=fe-bounces.kwiboo.se Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kwiboo.se header.i=@kwiboo.se header.b="AzPHzvRg" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=kwiboo.se; h=Content-Transfer-Encoding: MIME-Version: References: In-Reply-To: Message-ID: Date: Subject: Cc: To: From; q=dns/txt; s=fe-e1b5cab7be; t=1741562810; bh=g1vzbhos5OwaddvUHip/yFVK9gBZxHa1+o/ob3Y9bs8=; b=AzPHzvRgM/T+yIWLuTrvlPljI7sCwom5F+CD646XsZW6L5xSYCX+LWmyTSaF3MlMl4+8uZmAp bCEi6Rknudhi8ibaMNe7wLN4HuhT4XLhen/S3E+HQUItzcSek62n6TCgIwTNVI5tiLfHzv6Llin uVUpFjPC6/jba/MgtCha45Ck8GijJfnMVTNyZRqamE1Y9Ptld9xNkbFs1fHLVwfej7h4l5Uuwap X2fNk/jrR3PGiIjfNHDMsONw48pV+9ZORdCXoKqEw+TY49YXlxkrLsFSgDFmSxmFRLKAdQuDFxL FOeJmpzhubpxH9fkzMHbu7rPg6V4UZuY5DEbC9f8DpWA== X-Forward-Email-ID: 67ce23b85209992d7c670ead X-Forward-Email-Sender: rfc822; jonas@kwiboo.se, smtp.forwardemail.net, 121.127.44.59 X-Forward-Email-Version: 0.4.40 X-Forward-Email-Website: https://forwardemail.net X-Complaints-To: abuse@forwardemail.net X-Report-Abuse: abuse@forwardemail.net X-Report-Abuse-To: abuse@forwardemail.net From: Jonas Karlman To: Heiko Stuebner , Andrew Lunn , "David S . Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Wu , Yao Zi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 4/5] net: stmmac: dwmac-rk: Add integrated_phy_powerdown operation Date: Sun, 9 Mar 2025 23:26:14 +0000 Message-ID: <20250309232622.1498084-5-jonas@kwiboo.se> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309232622.1498084-1-jonas@kwiboo.se> References: <20250309232622.1498084-1-jonas@kwiboo.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rockchip RK3528 (and RV1106) has a different integrated PHY compared to the integrated PHY on RK3228/RK3328. Current powerup/down operation is not compatible with the integrated PHY found in these newer SoCs. Add a new integrated_phy_powerdown operation and change the call chain for integrated_phy_powerup to prepare support for the integrated PHY found in these newer SoCs. Signed-off-by: Jonas Karlman --- Changes in v2: - New patch --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 26 +++++++++++-------- 1 file changed, 15 insertions(+), 11 deletions(-) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/e= thernet/stmicro/stmmac/dwmac-rk.c index 31f4b7eb3718..3f096b3ccee8 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -33,6 +33,7 @@ struct rk_gmac_ops { void (*set_clock_selection)(struct rk_priv_data *bsp_priv, bool input, bool enable); void (*integrated_phy_powerup)(struct rk_priv_data *bsp_priv); + void (*integrated_phy_powerdown)(struct rk_priv_data *bsp_priv); bool php_grf_required; bool regs_valid; u32 regs[]; @@ -104,11 +105,8 @@ struct rk_priv_data { #define RK_GRF_CON2_MACPHY_ID HIWORD_UPDATE(0x1234, 0xffff, 0) #define RK_GRF_CON3_MACPHY_ID HIWORD_UPDATE(0x35, 0x3f, 0) =20 -static void rk_gmac_integrated_phy_powerup(struct rk_priv_data *priv) +static void rk_gmac_integrated_ephy_powerup(struct rk_priv_data *priv) { - if (priv->ops->integrated_phy_powerup) - priv->ops->integrated_phy_powerup(priv); - regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_CFG_CLK_50M); regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_GMAC2PHY_RMII_MODE); =20 @@ -129,7 +127,7 @@ static void rk_gmac_integrated_phy_powerup(struct rk_pr= iv_data *priv) } } =20 -static void rk_gmac_integrated_phy_powerdown(struct rk_priv_data *priv) +static void rk_gmac_integrated_ephy_powerdown(struct rk_priv_data *priv) { regmap_write(priv->grf, RK_GRF_MACPHY_CON0, RK_MACPHY_DISABLE); if (priv->phy_reset) @@ -368,6 +366,8 @@ static void rk3228_integrated_phy_powerup(struct rk_pri= v_data *priv) { regmap_write(priv->grf, RK3228_GRF_CON_MUX, RK3228_GRF_CON_MUX_GMAC_INTEGRATED_PHY); + + rk_gmac_integrated_ephy_powerup(priv); } =20 static const struct rk_gmac_ops rk3228_ops =3D { @@ -375,7 +375,8 @@ static const struct rk_gmac_ops rk3228_ops =3D { .set_to_rmii =3D rk3228_set_to_rmii, .set_rgmii_speed =3D rk3228_set_rgmii_speed, .set_rmii_speed =3D rk3228_set_rmii_speed, - .integrated_phy_powerup =3D rk3228_integrated_phy_powerup, + .integrated_phy_powerup =3D rk3228_integrated_phy_powerup, + .integrated_phy_powerdown =3D rk_gmac_integrated_ephy_powerdown, }; =20 #define RK3288_GRF_SOC_CON1 0x0248 @@ -601,6 +602,8 @@ static void rk3328_integrated_phy_powerup(struct rk_pri= v_data *priv) { regmap_write(priv->grf, RK3328_GRF_MACPHY_CON1, RK3328_MACPHY_RMII_MODE); + + rk_gmac_integrated_ephy_powerup(priv); } =20 static const struct rk_gmac_ops rk3328_ops =3D { @@ -608,7 +611,8 @@ static const struct rk_gmac_ops rk3328_ops =3D { .set_to_rmii =3D rk3328_set_to_rmii, .set_rgmii_speed =3D rk3328_set_rgmii_speed, .set_rmii_speed =3D rk3328_set_rmii_speed, - .integrated_phy_powerup =3D rk3328_integrated_phy_powerup, + .integrated_phy_powerup =3D rk3328_integrated_phy_powerup, + .integrated_phy_powerdown =3D rk_gmac_integrated_ephy_powerdown, }; =20 #define RK3366_GRF_SOC_CON6 0x0418 @@ -1802,16 +1806,16 @@ static int rk_gmac_powerup(struct rk_priv_data *bsp= _priv) =20 pm_runtime_get_sync(dev); =20 - if (bsp_priv->integrated_phy) - rk_gmac_integrated_phy_powerup(bsp_priv); + if (bsp_priv->integrated_phy && bsp_priv->ops->integrated_phy_powerup) + bsp_priv->ops->integrated_phy_powerup(bsp_priv); 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Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Maxime Coquelin , Alexandre Torgue , Philipp Zabel Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , David Wu , Yao Zi , netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Jonas Karlman , linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v2 5/5] net: stmmac: dwmac-rk: Add initial support for RK3528 integrated PHY Date: Sun, 9 Mar 2025 23:26:15 +0000 Message-ID: <20250309232622.1498084-6-jonas@kwiboo.se> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309232622.1498084-1-jonas@kwiboo.se> References: <20250309232622.1498084-1-jonas@kwiboo.se> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Rockchip RK3528 (and RV1106) has a different integrated PHY compared to the integrated PHY on RK3228/RK3328. Current powerup/down operation is not compatible with the integrated PHY found in these newer SoCs. Add operations to powerup/down the integrated PHY found in RK3528. Use helpers that can be used by other GMAC variants in the future. Signed-off-by: Jonas Karlman --- Changes in v2: - New patch This is enough to power up the integrated PHY on RK3528 for MDIO/MII. However, a PHY driver is still missing and I do not have any RK3528 board that make use of this MAC and PHY, so something that can be improved upon in the future. --- .../net/ethernet/stmicro/stmmac/dwmac-rk.c | 41 +++++++++++++++++++ 1 file changed, 41 insertions(+) diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c b/drivers/net/e= thernet/stmicro/stmmac/dwmac-rk.c index 3f096b3ccee8..ab2c872d33e0 100644 --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-rk.c @@ -134,6 +134,35 @@ static void rk_gmac_integrated_ephy_powerdown(struct r= k_priv_data *priv) reset_control_assert(priv->phy_reset); } =20 +#define RK_FEPHY_SHUTDOWN GRF_BIT(1) +#define RK_FEPHY_POWERUP GRF_CLR_BIT(1) +#define RK_FEPHY_INTERNAL_RMII_SEL GRF_BIT(6) +#define RK_FEPHY_24M_CLK_SEL (GRF_BIT(8) | GRF_BIT(9)) +#define RK_FEPHY_PHY_ID GRF_BIT(11) + +static void rk_gmac_integrated_fephy_powerup(struct rk_priv_data *priv, + unsigned int reg) +{ + reset_control_assert(priv->phy_reset); + usleep_range(20, 30); + + regmap_write(priv->grf, reg, + RK_FEPHY_POWERUP | + RK_FEPHY_INTERNAL_RMII_SEL | + RK_FEPHY_24M_CLK_SEL | + RK_FEPHY_PHY_ID); + usleep_range(10000, 12000); + + reset_control_deassert(priv->phy_reset); + usleep_range(50000, 60000); +} + +static void rk_gmac_integrated_fephy_powerdown(struct rk_priv_data *priv, + unsigned int reg) +{ + regmap_write(priv->grf, reg, RK_FEPHY_SHUTDOWN); +} + #define PX30_GRF_GMAC_CON1 0x0904 =20 /* PX30_GRF_GMAC_CON1 */ @@ -993,12 +1022,24 @@ static void rk3528_set_clock_selection(struct rk_pri= v_data *bsp_priv, } } =20 +static void rk3528_integrated_phy_powerup(struct rk_priv_data *bsp_priv) +{ + rk_gmac_integrated_fephy_powerup(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); +} + +static void rk3528_integrated_phy_powerdown(struct rk_priv_data *bsp_priv) +{ + rk_gmac_integrated_fephy_powerdown(bsp_priv, RK3528_VO_GRF_MACPHY_CON0); +} + static const struct rk_gmac_ops rk3528_ops =3D { .set_to_rgmii =3D rk3528_set_to_rgmii, .set_to_rmii =3D rk3528_set_to_rmii, .set_rgmii_speed =3D rk3528_set_rgmii_speed, .set_rmii_speed =3D rk3528_set_rmii_speed, .set_clock_selection =3D rk3528_set_clock_selection, + .integrated_phy_powerup =3D rk3528_integrated_phy_powerup, + .integrated_phy_powerdown =3D rk3528_integrated_phy_powerdown, .regs_valid =3D true, .regs =3D { 0xffbd0000, /* gmac0 */ --=20 2.48.1