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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id a640c23a62f3a-ac27c7e29bbsm281833966b.92.2025.03.09.13.26.47 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 09 Mar 2025 13:26:47 -0700 (PDT) From: Alexander Sverdlin To: sophgo@lists.linux.dev, devicetree@vger.kernel.org, linux-rtc@vger.kernel.org Cc: Jingbao Qiu , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Alexandre Belloni , Arnd Bergmann , Yangyu Chen , linux-kernel@vger.kernel.org, Alexander Sverdlin Subject: [PATCH v13 3/3] rtc: sophgo: add rtc support for Sophgo CV1800 SoC Date: Sun, 9 Mar 2025 21:26:25 +0100 Message-ID: <20250309202629.3516822-4-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250309202629.3516822-1-alexander.sverdlin@gmail.com> References: <20250309202629.3516822-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jingbao Qiu Implement the RTC driver for CV1800, which able to provide time alarm. Signed-off-by: Jingbao Qiu Signed-off-by: Alexander Sverdlin --- Changelog: v13: - Change in the Kconfig dependency caused by the move of the previous patch from MFD into SOC v12: - added MAINTAINERS entry - depends on cv1800-rtcsys MFD driver - use syscon for regmap - get named clock from parent MFD - corresponding platform device is expected to be instantiated by MFD stub Changes since v10: - only start RTC on set_time; Changes since v9: - further simplified bitmask macros; - unconditional RTC start (rtc_enable_sec_counter()), otherwise didn't start on SG2000; - dropped ANA_CALIB modification (has been forgotten in v8 with the drop of SW calibration to switch to HW calibration); - successfully tested on SG2000; MAINTAINERS | 1 + drivers/rtc/Kconfig | 12 +++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-cv1800.c | 218 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 232 insertions(+) create mode 100644 drivers/rtc/rtc-cv1800.c diff --git a/MAINTAINERS b/MAINTAINERS index ac15e448fffb..be8fee50a49c 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22354,6 +22354,7 @@ L: sophgo@lists.linux.dev W: https://github.com/sophgo/linux/wiki T: git https://github.com/sophgo/linux.git S: Maintained +F: drivers/rtc/rtc-cv1800.c F: drivers/soc/sophgo/cv1800-rtcsys.c N: sophgo K: sophgo diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 0bbbf778ecfa..46593103db11 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1395,6 +1395,18 @@ config RTC_DRV_ASM9260 This driver can also be built as a module. If so, the module will be called rtc-asm9260. =20 +config RTC_DRV_CV1800 + tristate "Sophgo CV1800 RTC" + depends on SOPHGO_CV1800_RTCSYS || COMPILE_TEST + select MFD_SYSCON + select REGMAP + help + If you say yes here you get support the RTC driver for Sophgo CV1800 + series SoC. + + This driver can also be built as a module. If so, the module will be + called rtc-cv1800. + config RTC_DRV_DIGICOLOR tristate "Conexant Digicolor RTC" depends on ARCH_DIGICOLOR || COMPILE_TEST diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 489b4ab07068..621b30a33dda 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_RTC_DRV_CADENCE) +=3D rtc-cadence.o obj-$(CONFIG_RTC_DRV_CMOS) +=3D rtc-cmos.o obj-$(CONFIG_RTC_DRV_CPCAP) +=3D rtc-cpcap.o obj-$(CONFIG_RTC_DRV_CROS_EC) +=3D rtc-cros-ec.o +obj-$(CONFIG_RTC_DRV_CV1800) +=3D rtc-cv1800.o obj-$(CONFIG_RTC_DRV_DA9052) +=3D rtc-da9052.o obj-$(CONFIG_RTC_DRV_DA9055) +=3D rtc-da9055.o obj-$(CONFIG_RTC_DRV_DA9063) +=3D rtc-da9063.o diff --git a/drivers/rtc/rtc-cv1800.c b/drivers/rtc/rtc-cv1800.c new file mode 100644 index 000000000000..18bc542bbdb8 --- /dev/null +++ b/drivers/rtc/rtc-cv1800.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * rtc-cv1800.c: RTC driver for Sophgo cv1800 RTC + * + * Author: Jingbao Qiu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SEC_PULSE_GEN 0x1004 +#define ALARM_TIME 0x1008 +#define ALARM_ENABLE 0x100C +#define SET_SEC_CNTR_VAL 0x1010 +#define SET_SEC_CNTR_TRIG 0x1014 +#define SEC_CNTR_VAL 0x1018 + +/* + * When in VDDBKUP domain, this MACRO register + * does not power down + */ +#define MACRO_RO_T 0x14A8 +#define MACRO_RG_SET_T 0x1498 + +#define ALARM_ENABLE_MASK BIT(0) +#define SEL_SEC_PULSE BIT(31) + +struct cv1800_rtc_priv { + struct rtc_device *rtc_dev; + struct regmap *rtc_map; + struct clk *clk; + int irq; +}; + +static bool cv1800_rtc_enabled(struct device *dev) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + u32 reg; + + regmap_read(info->rtc_map, SEC_PULSE_GEN, ®); + + return (reg & SEL_SEC_PULSE) =3D=3D 0; +} + +static void cv1800_rtc_enable(struct device *dev) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + + /* Sec pulse generated internally */ + regmap_update_bits(info->rtc_map, SEC_PULSE_GEN, SEL_SEC_PULSE, 0); +} + +static int cv1800_rtc_alarm_irq_enable(struct device *dev, unsigned int en= abled) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + + regmap_write(info->rtc_map, ALARM_ENABLE, enabled); + + return 0; +} + +static int cv1800_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alr= m) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + unsigned long alarm_time; + + alarm_time =3D rtc_tm_to_time64(&alrm->time); + + cv1800_rtc_alarm_irq_enable(dev, 0); + + regmap_write(info->rtc_map, ALARM_TIME, alarm_time); + + cv1800_rtc_alarm_irq_enable(dev, alrm->enabled); + + return 0; +} + +static int cv1800_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *al= arm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + u32 enabled; + u32 time; + + if (!cv1800_rtc_enabled(dev)) { + alarm->enabled =3D 0; + return 0; + } + + regmap_read(info->rtc_map, ALARM_ENABLE, &enabled); + + alarm->enabled =3D enabled & ALARM_ENABLE_MASK; + + regmap_read(info->rtc_map, ALARM_TIME, &time); + + rtc_time64_to_tm(time, &alarm->time); + + return 0; +} + +static int cv1800_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + u32 sec; + + if (!cv1800_rtc_enabled(dev)) + return -EINVAL; + + regmap_read(info->rtc_map, SEC_CNTR_VAL, &sec); + + rtc_time64_to_tm(sec, tm); + + return 0; +} + +static int cv1800_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + unsigned long sec; + + sec =3D rtc_tm_to_time64(tm); + + regmap_write(info->rtc_map, SET_SEC_CNTR_VAL, sec); + regmap_write(info->rtc_map, SET_SEC_CNTR_TRIG, 1); + + regmap_write(info->rtc_map, MACRO_RG_SET_T, sec); + + cv1800_rtc_enable(dev); + + return 0; +} + +static irqreturn_t cv1800_rtc_irq_handler(int irq, void *dev_id) +{ + struct cv1800_rtc_priv *info =3D dev_id; + + rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); + + regmap_write(info->rtc_map, ALARM_ENABLE, 0); + + return IRQ_HANDLED; +} + +static const struct rtc_class_ops cv1800_rtc_ops =3D { + .read_time =3D cv1800_rtc_read_time, + .set_time =3D cv1800_rtc_set_time, + .read_alarm =3D cv1800_rtc_read_alarm, + .set_alarm =3D cv1800_rtc_set_alarm, + .alarm_irq_enable =3D cv1800_rtc_alarm_irq_enable, +}; + +static int cv1800_rtc_probe(struct platform_device *pdev) +{ + struct cv1800_rtc_priv *rtc; + int ret; + + rtc =3D devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + rtc->rtc_map =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rtc->rtc_map)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtc_map), + "cannot get parent regmap\n"); + + rtc->irq =3D platform_get_irq(pdev, 0); + if (rtc->irq < 0) + return rtc->irq; + + rtc->clk =3D devm_clk_get_enabled(pdev->dev.parent, "rtc"); + if (IS_ERR(rtc->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->clk), + "rtc clk not found\n"); + + platform_set_drvdata(pdev, rtc); + + device_init_wakeup(&pdev->dev, 1); + + rtc->rtc_dev =3D devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtc->rtc_dev)) + return PTR_ERR(rtc->rtc_dev); + + rtc->rtc_dev->ops =3D &cv1800_rtc_ops; + rtc->rtc_dev->range_max =3D U32_MAX; + + ret =3D devm_request_irq(&pdev->dev, rtc->irq, cv1800_rtc_irq_handler, + IRQF_TRIGGER_HIGH, "rtc alarm", rtc); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "cannot register interrupt handler\n"); + + return devm_rtc_register_device(rtc->rtc_dev); +} + +static const struct platform_device_id cv1800_rtc_id[] =3D { + { .name =3D "cv1800-rtc" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, cv1800_rtc_id); + +static struct platform_driver cv1800_rtc_driver =3D { + .driver =3D { + .name =3D "sophgo-cv1800-rtc", + }, + .probe =3D cv1800_rtc_probe, + .id_table =3D cv1800_rtc_id, +}; + +module_platform_driver(cv1800_rtc_driver); +MODULE_AUTHOR("Jingbao Qiu"); +MODULE_DESCRIPTION("Sophgo cv1800 RTC Driver"); +MODULE_LICENSE("GPL"); --=20 2.48.1