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To enable this feature increase configuration space size to 256MB. If the config space is increased, the BAR space needs to be truncated as it resides in the same location. To avoid the bar space truncation move config space, DBI, ELBI, iATU to upper PCIe region and use lower PCIe iregion entirely for BAR region. This depends on the commit: '10ba0854c5e6 ("PCI: qcom: Disable mirroring of DBI and iATU register space in BAR region")' Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Manivannan Sadhasivam Reviewed-by: Konrad Dybcio --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 0f2caf36910b..64c46221d8bf 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2201,10 +2201,10 @@ wifi: wifi@17a10040 { pcie1: pcie@1c08000 { compatible =3D "qcom,pcie-sc7280"; reg =3D <0 0x01c08000 0 0x3000>, - <0 0x40000000 0 0xf1d>, - <0 0x40000f20 0 0xa8>, - <0 0x40001000 0 0x1000>, - <0 0x40100000 0 0x100000>; + <4 0x00000000 0 0xf1d>, + <4 0x00000f20 0 0xa8>, + <4 0x10000000 0 0x1000>, + <4 0x00000000 0 0x10000000>; =20 reg-names =3D "parf", "dbi", "elbi", "atu", "config"; device_type =3D "pci"; @@ -2215,8 +2215,8 @@ pcie1: pcie@1c08000 { #address-cells =3D <3>; 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Having this register as required is not allowing to enable ECAM feature of the PCIe cleanly. ECAM feature needs to do single remap of entire 256MB which includes DBI and ELBI. Having optional ELBI registers in the devicetree and binding is causing resorce conflicts when enabling ECAM feature. So, make ELBI registers as optional one. Suggested-by: Manivannan Sadhasivam Signed-off-by: Krishna Chaitanya Chundru --- Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml b/= Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml index 76cb9fbfd476..326059a59b61 100644 --- a/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml +++ b/Documentation/devicetree/bindings/pci/qcom,pcie-sc7280.yaml @@ -19,17 +19,17 @@ properties: const: qcom,pcie-sc7280 =20 reg: - minItems: 5 + minItems: 4 maxItems: 6 =20 reg-names: - minItems: 5 + minItems: 4 items: - const: parf # Qualcomm specific registers - const: dbi # DesignWare PCIe registers - - const: elbi # External local bus interface registers - const: atu # ATU address space - const: config # PCIe configuration space + - const: elbi # External local bus interface registers - const: mhi # MHI registers =20 clocks: @@ -94,10 +94,9 @@ examples: compatible =3D "qcom,pcie-sc7280"; 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So removing the elbi registers from PCIe node. Signed-off-by: Krishna Chaitanya Chundru --- arch/arm64/boot/dts/qcom/sc7280.dtsi | 3 +-- 1 file changed, 1 insertion(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qco= m/sc7280.dtsi index 64c46221d8bf..e556285d6b75 100644 --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi @@ -2202,11 +2202,10 @@ pcie1: pcie@1c08000 { compatible =3D "qcom,pcie-sc7280"; reg =3D <0 0x01c08000 0 0x3000>, <4 0x00000000 0 0xf1d>, - <4 0x00000f20 0 0xa8>, <4 0x10000000 0 0x1000>, <4 0x00000000 0 0x10000000>; =20 - reg-names =3D "parf", "dbi", "elbi", "atu", "config"; + reg-names =3D "parf", "dbi", "atu", "config"; device_type =3D "pci"; linux,pci-domain =3D <1>; bus-range =3D <0x00 0xff>; --=20 2.34.1 From nobody Sun Feb 8 16:33:37 2026 Received: from mx0a-0031df01.pphosted.com (mx0a-0031df01.pphosted.com [205.220.168.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4868218872D for ; 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As these are part of dwc add the mapping support in dwc itself. Suggested-by: Manivannan Sadhasivam Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-designware.c | 9 +++++++++ drivers/pci/controller/dwc/pcie-designware.h | 1 + 2 files changed, 10 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 145e7f579072..874fd31a6079 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -157,6 +157,15 @@ int dw_pcie_get_resources(struct dw_pcie *pci) } } =20 + if (!pci->elbi_base) { + res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "elbi"); + if (res) { + pci->elbi_base =3D devm_ioremap_resource(pci->dev, res); + if (IS_ERR(pci->elbi_base)) + return PTR_ERR(pci->elbi_base); + } + } + /* LLDD is supposed to manually switch the clocks and resets state */ if (dw_pcie_cap_is(pci, REQ_RES)) { ret =3D dw_pcie_get_clocks(pci); diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 501d9ddfea16..3248318d3edd 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -443,6 +443,7 @@ struct dw_pcie { resource_size_t dbi_phys_addr; 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Signed-off-by: Krishna Chaitanya Chundru Reviewed-by: Manivannan Sadhasivam --- drivers/pci/controller/dwc/pcie-qcom.c | 12 +++--------- 1 file changed, 3 insertions(+), 9 deletions(-) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index e4d3366ead1f..258b2d615080 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -265,7 +265,6 @@ struct qcom_pcie_cfg { struct qcom_pcie { struct dw_pcie *pci; void __iomem *parf; /* DT parf */ - void __iomem *elbi; /* DT elbi */ void __iomem *mhi; union qcom_pcie_resources res; struct phy *phy; @@ -390,12 +389,13 @@ static void qcom_pcie_configure_dbi_atu_base(struct q= com_pcie *pcie) =20 static void qcom_pcie_2_1_0_ltssm_enable(struct qcom_pcie *pcie) { + struct dw_pcie *pci =3D pcie->pci; u32 val; =20 /* enable link training */ - val =3D readl(pcie->elbi + ELBI_SYS_CTRL); + val =3D readl(pci->elbi_base + ELBI_SYS_CTRL); val |=3D ELBI_SYS_CTRL_LT_ENABLE; - writel(val, pcie->elbi + ELBI_SYS_CTRL); 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Designware databook 5.20a, section 3.10.10.3 says about CFG Shift Feature, which shifts/maps the BDF (bits [31:16] of the third header DWORD, which would be matched against the Base and Limit addresses) of the incoming CfgRd0/CfgWr0 down to bits[27:12]of the translated address. Configuring iATU in config shift feature enables ECAM feature to access the config space, which avoids iATU configuration for every config access. Add "ctrl2" into struct dw_pcie_ob_atu_cfg to enable config shift feature. As DBI comes under config space, this avoids remapping of DBI space separately. Instead, it uses the mapped config space address returned from ECAM initialization. Change the order of dw_pcie_get_resources() execution to achieve this. Enable the ECAM feature if the config space size is equal to size required to represent number of buses in the bus range property. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/Kconfig | 1 + drivers/pci/controller/dwc/pcie-designware-host.c | 134 ++++++++++++++++++= +--- drivers/pci/controller/dwc/pcie-designware.c | 2 +- drivers/pci/controller/dwc/pcie-designware.h | 5 + 4 files changed, 124 insertions(+), 18 deletions(-) diff --git a/drivers/pci/controller/dwc/Kconfig b/drivers/pci/controller/dw= c/Kconfig index b6d6778b0698..73c3aed6b60a 100644 --- a/drivers/pci/controller/dwc/Kconfig +++ b/drivers/pci/controller/dwc/Kconfig @@ -9,6 +9,7 @@ config PCIE_DW config PCIE_DW_HOST bool select PCIE_DW + select PCI_HOST_COMMON =20 config PCIE_DW_EP bool diff --git a/drivers/pci/controller/dwc/pcie-designware-host.c b/drivers/pc= i/controller/dwc/pcie-designware-host.c index ffaded8f2df7..4433ae3a0dfa 100644 --- a/drivers/pci/controller/dwc/pcie-designware-host.c +++ b/drivers/pci/controller/dwc/pcie-designware-host.c @@ -418,6 +418,81 @@ static void dw_pcie_host_request_msg_tlp_res(struct dw= _pcie_rp *pp) } } =20 +static int dw_pcie_config_ecam_iatu(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct dw_pcie_ob_atu_cfg atu =3D {0}; + resource_size_t bus_range_max; + struct resource_entry *bus; + int ret; + + bus =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + + /* + * Root bus under the host bridge doesn't require any iATU configuration + * as DBI region will be used to access root bus config space. + * Immediate bus under Root Bus, needs type 0 iATU configuration and + * remaining buses need type 1 iATU configuration. + */ + atu.index =3D 0; + atu.type =3D PCIE_ATU_TYPE_CFG0; + atu.cpu_addr =3D pp->cfg0_base + SZ_1M; + /* 1MiB is to cover 1 (bus) * 32 (devices) * 8 (functions) */ + atu.size =3D SZ_1M; + atu.ctrl2 =3D PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + ret =3D dw_pcie_prog_outbound_atu(pci, &atu); + if (ret) + return ret; + + bus_range_max =3D resource_size(bus->res); + + if (bus_range_max < 2) + return 0; + + /* Configure remaining buses in type 1 iATU configuration */ + atu.index =3D 1; + atu.type =3D PCIE_ATU_TYPE_CFG1; + atu.cpu_addr =3D pp->cfg0_base + SZ_2M; + atu.size =3D (SZ_1M * bus_range_max) - SZ_2M; + atu.ctrl2 =3D PCIE_ATU_CFG_SHIFT_MODE_ENABLE; + + return dw_pcie_prog_outbound_atu(pci, &atu); +} + +static int dw_pcie_create_ecam_window(struct dw_pcie_rp *pp, struct resour= ce *res) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct device *dev =3D pci->dev; + struct resource_entry *bus; + + bus =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_BUS); + if (!bus) + return -ENODEV; + + pp->cfg =3D pci_ecam_create(dev, res, bus->res, &pci_generic_ecam_ops); + if (IS_ERR(pp->cfg)) + return PTR_ERR(pp->cfg); + + pci->dbi_base =3D pp->cfg->win; + pci->dbi_phys_addr =3D res->start; + + return 0; +} + +static bool dw_pcie_ecam_supported(struct dw_pcie_rp *pp, struct resource = *config_res) +{ + struct resource *bus_range; + u64 nr_buses; + + bus_range =3D resource_list_first_type(&pp->bridge->windows, IORESOURCE_B= US)->res; + if (!bus_range) + return false; + + nr_buses =3D resource_size(config_res) >> PCIE_ECAM_BUS_SHIFT; + + return !!(nr_buses >=3D resource_size(bus_range)); +} + int dw_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); @@ -431,9 +506,11 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 raw_spin_lock_init(&pp->lock); =20 - ret =3D dw_pcie_get_resources(pci); - if (ret) - return ret; + bridge =3D devm_pci_alloc_host_bridge(dev, 0); + if (!bridge) + return -ENOMEM; + + pp->bridge =3D bridge; =20 res =3D platform_get_resource_byname(pdev, IORESOURCE_MEM, "config"); if (!res) { @@ -444,15 +521,29 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->cfg0_size =3D resource_size(res); pp->cfg0_base =3D res->start; =20 - pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); - if (IS_ERR(pp->va_cfg0_base)) - return PTR_ERR(pp->va_cfg0_base); + pp->ecam_mode =3D dw_pcie_ecam_supported(pp, res); + if (pp->ecam_mode) { + ret =3D dw_pcie_create_ecam_window(pp, res); + if (ret) + return ret; =20 - bridge =3D devm_pci_alloc_host_bridge(dev, 0); - if (!bridge) - return -ENOMEM; + bridge->ops =3D (struct pci_ops *)&pci_generic_ecam_ops.pci_ops; + pp->bridge->sysdata =3D pp->cfg; + pp->cfg->priv =3D pp; + } else { + pp->va_cfg0_base =3D devm_pci_remap_cfg_resource(dev, res); + if (IS_ERR(pp->va_cfg0_base)) + return PTR_ERR(pp->va_cfg0_base); + + /* Set default bus ops */ + bridge->ops =3D &dw_pcie_ops; + bridge->child_ops =3D &dw_child_pcie_ops; + bridge->sysdata =3D pp; + } =20 - pp->bridge =3D bridge; + ret =3D dw_pcie_get_resources(pci); + if (ret) + return ret; =20 /* Get the I/O range from DT */ win =3D resource_list_first_type(&bridge->windows, IORESOURCE_IO); @@ -462,14 +553,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) pp->io_base =3D pci_pio_to_address(win->res->start); } =20 - /* Set default bus ops */ - bridge->ops =3D &dw_pcie_ops; - bridge->child_ops =3D &dw_child_pcie_ops; - if (pp->ops->init) { ret =3D pp->ops->init(pp); if (ret) - return ret; + goto err_free_ecam; } =20 if (pci_msi_enabled()) { @@ -504,6 +591,14 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) =20 dw_pcie_iatu_detect(pci); =20 + if (pp->ecam_mode) { + ret =3D dw_pcie_config_ecam_iatu(pp); + if (ret) { + dev_err(dev, "Failed to configure iATU in ECAM mode\n"); + goto err_free_msi; + } + } + /* * Allocate the resource for MSG TLP before programming the iATU * outbound window in dw_pcie_setup_rc(). Since the allocation depends @@ -539,8 +634,6 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) /* Ignore errors, the link may come up later */ dw_pcie_wait_for_link(pci); =20 - bridge->sysdata =3D pp; - ret =3D pci_host_probe(bridge); if (ret) goto err_stop_link; @@ -564,6 +657,10 @@ int dw_pcie_host_init(struct dw_pcie_rp *pp) if (pp->ops->deinit) pp->ops->deinit(pp); =20 +err_free_ecam: + if (pp->cfg) + pci_ecam_free(pp->cfg); + return ret; } EXPORT_SYMBOL_GPL(dw_pcie_host_init); @@ -584,6 +681,9 @@ void dw_pcie_host_deinit(struct dw_pcie_rp *pp) =20 if (pp->ops->deinit) pp->ops->deinit(pp); + + if (pp->cfg) + pci_ecam_free(pp->cfg); } EXPORT_SYMBOL_GPL(dw_pcie_host_deinit); =20 diff --git a/drivers/pci/controller/dwc/pcie-designware.c b/drivers/pci/con= troller/dwc/pcie-designware.c index 874fd31a6079..3dd9406edce4 100644 --- a/drivers/pci/controller/dwc/pcie-designware.c +++ b/drivers/pci/controller/dwc/pcie-designware.c @@ -518,7 +518,7 @@ int dw_pcie_prog_outbound_atu(struct dw_pcie *pci, val =3D dw_pcie_enable_ecrc(val); dw_pcie_writel_atu_ob(pci, atu->index, PCIE_ATU_REGION_CTRL1, val); =20 - val =3D PCIE_ATU_ENABLE; + val =3D PCIE_ATU_ENABLE | atu->ctrl2; if (atu->type =3D=3D PCIE_ATU_TYPE_MSG) { /* The data-less messages only for now */ val |=3D PCIE_ATU_INHIBIT_PAYLOAD | atu->code; diff --git a/drivers/pci/controller/dwc/pcie-designware.h b/drivers/pci/con= troller/dwc/pcie-designware.h index 3248318d3edd..6c95c36e3b0b 100644 --- a/drivers/pci/controller/dwc/pcie-designware.h +++ b/drivers/pci/controller/dwc/pcie-designware.h @@ -20,6 +20,7 @@ #include #include #include +#include #include =20 #include @@ -171,6 +172,7 @@ #define PCIE_ATU_REGION_CTRL2 0x004 #define PCIE_ATU_ENABLE BIT(31) #define PCIE_ATU_BAR_MODE_ENABLE BIT(30) +#define PCIE_ATU_CFG_SHIFT_MODE_ENABLE BIT(28) #define PCIE_ATU_INHIBIT_PAYLOAD BIT(22) #define PCIE_ATU_FUNC_NUM_MATCH_EN BIT(19) #define PCIE_ATU_LOWER_BASE 0x008 @@ -343,6 +345,7 @@ struct dw_pcie_ob_atu_cfg { u8 func_no; u8 code; u8 routing; + u32 ctrl2; u64 cpu_addr; u64 pci_addr; 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a=ed25519-sha256; t=1741499159; l=5409; i=krishna.chundru@oss.qualcomm.com; s=20230907; h=from:subject:message-id; bh=sEcZFHTUzdOTAZzu2vqRCbTaZ+x+54x0/4maTU/qWnM=; b=Hf6ymgF00bE2KFsDVcS36WMgOqoJSOXu97ObSuEfqieJtzHX2tNxi+qIlGhK2zOamXPPDnWfs aLfNgw0nCItC8hCza4NPVivk2X0//WHCGuWnjv31ObgWsMPeMbTwtjZ X-Developer-Key: i=krishna.chundru@oss.qualcomm.com; a=ed25519; pk=10CL2pdAKFyzyOHbfSWHCD0X0my7CXxj8gJScmn1FAg= X-Proofpoint-ORIG-GUID: fGxVXXjLQkFms0LJi-5A3siQdeDp0C4l X-Authority-Analysis: v=2.4 cv=f/qyBPyM c=1 sm=1 tr=0 ts=67cd2b47 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ZePRamnt/+rB5gQjfz0u9A==:17 a=IkcTkHD0fZMA:10 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=oQbQ34n3Jerzy_GFPTkA:9 a=QEXdDO2ut3YA:10 a=324X-CrmTo6CU4MGRt3R:22 X-Proofpoint-GUID: fGxVXXjLQkFms0LJi-5A3siQdeDp0C4l X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-09_02,2025-03-07_03,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 spamscore=0 bulkscore=0 phishscore=0 lowpriorityscore=0 mlxlogscore=999 clxscore=1015 priorityscore=1501 malwarescore=0 adultscore=0 suspectscore=0 mlxscore=0 classifier=spam authscore=0 authtc=n/a authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503090043 The ELBI registers falls after the DBI space, PARF_SLV_DBI_ELBI register gives us the offset from which ELBI starts. so use this offset and cfg win to map these regions. On root bus, we have only the root port. Any access other than that should not go out of the link and should return all F's. Since the iATU is configured for the buses which starts after root bus, block the transactions starting from function 1 of the root bus to the end of the root bus (i.e from dbi_base + 4kb to dbi_base + 1MB) from going outside the link through ECAM blocker through PARF registers. Signed-off-by: Krishna Chaitanya Chundru --- drivers/pci/controller/dwc/pcie-qcom.c | 64 ++++++++++++++++++++++++++++++= ++++ 1 file changed, 64 insertions(+) diff --git a/drivers/pci/controller/dwc/pcie-qcom.c b/drivers/pci/controlle= r/dwc/pcie-qcom.c index 258b2d615080..c34c0edd225f 100644 --- a/drivers/pci/controller/dwc/pcie-qcom.c +++ b/drivers/pci/controller/dwc/pcie-qcom.c @@ -52,6 +52,7 @@ #define PARF_AXI_MSTR_WR_ADDR_HALT_V2 0x1a8 #define PARF_Q2A_FLUSH 0x1ac #define PARF_LTSSM 0x1b0 +#define PARF_SLV_DBI_ELBI 0x1b4 #define PARF_INT_ALL_STATUS 0x224 #define PARF_INT_ALL_CLEAR 0x228 #define PARF_INT_ALL_MASK 0x22c @@ -61,6 +62,17 @@ #define PARF_DBI_BASE_ADDR_V2_HI 0x354 #define PARF_SLV_ADDR_SPACE_SIZE_V2 0x358 #define PARF_SLV_ADDR_SPACE_SIZE_V2_HI 0x35c +#define PARF_BLOCK_SLV_AXI_WR_BASE 0x360 +#define PARF_BLOCK_SLV_AXI_WR_BASE_HI 0x364 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT 0x368 +#define PARF_BLOCK_SLV_AXI_WR_LIMIT_HI 0x36c +#define PARF_BLOCK_SLV_AXI_RD_BASE 0x370 +#define PARF_BLOCK_SLV_AXI_RD_BASE_HI 0x374 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT 0x378 +#define PARF_BLOCK_SLV_AXI_RD_LIMIT_HI 0x37c +#define PARF_ECAM_BASE 0x380 +#define PARF_ECAM_BASE_HI 0x384 + #define PARF_NO_SNOOP_OVERIDE 0x3d4 #define PARF_ATU_BASE_ADDR 0x634 #define PARF_ATU_BASE_ADDR_HI 0x638 @@ -84,6 +96,7 @@ =20 /* PARF_SYS_CTRL register fields */ #define MAC_PHY_POWERDOWN_IN_P2_D_MUX_EN BIT(29) +#define PCIE_ECAM_BLOCKER_EN BIT(26) #define MST_WAKEUP_EN BIT(13) #define SLV_WAKEUP_EN BIT(12) #define MSTR_ACLK_CGC_DIS BIT(10) @@ -293,6 +306,48 @@ static void qcom_ep_reset_deassert(struct qcom_pcie *p= cie) usleep_range(PERST_DELAY_US, PERST_DELAY_US + 500); } =20 +static void qcom_pci_config_ecam(struct dw_pcie_rp *pp) +{ + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); + struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u64 addr, addr_end; + u32 val; + + /* Set the ECAM base */ + writel_relaxed(lower_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_= BASE); + writel_relaxed(upper_32_bits(pci->dbi_phys_addr), pcie->parf + PARF_ECAM_= BASE_HI); + + /* + * The only device on root bus is the Root Port. Any access to the PCIe + * region will go outside the PCIe link. As part of enumeration the PCI + * sw can try to read to vendor ID & device ID with different device + * number and function number under root bus. As any access other than + * root bus, device 0, function 0, should not go out of the link and + * should return all F's. Since the iATU is configured for the buses + * which starts after root bus, block the transactions starting from + * function 1 of the root bus to the end of the root bus (i.e from + * dbi_base + 4kb to dbi_base + 1MB) from going outside the link. + */ + addr =3D pci->dbi_phys_addr + SZ_4K; + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BA= SE); + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_WR_BA= SE_HI); + + writel_relaxed(lower_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BA= SE); + writel_relaxed(upper_32_bits(addr), pcie->parf + PARF_BLOCK_SLV_AXI_RD_BA= SE_HI); + + addr_end =3D pci->dbi_phys_addr + SZ_1M - 1; + + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_W= R_LIMIT); + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_W= R_LIMIT_HI); + + writel_relaxed(lower_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_R= D_LIMIT); + writel_relaxed(upper_32_bits(addr_end), pcie->parf + PARF_BLOCK_SLV_AXI_R= D_LIMIT_HI); + + val =3D readl_relaxed(pcie->parf + PARF_SYS_CTRL); + val |=3D PCIE_ECAM_BLOCKER_EN; + writel_relaxed(val, pcie->parf + PARF_SYS_CTRL); +} + static int qcom_pcie_start_link(struct dw_pcie *pci) { struct qcom_pcie *pcie =3D to_qcom_pcie(pci); @@ -302,6 +357,9 @@ static int qcom_pcie_start_link(struct dw_pcie *pci) qcom_pcie_common_set_16gt_lane_margining(pci); } =20 + if (pci->pp.ecam_mode) + qcom_pci_config_ecam(&pci->pp); + /* Enable Link Training state machine */ if (pcie->cfg->ops->ltssm_enable) pcie->cfg->ops->ltssm_enable(pcie); @@ -1233,6 +1291,7 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) { struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); struct qcom_pcie *pcie =3D to_qcom_pcie(pci); + u16 offset; int ret; =20 qcom_ep_reset_assert(pcie); @@ -1241,6 +1300,11 @@ static int qcom_pcie_host_init(struct dw_pcie_rp *pp) if (ret) return ret; =20 + if (pp->ecam_mode) { + offset =3D readl(pcie->parf + PARF_SLV_DBI_ELBI); + pci->elbi_base =3D pci->dbi_base + offset; + } + ret =3D phy_set_mode_ext(pcie->phy, PHY_MODE_PCIE, PHY_MODE_PCIE_RC); if (ret) goto err_deinit; --=20 2.34.1