From nobody Mon Feb 9 15:45:38 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5D5E61B87ED for ; Sat, 8 Mar 2025 12:21:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741436497; cv=none; b=CTv6fRQnb7gpFeaoGBa8bn5GZr0kC7a6Wd6oVQpAvWrV7yj9F5PuA2bo770CHtHT+xQGgD+uLkrwgsPMS/lYXqPoTY47zrh3xU+4zxAMej/L0jLoS7b3/vcw0tvIKHbNfJiusNZ1WSkIVv4L2inRAqYm85QqgVkxHTZsbtYKjF0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741436497; c=relaxed/simple; bh=JVO6B5huh7eGDo+k3A1fG3SKCxGyB11XeWKMxuuZ+rw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=GjPtNIPamfSuE3CHkGPArVDhwhqlxd9cMOE8b/sKWndvd68x7Q9jKoupPu2tATteJL7bVJZRIrr7ozgFDv8PbvpdNRu3Yr7HQgSAevnUQEoZtPDesrQFSKOWN5FvG0KMez7+bXgDGSpFJruoZS6HtqyzbHHKYNrfO6aK6jp4Qgg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=HPioRTv4; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="HPioRTv4" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741436493; bh=JVO6B5huh7eGDo+k3A1fG3SKCxGyB11XeWKMxuuZ+rw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=HPioRTv4CnTVqQh81bzz/2o6ENJerd7U3kGDTqmShoHEsNZdO5m193+SPAfLDvBA4 Qu5Qktc3iCmujLpVZPu82JaSRVAsvtw1XY0rvJOddfFWDc+Bb0ChVfT7gs0Fus4eL4 ofppyfFyejOWHhE+B/TvP7ow4WBDwqsVT7qXMk/Ta/BeWmsp76dGcM8kYPCypYZhLX Gp0Op8err6kj/xSCDn71TY50aXBNVg3Se+UrC0BSK0/fd9Y0zls7SkX4WKw+YVqhmG uWqWH1Phr0PYzHZso4pKqksBnLOobfDxZ2eeFcO6XaSY9YHIjXvRyPOfKFMViss5Y2 WM4qraw/HTawg== Received: from localhost (unknown [84.232.140.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 6300117E1016; Sat, 8 Mar 2025 13:21:33 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 08 Mar 2025 14:21:12 +0200 Subject: [PATCH v5 03/12] phy: rockchip: samsung-hdptx: Fix clock ratio setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250308-phy-sam-hdptx-bpc-v5-3-35087287f9d1@collabora.com> References: <20250308-phy-sam-hdptx-bpc-v5-0-35087287f9d1@collabora.com> In-Reply-To: <20250308-phy-sam-hdptx-bpc-v5-0-35087287f9d1@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The switch from 1/10 to 1/40 clock ratio must happen when exceeding the 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, and not before. While at it, introduce a define for this rate limit constant. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea Reviewed-by: Dmitry Baryshkov --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index f88369864c50e4563834ccbb26f1f9f440e99271..cf2c3a46604cb9d8c26fe5ec834= 6904e0b62848f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -320,6 +320,7 @@ #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) =20 +#define HDMI14_MAX_RATE 340000000 #define HDMI20_MAX_RATE 600000000 =20 enum dp_link_rate { @@ -1072,7 +1073,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_= hdptx_phy *hdptx, =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 - if (rate >=3D 3400000) { + if (rate > HDMI14_MAX_RATE / 100) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { --=20 2.48.1