From nobody Mon Feb 9 21:21:11 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 029F91DE4E7 for ; Sat, 8 Mar 2025 12:21:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741436507; cv=none; b=KH2ywK+KYAsIyPuTLcy25OkIKC+BkFsdN7SaEUiTUabxgnTOfiNcNC1hPy/9tl7Ee/CaDtnKeCykYicDWYnYrNN8LMpTBFNyH7pDBwPDt/+WqrJxauwpKjhe958fMSdJkQo6b4yyNkKxP9hZVh8/NViKArqtl8ocU6VCKegidUo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741436507; c=relaxed/simple; bh=N/G4fkXT6+5018ut/u7iPs197Kprin8y3w6PxA82c28=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U1eof6nZPdLJhiERHBHIHZTl5jUfXB2WEjgK4A9aX1MXa1eENd7kEFufBpSqb7yTglrqzMtgJlGp4Xt2KZTuoVGe+zNmyliXR+Jqx4hTye6B00XqW+MclZ1w16iJ41vJt4/9/fvmJ/qGfgncJ52c5sIzF7d5OFK0AsFPVryxEsE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=U2XOPCiF; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="U2XOPCiF" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741436503; bh=N/G4fkXT6+5018ut/u7iPs197Kprin8y3w6PxA82c28=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=U2XOPCiFIW4WzxDh6yoKgHua2O9ZIJN5lN1htAVzEanZwTWda5Wyv7Iw8u+5Av9nG 6mfI8k+U+Y5lB2dhgW92KsyZ4VQw4E9rdLuQU4tmpWcAqGUTgVzPXkmSC6RtgOUnzm z5D4JxXaXHjOj5XJ7BF6qHd9lyuquLfK8k5IGfX9X11dBPuOZGrNIVIf4VsK1cdTvN LENTBh/bQULK5Kf+fXpuewxQhiGAUbYUHHlU5Tv33riXDx6erplG1D/Aiy7Jnc9H45 5veuAfllGeB/+Sn+14Ou8wxXgWuygeuU7h02971c40rR0haGe3rrwzjxAPvf6cFij0 jllIryqGRIeLg== Received: from localhost (unknown [84.232.140.93]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 58C4517E1022; Sat, 8 Mar 2025 13:21:43 +0100 (CET) From: Cristian Ciocaltea Date: Sat, 08 Mar 2025 14:21:20 +0200 Subject: [PATCH v5 11/12] phy: rockchip: samsung-hdptx: Optimize internal rate handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250308-phy-sam-hdptx-bpc-v5-11-35087287f9d1@collabora.com> References: <20250308-phy-sam-hdptx-bpc-v5-0-35087287f9d1@collabora.com> In-Reply-To: <20250308-phy-sam-hdptx-bpc-v5-0-35087287f9d1@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Drop the rate parameter from a bunch of internal helpers and, instead, make better use of the newly introduced ->hdmi_cfg.tmds_char_rate driver data. Additionally, rename the rather ambiguous ->rate member of struct rk_hdptx_phy to ->hw_rate and ensure rk_hdptx_ropll_tmds_cmn_config() updates it only after all the other operations have been successful. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 59 ++++++++++++-------= ---- 1 file changed, 30 insertions(+), 29 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index a62c634f5254e742088515c3b21c05f95acbaded..98f831c3704f5cd65dcf29a4f0a= 12862a4aa0482 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -401,7 +401,7 @@ struct rk_hdptx_phy { =20 /* clk provider */ struct clk_hw hw; - unsigned long rate; + unsigned long hw_rate; bool restrict_rate_change; =20 atomic_t usage_count; @@ -968,33 +968,34 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned long r= ate, return true; } =20 -static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - unsigned long rate) +static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx) { const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; - int i; + int ret, i; =20 - hdptx->rate =3D rate; + if (!hdptx->hdmi_cfg.tmds_char_rate) + return 0; =20 for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (rate =3D=3D ropll_tmds_cfg[i].rate) { + if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) { cfg =3D &ropll_tmds_cfg[i]; break; } =20 if (!cfg) { - if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) { - cfg =3D &rc; - } else { - dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__); + if (!rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) { + dev_err(hdptx->dev, "%s cannot find pll cfg for rate=3D%llu\n", + __func__, hdptx->hdmi_cfg.tmds_char_rate); return -EINVAL; } + + cfg =3D &rc; } =20 - dev_dbg(hdptx->dev, "%s rate=3D%lu mdiv=3D%u sdiv=3D%u sdm_en=3D%u k_sign= =3D%u k=3D%u lc=3D%u\n", - __func__, rate, cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, - cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); + dev_dbg(hdptx->dev, "%s rate=3D%llu mdiv=3D%u sdiv=3D%u sdm_en=3D%u k_sig= n=3D%u k=3D%u lc=3D%u\n", + __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv += 1, + cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); =20 rk_hdptx_pre_power_up(hdptx); =20 @@ -1030,17 +1031,20 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk= _hdptx_phy *hdptx, regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); =20 - return rk_hdptx_post_enable_pll(hdptx); + ret =3D rk_hdptx_post_enable_pll(hdptx); + if (!ret) + hdptx->hw_rate =3D hdptx->hdmi_cfg.tmds_char_rate; + + return ret; } =20 -static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - unsigned long rate) +static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx) { rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 - if (rate > HDMI14_MAX_RATE) { + if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { @@ -1092,8 +1096,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hd= ptx) HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0)); } =20 -static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx, - unsigned long rate) +static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx) { enum phy_mode mode =3D phy_get_mode(hdptx->phy); u32 status; @@ -1112,11 +1115,9 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx= _phy *hdptx, if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { - if (rate) { - ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); - if (ret) - goto dec_usage; - } + ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx); + if (ret) + goto dec_usage; } =20 return 0; @@ -1429,7 +1430,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) dev_dbg(hdptx->dev, "%s rate=3D%llu\n", __func__, hdptx->hdmi_cfg.tmds_c= har_rate); } =20 - ret =3D rk_hdptx_phy_consumer_get(hdptx, hdptx->hdmi_cfg.tmds_char_rate); + ret =3D rk_hdptx_phy_consumer_get(hdptx); if (ret) return ret; =20 @@ -1460,7 +1461,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) regmap_write(hdptx->grf, GRF_HDPTX_CON0, HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); =20 - ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx, hdptx->hdmi_cfg.tmds_char= _rate); + ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx); if (ret) rk_hdptx_phy_consumer_put(hdptx, true); } @@ -1828,7 +1829,7 @@ static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 - return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate); + return rk_hdptx_phy_consumer_get(hdptx); } =20 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) @@ -1843,7 +1844,7 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(str= uct clk_hw *hw, { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 - return hdptx->rate; + return hdptx->hw_rate; } =20 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, @@ -1895,7 +1896,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *h= w, unsigned long rate, * while the latter being executed only once, i.e. when clock remains * in the prepared state during rate changes. */ - return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); + return rk_hdptx_ropll_tmds_cmn_config(hdptx); } =20 static const struct clk_ops hdptx_phy_clk_ops =3D { --=20 2.48.1