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([188.163.112.51]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498b0bd148sm409886e87.139.2025.03.07.00.11.17 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 00:11:18 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 1/3] dt-bindings: display: tegra: document EPP, ISP, MPE and TSEC for Tegra114 and Tegra124 Date: Fri, 7 Mar 2025 10:10:45 +0200 Message-ID: <20250307081047.13724-2-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307081047.13724-1-clamor95@gmail.com> References: <20250307081047.13724-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The current EPP, ISP and MPE schemas are largely compatible with Tegra114 a= nd Tegra124, requiring only minor adjustments. Additionally, the TSEC schema for the Sec= urity engine, which is available from Tegra114 onwards, is included. Signed-off-by: Svyatoslav Ryhel --- .../display/tegra/nvidia,tegra114-tsec.yaml | 70 +++++++++++++++++++ .../display/tegra/nvidia,tegra20-epp.yaml | 12 ++-- .../display/tegra/nvidia,tegra20-isp.yaml | 16 +++-- .../display/tegra/nvidia,tegra20-mpe.yaml | 30 ++++++-- 4 files changed, 114 insertions(+), 14 deletions(-) create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,= tegra114-tsec.yaml diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra11= 4-tsec.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra1= 14-tsec.yaml new file mode 100644 index 000000000000..84d9ab9394d5 --- /dev/null +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra114-tsec.= yaml @@ -0,0 +1,70 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra114-tsec.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra Security co-processor + +maintainers: + - Svyatoslav Ryhel + - Thierry Reding + +properties: + compatible: + oneOf: + - const: nvidia,tegra114-tsec + - const: nvidia,tegra124-tsec + - items: + - const: nvidia,tegra132-tsec + - const: nvidia,tegra124-tsec + - const: nvidia,tegra210-tsec + + reg: + maxItems: 1 + + interrupts: + maxItems: 1 + + clocks: + items: + - description: module clock + + resets: + items: + - description: module reset + + reset-names: + items: + - const: tsec + + iommus: + maxItems: 1 + + interconnects: + maxItems: 6 + + interconnect-names: + maxItems: 6 + + operating-points-v2: true + + power-domains: + items: + - description: phandle to the core power domain + +additionalProperties: false + +examples: + - | + #include + #include + + tsec@54500000 { + compatible =3D "nvidia,tegra114-tsec"; + reg =3D <0x54500000 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_TSEC>; + resets =3D <&tegra_car TEGRA114_CLK_TSEC>; + reset-names =3D "tsec"; + }; diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20= -epp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-= epp.yaml index 3c095a5491fe..a50e3261a191 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.ya= ml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-epp.ya= ml @@ -15,10 +15,14 @@ properties: pattern: "^epp@[0-9a-f]+$" =20 compatible: - enum: - - nvidia,tegra20-epp - - nvidia,tegra30-epp - - nvidia,tegra114-epp + oneOf: + - const: nvidia,tegra20-epp + - const: nvidia,tegra30-epp + - const: nvidia,tegra114-epp + - const: nvidia,tegra124-epp + - items: + - const: nvidia,tegra132-epp + - const: nvidia,tegra124-epp =20 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20= -isp.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-= isp.yaml index 3bc3b22e98e1..bfef4f26a3d7 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.ya= ml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-isp.ya= ml @@ -11,11 +11,19 @@ maintainers: - Jon Hunter =20 properties: + $nodename: + pattern: "^isp@[0-9a-f]+$" + compatible: - enum: - - nvidia,tegra20-isp - - nvidia,tegra30-isp - - nvidia,tegra210-isp + oneOf: + - const: nvidia,tegra20-isp + - const: nvidia,tegra30-isp + - const: nvidia,tegra114-isp + - const: nvidia,tegra124-isp + - items: + - const: nvidia,tegra132-isp + - const: nvidia,tegra124-isp + - const: nvidia,tegra210-isp =20 reg: maxItems: 1 diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20= -mpe.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-= mpe.yaml index 2cd3e60cd0a8..35e3991f1135 100644 --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.ya= ml +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra20-mpe.ya= ml @@ -12,13 +12,19 @@ maintainers: =20 properties: $nodename: - pattern: "^mpe@[0-9a-f]+$" + oneOf: + - pattern: "^mpe@[0-9a-f]+$" + - pattern: "^msenc@[0-9a-f]+$" =20 compatible: - enum: - - nvidia,tegra20-mpe - - nvidia,tegra30-mpe - - nvidia,tegra114-mpe + oneOf: + - const: nvidia,tegra20-mpe + - const: nvidia,tegra30-mpe + - const: nvidia,tegra114-msenc + - const: nvidia,tegra124-msenc + - items: + - const: nvidia,tegra132-msenc + - const: nvidia,tegra124-msenc =20 reg: maxItems: 1 @@ -36,7 +42,9 @@ properties: =20 reset-names: items: - - const: mpe + - enum: + - mpe + - msenc =20 iommus: maxItems: 1 @@ -58,6 +66,7 @@ additionalProperties: false examples: - | #include + #include #include =20 mpe@54040000 { @@ -68,3 +77,12 @@ examples: resets =3D <&tegra_car 60>; reset-names =3D "mpe"; }; + + msenc@544c0000 { + compatible =3D "nvidia,tegra114-msenc"; + reg =3D <0x544c0000 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_MSENC>; + resets =3D <&tegra_car TEGRA114_CLK_MSENC>; + reset-names =3D "msenc"; + }; --=20 2.43.0 From nobody Sun Feb 8 18:44:28 2026 Received: from mail-lf1-f49.google.com (mail-lf1-f49.google.com [209.85.167.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 050E81B86EF; Fri, 7 Mar 2025 08:11:23 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.49 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741335085; cv=none; b=R0Sf+0v4uTanMiJQNH5Wzz3hSE+HuOJCeWIzgsondwOEJzwhFpZXQBn8d9wFWfM1OMjNG6suwYPN5cSAqos4UVL0C2vhJvpwiRC+DgV9oGp2/LOHhJw1A+ag93n10QHkyf69WHdOH0pU9Vf3b9MJLixsYT3W/GwUXz64E0VeRMw= ARC-Message-Signature: i=1; a=rsa-sha256; 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([188.163.112.51]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498b0bd148sm409886e87.139.2025.03.07.00.11.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 00:11:21 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 2/3] ARM: tegra114: complete HOST1X devices binding Date: Fri, 7 Mar 2025 10:10:46 +0200 Message-ID: <20250307081047.13724-3-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307081047.13724-1-clamor95@gmail.com> References: <20250307081047.13724-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for devices on the HOST1X bus: VI, EPP, ISP, MSENC and TSEC. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra114.dtsi | 65 ++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra114.dtsi b/arch/arm/boot/dts/nvi= dia/tegra114.dtsi index 4caf2073c556..e2623a0629d2 100644 --- a/arch/arm/boot/dts/nvidia/tegra114.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra114.dtsi @@ -47,6 +47,45 @@ host1x@50000000 { =20 ranges =3D <0x54000000 0x54000000 0x01000000>; =20 + vi@54080000 { + compatible =3D "nvidia,tegra114-vi"; + reg =3D <0x54080000 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_VI>; + resets =3D <&tegra_car 20>; + reset-names =3D "vi"; + + iommus =3D <&mc TEGRA_SWGROUP_VI>; + + status =3D "disabled"; + }; + + epp@540c0000 { + compatible =3D "nvidia,tegra114-epp"; + reg =3D <0x540c0000 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_EPP>; + resets =3D <&tegra_car TEGRA114_CLK_EPP>; + reset-names =3D "epp"; + + iommus =3D <&mc TEGRA_SWGROUP_EPP>; + + status =3D "disabled"; + }; + + isp@54100000 { + compatible =3D "nvidia,tegra114-isp"; + reg =3D <0x54100000 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_ISP>; + resets =3D <&tegra_car TEGRA114_CLK_ISP>; + reset-names =3D "isp"; + + iommus =3D <&mc TEGRA_SWGROUP_ISP>; + + status =3D "disabled"; + }; + gr2d@54140000 { compatible =3D "nvidia,tegra114-gr2d"; reg =3D <0x54140000 0x00040000>; @@ -149,6 +188,32 @@ dsib: dsi@54400000 { #address-cells =3D <1>; #size-cells =3D <0>; }; + + msenc@544c0000 { + compatible =3D "nvidia,tegra114-msenc"; + reg =3D <0x544c0000 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_MSENC>; + resets =3D <&tegra_car TEGRA114_CLK_MSENC>; + reset-names =3D "msenc"; + + iommus =3D <&mc TEGRA_SWGROUP_MSENC>; + + status =3D "disabled"; + }; + + tsec@54500000 { + compatible =3D "nvidia,tegra114-tsec"; + reg =3D <0x54500000 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA114_CLK_TSEC>; + resets =3D <&tegra_car TEGRA114_CLK_TSEC>; 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([188.163.112.51]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5498b0bd148sm409886e87.139.2025.03.07.00.11.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 07 Mar 2025 00:11:23 -0800 (PST) From: Svyatoslav Ryhel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Thierry Reding , Jonathan Hunter , Svyatoslav Ryhel Cc: devicetree@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org Subject: [PATCH v2 3/3] ARM: tegra124: complete HOST1X devices binding Date: Fri, 7 Mar 2025 10:10:47 +0200 Message-ID: <20250307081047.13724-4-clamor95@gmail.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250307081047.13724-1-clamor95@gmail.com> References: <20250307081047.13724-1-clamor95@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add nodes for devices on the HOST1X bus: VI, ISP, ISPB, MSENC and TSEC. Signed-off-by: Svyatoslav Ryhel --- arch/arm/boot/dts/nvidia/tegra124.dtsi | 65 ++++++++++++++++++++++++++ 1 file changed, 65 insertions(+) diff --git a/arch/arm/boot/dts/nvidia/tegra124.dtsi b/arch/arm/boot/dts/nvi= dia/tegra124.dtsi index ec4f0e346b2b..8181e5d88654 100644 --- a/arch/arm/boot/dts/nvidia/tegra124.dtsi +++ b/arch/arm/boot/dts/nvidia/tegra124.dtsi @@ -103,6 +103,45 @@ host1x@50000000 { =20 ranges =3D <0 0x54000000 0 0x54000000 0 0x01000000>; =20 + vi@54080000 { + compatible =3D "nvidia,tegra124-vi"; + reg =3D <0x0 0x54080000 0x0 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA124_CLK_VI>; + resets =3D <&tegra_car 20>; + reset-names =3D "vi"; + + iommus =3D <&mc TEGRA_SWGROUP_VI>; + + status =3D "disabled"; + }; + + isp@54600000 { + compatible =3D "nvidia,tegra124-isp"; + reg =3D <0x0 0x54600000 0x0 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA124_CLK_ISP>; + resets =3D <&tegra_car TEGRA124_CLK_ISP>; + reset-names =3D "isp"; + + iommus =3D <&mc TEGRA_SWGROUP_ISP2>; + + status =3D "disabled"; + }; + + isp@54680000 { + compatible =3D "nvidia,tegra124-isp"; + reg =3D <0x0 0x54680000 0x0 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA124_CLK_ISPB>; + resets =3D <&tegra_car TEGRA124_CLK_ISPB>; + reset-names =3D "ispb"; + + iommus =3D <&mc TEGRA_SWGROUP_ISP2B>; + + status =3D "disabled"; + }; + dc@54200000 { compatible =3D "nvidia,tegra124-dc"; reg =3D <0x0 0x54200000 0x0 0x00040000>; @@ -209,6 +248,32 @@ dsib: dsi@54400000 { #size-cells =3D <0>; }; =20 + msenc@544c0000 { + compatible =3D "nvidia,tegra124-msenc"; + reg =3D <0x0 0x544c0000 0x0 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA124_CLK_MSENC>; + resets =3D <&tegra_car TEGRA124_CLK_MSENC>; + reset-names =3D "msenc"; + + iommus =3D <&mc TEGRA_SWGROUP_MSENC>; + + status =3D "disabled"; + }; + + tsec@54500000 { + compatible =3D "nvidia,tegra124-tsec"; + reg =3D <0x0 0x54500000 0x0 0x00040000>; + interrupts =3D ; + clocks =3D <&tegra_car TEGRA124_CLK_TSEC>; + resets =3D <&tegra_car TEGRA124_CLK_TSEC>; + reset-names =3D "tsec"; + + iommus =3D <&mc TEGRA_SWGROUP_TSEC>; + + status =3D "disabled"; + }; + sor@54540000 { compatible =3D "nvidia,tegra124-sor"; reg =3D <0x0 0x54540000 0x0 0x00040000>; --=20 2.43.0