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Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mt8196-scpsys.h | 114 ++++ drivers/pmdomain/mediatek/mtk-scpsys.c | 629 ++++++++++++++++++++++ 2 files changed, 743 insertions(+) create mode 100644 drivers/pmdomain/mediatek/mt8196-scpsys.h diff --git a/drivers/pmdomain/mediatek/mt8196-scpsys.h b/drivers/pmdomain/m= ediatek/mt8196-scpsys.h new file mode 100644 index 000000000000..07cb08eaa920 --- /dev/null +++ b/drivers/pmdomain/mediatek/mt8196-scpsys.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Guangjie Song + */ +#ifndef __PMDOMAIN_MEDIATEK_MT8196_SCPSYS_H +#define __PMDOMAIN_MEDIATEK_MT8196_SCPSYS_H + +#define MT8196_SPM_CONN_PWR_CON 0xe04 +#define MT8196_SPM_SSUSB_DP_PHY_P0_PWR_CON 0xe18 +#define MT8196_SPM_SSUSB_P0_PWR_CON 0xe1c +#define MT8196_SPM_SSUSB_P1_PWR_CON 0xe20 +#define MT8196_SPM_SSUSB_P23_PWR_CON 0xe24 +#define MT8196_SPM_SSUSB_PHY_P2_PWR_CON 0xe28 +#define MT8196_SPM_PEXTP_MAC0_PWR_CON 0xe34 +#define MT8196_SPM_PEXTP_MAC1_PWR_CON 0xe38 +#define MT8196_SPM_PEXTP_MAC2_PWR_CON 0xe3c +#define MT8196_SPM_PEXTP_PHY0_PWR_CON 0xe40 +#define MT8196_SPM_PEXTP_PHY1_PWR_CON 0xe44 +#define MT8196_SPM_PEXTP_PHY2_PWR_CON 0xe48 +#define MT8196_SPM_AUDIO_PWR_CON 0xe4c +#define MT8196_SPM_ADSP_TOP_PWR_CON 0xe54 +#define MT8196_SPM_ADSP_INFRA_PWR_CON 0xe58 +#define MT8196_SPM_ADSP_AO_PWR_CON 0xe5c +#define MT8196_SPM_PWR_STATUS 0xf14 +#define MT8196_SPM_PWR_STATUS_2ND 0xf18 + +#define MT8196_SPM_BUS_PROTECT_EN 0xd8 +#define MT8196_SPM_BUS_PROTECT_EN_SET 0xdc +#define MT8196_SPM_BUS_PROTECT_EN_CLR 0xe0 +#define MT8196_SPM_BUS_PROTECT_RDY 0x208 + +#define MT8196_MM_PWR_STATUS 0x100 +#define MT8196_MM_PWR_STATUS_2ND 0x104 + +#define MT8196_VOTE_MTCMOS_SET0 0x218 +#define MT8196_VOTE_MTCMOS_CLR0 0x21c +#define MT8196_VOTE_MTCMOS_ENABLE0 0x1410 +#define MT8196_VOTE_MTCMOS_DONE0 0x141c +#define MT8196_VOTE_MTCMOS_SET_STATUS0 0x146c +#define MT8196_VOTE_MTCMOS_CLR_STATUS0 0x1470 + +#define MT8196_MM_VOTE_MTCMOS_SET0 0x218 +#define MT8196_MM_VOTE_MTCMOS_CLR0 0x21c +#define MT8196_MM_VOTE_MTCMOS_SET1 0x220 +#define MT8196_MM_VOTE_MTCMOS_CLR1 0x224 +#define MT8196_MM_VOTE_MTCMOS_ENABLE0 0x1410 +#define MT8196_MM_VOTE_MTCMOS_DONE0 0x141c +#define MT8196_MM_VOTE_MTCMOS_ENABLE1 0x1420 +#define MT8196_MM_VOTE_MTCMOS_DONE1 0x142c +#define MT8196_MM_VOTE_MTCMOS_SET_STATUS0 0x146c +#define MT8196_MM_VOTE_MTCMOS_CLR_STATUS0 0x1470 +#define MT8196_MM_VOTE_MTCMOS_SET_STATUS1 0x1474 +#define MT8196_MM_VOTE_MTCMOS_CLR_STATUS1 0x1478 +#define MT8196_MM_VOTE_MTCMOS_PM_ACK0 0x5514 +#define MT8196_MM_VOTE_MTCMOS_PM_ACK1 0x5518 + +#define MT8196_SPM_PROT_EN_BUS_CONN BIT(1) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0 BIT(6) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_P0 BIT(7) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_P1 BIT(8) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_P23 BIT(9) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2 BIT(10) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0 BIT(13) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1 BIT(14) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2 BIT(15) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0 BIT(16) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1 BIT(17) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2 BIT(18) +#define MT8196_SPM_PROT_EN_BUS_AUDIO BIT(19) +#define MT8196_SPM_PROT_EN_BUS_ADSP_TOP BIT(21) +#define MT8196_SPM_PROT_EN_BUS_ADSP_INFRA BIT(22) +#define MT8196_SPM_PROT_EN_BUS_ADSP_AO BIT(23) + +#define MT8196_VOTE_MM_PROC_SHIFT 0 +#define MT8196_VOTE_SSR_SHIFT 1 + +#define MT8196_MM_VOTE_VDE0_SHIFT 7 +#define MT8196_MM_VOTE_VDE1_SHIFT 8 +#define MT8196_MM_VOTE_VDE_VCORE0_SHIFT 9 +#define MT8196_MM_VOTE_VEN0_SHIFT 10 +#define MT8196_MM_VOTE_VEN1_SHIFT 11 +#define MT8196_MM_VOTE_VEN2_SHIFT 12 +#define MT8196_MM_VOTE_DISP_VCORE_SHIFT 24 +#define MT8196_MM_VOTE_DIS0_SHIFT 25 +#define MT8196_MM_VOTE_DIS1_SHIFT 26 +#define MT8196_MM_VOTE_OVL0_SHIFT 27 +#define MT8196_MM_VOTE_OVL1_SHIFT 28 +#define MT8196_MM_VOTE_DISP_EDPTX_SHIFT 29 +#define MT8196_MM_VOTE_DISP_DPTX_SHIFT 30 +#define MT8196_MM_VOTE_MML0_SHIFT 31 +#define MT8196_MM_VOTE_MML1_SHIFT 0 +#define MT8196_MM_VOTE_MM_INFRA0_SHIFT 1 +#define MT8196_MM_VOTE_MM_INFRA1_SHIFT 2 +#define MT8196_MM_VOTE_MM_INFRA_AO_SHIFT 3 +#define MT8196_MM_VOTE_CSI_BS_RX_SHIFT 5 +#define MT8196_MM_VOTE_CSI_LS_RX_SHIFT 6 +#define MT8196_MM_VOTE_DSI_PHY0_SHIFT 7 +#define MT8196_MM_VOTE_DSI_PHY1_SHIFT 8 +#define MT8196_MM_VOTE_DSI_PHY2_SHIFT 9 + +enum { + MT8196_SPM_BP_INVALID =3D 0, + MT8196_SPM_BP_SPM, + MT8196_SPM_BP_NR +}; + +enum { + MT8196_MMPC_BP_INVALID =3D 0, + MT8196_MMPC_BP_MMPC, + MT8196_MMPC_BP_NR, +}; + +#endif /* __PMDOMAIN_MEDIATEK_MT8196_SCPSYS_H */ diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 7bfe36c1a1ae..667e69ada125 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -20,6 +20,9 @@ #include #include #include +#include + +#include "mt8196-scpsys.h" =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -137,6 +140,8 @@ enum clk_id { CLK_HIFSEL, CLK_JPGDEC, CLK_AUDIO, + CLK_DISP_AO_CONFIG, + CLK_DISP_DPC, CLK_MAX, }; =20 @@ -151,6 +156,8 @@ static const char * const clk_names[] =3D { "hif_sel", "jpgdec", "audio", + "disp_ao_config", + "disp_dpc", NULL, }; =20 @@ -1575,6 +1582,594 @@ static const struct scp_subdomain scp_subdomain_mt8= 173[] =3D { {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, }; =20 +/* + * MT8196 power domain support + */ +static const char *mt8196_spm_bp_list[MT8196_SPM_BP_NR] =3D { + [MT8196_SPM_BP_SPM] =3D "spm", +}; + +static const struct scp_domain_data scp_domain_mt8196_spm_vote_data[] =3D { + [MT8196_POWER_DOMAIN_CONN] =3D { + .name =3D "conn", + .ctl_offs =3D MT8196_SPM_CONN_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_CONN), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_BYPA= SS_INIT_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0] =3D { + .name =3D "ssusb-dp-phy-p0", + .ctl_offs =3D MT8196_SPM_SSUSB_DP_PHY_P0_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, + MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_P0] =3D { + .name =3D "ssusb-p0", + .ctl_offs =3D MT8196_SPM_SSUSB_P0_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_SSUSB_P0), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_P1] =3D { + .name =3D "ssusb-p1", + .ctl_offs =3D MT8196_SPM_SSUSB_P1_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_SSUSB_P1), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_P23] =3D { + .name =3D "ssusb-p23", + .ctl_offs =3D MT8196_SPM_SSUSB_P23_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_SSUSB_P23), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_BYPA= SS_INIT_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_PHY_P2] =3D { + .name =3D "ssusb-phy-p2", + .ctl_offs =3D MT8196_SPM_SSUSB_PHY_P2_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, + MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_BYPA= SS_INIT_ON, + }, + [MT8196_POWER_DOMAIN_PEXTP_MAC0] =3D { + .name =3D "pextp-mac0", + .ctl_offs =3D MT8196_SPM_PEXTP_MAC0_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_MAC1] =3D { + .name =3D "pextp-mac1", + .ctl_offs =3D MT8196_SPM_PEXTP_MAC1_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_MAC2] =3D { + .name =3D "pextp-mac2", + .ctl_offs =3D MT8196_SPM_PEXTP_MAC2_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_PHY0] =3D { + .name =3D "pextp-phy0", + .ctl_offs =3D MT8196_SPM_PEXTP_PHY0_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_PHY1] =3D { + .name =3D "pextp-phy1", + .ctl_offs =3D MT8196_SPM_PEXTP_PHY1_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_PHY2] =3D { + .name =3D "pextp-phy2", + .ctl_offs =3D MT8196_SPM_PEXTP_PHY2_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .ctl_offs =3D MT8196_SPM_AUDIO_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_AUDIO), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF, + }, + [MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT] =3D { + .name =3D "adsp-top-dormant", + .ctl_offs =3D MT8196_SPM_ADSP_TOP_PWR_CON, + .sram_slp_bits =3D GENMASK(9, 9), + .sram_slp_ack_bits =3D GENMASK(13, 13), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_ADSP_TOP), + }, + .caps =3D MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_SLP | MTK_SCPD_IS_PWR_CON_ON, + }, + [MT8196_POWER_DOMAIN_ADSP_INFRA] =3D { + .name =3D "adsp-infra", + .ctl_offs =3D MT8196_SPM_ADSP_INFRA_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_ADSP_INFRA), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_ADSP_AO] =3D { + .name =3D "adsp-ao", + .ctl_offs =3D MT8196_SPM_ADSP_AO_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_ADSP_AO), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_MM_PROC_DORMANT] =3D { + .name =3D "mm-proc-dormant", + .vote_comp =3D "vote-regmap", + .vote_set_ofs =3D MT8196_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_VOTE_MTCMOS_ENABLE0, + .vote_set_sta_ofs =3D MT8196_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_VOTE_MTCMOS_CLR_STATUS0, + .vote_shift =3D MT8196_VOTE_MM_PROC_SHIFT, + /* TODO: drop MTK_SCPD_ALWAYS_ON after fixing suspend issue. */ + .caps =3D MTK_SCPD_VOTE_OPS | MTK_SCPD_IRQ_SAFE | MTK_SCPD_ALWAYS_ON, + }, + [MT8196_POWER_DOMAIN_SSR] =3D { + .name =3D "ssrsys", + .vote_comp =3D "vote-regmap", + .vote_set_ofs =3D MT8196_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_VOTE_MTCMOS_ENABLE0, + .vote_set_sta_ofs =3D MT8196_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_VOTE_MTCMOS_CLR_STATUS0, + .vote_shift =3D MT8196_VOTE_SSR_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8196_spm[] =3D { + {MT8196_POWER_DOMAIN_SSUSB_P0, MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0}, + {MT8196_POWER_DOMAIN_SSUSB_P23, MT8196_POWER_DOMAIN_SSUSB_PHY_P2}, + {MT8196_POWER_DOMAIN_PEXTP_MAC0, MT8196_POWER_DOMAIN_PEXTP_PHY0}, + {MT8196_POWER_DOMAIN_PEXTP_MAC1, MT8196_POWER_DOMAIN_PEXTP_PHY1}, + {MT8196_POWER_DOMAIN_PEXTP_MAC2, MT8196_POWER_DOMAIN_PEXTP_PHY2}, + {MT8196_POWER_DOMAIN_ADSP_INFRA, MT8196_POWER_DOMAIN_AUDIO}, + {MT8196_POWER_DOMAIN_ADSP_INFRA, MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT}, + {MT8196_POWER_DOMAIN_ADSP_AO, MT8196_POWER_DOMAIN_ADSP_INFRA}, +}; + +static struct generic_pm_domain *mt8196_mm_proc_domain; + +static int mt8196_spm_post_probe(struct platform_device *pdev, struct scp = *scp) +{ + mt8196_mm_proc_domain =3D scp->pd_data.domains[MT8196_POWER_DOMAIN_MM_PRO= C_DORMANT]; + + return 0; +} + +static const char *mt8196_mmpc_bp_list[MT8196_MMPC_BP_NR] =3D { + [MT8196_MMPC_BP_MMPC] =3D "mmpc", +}; + +static const struct scp_domain_data scp_domain_mt8196_mmpc_vote_data[] =3D= { + [MT8196_POWER_DOMAIN_VDE0] =3D { + .name =3D "vde0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VDE0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VDE1] =3D { + .name =3D "vde1", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VDE1_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VDE_VCORE0] =3D { + .name =3D "vde-vcore0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VDE_VCORE0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VEN0] =3D { + .name =3D "ven0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VEN0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VEN1] =3D { + .name =3D "ven1", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VEN1_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VEN2] =3D { + .name =3D "ven2", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VEN2_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DISP_VCORE] =3D { + .name =3D "disp-vcore", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DISP_VCORE_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DIS0_DORMANT] =3D { + .name =3D "dis0-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DIS0_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DIS1_DORMANT] =3D { + .name =3D "dis1-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DIS1_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_OVL0_DORMANT] =3D { + .name =3D "ovl0-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_OVL0_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_OVL1_DORMANT] =3D { + .name =3D "ovl1-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_OVL1_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT] =3D { + .name =3D "disp-edptx-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DISP_EDPTX_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT] =3D { + .name =3D "disp-dptx-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DISP_DPTX_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_MML0_SHUTDOWN] =3D { + .name =3D "mml0-shutdown", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_MML0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_MML1_SHUTDOWN] =3D { + .name =3D "mml1-shutdown", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_MML0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_MM_INFRA0] =3D { + .name =3D "mm-infra0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_MM_INFRA0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS | MTK_SCPD_IRQ_SAFE, + }, + [MT8196_POWER_DOMAIN_MM_INFRA1] =3D { + .name =3D "mm-infra1", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_MM_INFRA1_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS | MTK_SCPD_IRQ_SAFE, + }, + [MT8196_POWER_DOMAIN_MM_INFRA_AO] =3D { + .name =3D "mm-infra-ao", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_MM_INFRA_AO_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS | MTK_SCPD_IRQ_SAFE, + }, + [MT8196_POWER_DOMAIN_CSI_BS_RX] =3D { + .name =3D "csi-bs-rx", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_CSI_BS_RX_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_CSI_LS_RX] =3D { + .name =3D "csi-ls-rx", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_CSI_LS_RX_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DSI_PHY0] =3D { + .name =3D "dsi-phy0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_DSI_PHY0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DSI_PHY1] =3D { + .name =3D "dsi-phy1", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_DSI_PHY1_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DSI_PHY2] =3D { + .name =3D "dsi-phy2", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_DSI_PHY2_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8196_mmpc[] =3D { + {MT8196_POWER_DOMAIN_VDE_VCORE0, MT8196_POWER_DOMAIN_VDE0}, + {MT8196_POWER_DOMAIN_VDE_VCORE0, MT8196_POWER_DOMAIN_VDE1}, + {MT8196_POWER_DOMAIN_VEN0, MT8196_POWER_DOMAIN_VEN1}, + {MT8196_POWER_DOMAIN_VEN1, MT8196_POWER_DOMAIN_VEN2}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_DIS0_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_DIS1_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_OVL0_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_OVL1_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_MML0_SHUTDOWN}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_MML1_SHUTDOWN}, + {MT8196_POWER_DOMAIN_MM_INFRA1, MT8196_POWER_DOMAIN_DISP_VCORE}, + {MT8196_POWER_DOMAIN_MM_INFRA1, MT8196_POWER_DOMAIN_VDE_VCORE0}, + {MT8196_POWER_DOMAIN_MM_INFRA1, MT8196_POWER_DOMAIN_VEN0}, + {MT8196_POWER_DOMAIN_MM_INFRA0, MT8196_POWER_DOMAIN_MM_INFRA1}, + {MT8196_POWER_DOMAIN_MM_INFRA_AO, MT8196_POWER_DOMAIN_MM_INFRA0}, +}; + +static int mt8196_mmpc_post_probe(struct platform_device *pdev, struct scp= *scp) +{ + int ret, i; + int subdomain[] =3D { + MT8196_POWER_DOMAIN_MM_INFRA_AO, + MT8196_POWER_DOMAIN_CSI_BS_RX, + MT8196_POWER_DOMAIN_CSI_LS_RX, + MT8196_POWER_DOMAIN_DSI_PHY0, + MT8196_POWER_DOMAIN_DSI_PHY1, + MT8196_POWER_DOMAIN_DSI_PHY2 + }; + + for (i =3D 0; i < ARRAY_SIZE(subdomain); i++) { + ret =3D pm_genpd_add_subdomain(mt8196_mm_proc_domain, scp->pd_data.domai= ns[subdomain[i]]); + if (ret && IS_ENABLED(CONFIG_PM)) { + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); + return ret; + } + } + + return 0; +} + static const struct scp_soc_data mt2701_data =3D { .domains =3D scp_domain_data_mt2701, .num_domains =3D ARRAY_SIZE(scp_domain_data_mt2701), @@ -1641,6 +2236,34 @@ static const struct scp_soc_data mt8173_data =3D { .bus_prot_reg_update =3D true, }; =20 +static const struct scp_soc_data mt8196_spm_vote_data =3D { + .domains =3D scp_domain_mt8196_spm_vote_data, + .num_domains =3D MT8196_SPM_POWER_DOMAIN_NR, + .subdomains =3D scp_subdomain_mt8196_spm, + .num_subdomains =3D ARRAY_SIZE(scp_subdomain_mt8196_spm), + .regs =3D { + .pwr_sta_offs =3D MT8196_SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D MT8196_SPM_PWR_STATUS_2ND, + }, + .bp_list =3D mt8196_spm_bp_list, + .num_bp =3D MT8196_SPM_BP_NR, + .post_probe =3D mt8196_spm_post_probe, +}; + +static const struct scp_soc_data mt8196_mmpc_vote_data =3D { + .domains =3D scp_domain_mt8196_mmpc_vote_data, + .num_domains =3D MT8196_MMPC_POWER_DOMAIN_NR, + .subdomains =3D scp_subdomain_mt8196_mmpc, + .num_subdomains =3D ARRAY_SIZE(scp_subdomain_mt8196_mmpc), + .regs =3D { + .pwr_sta_offs =3D MT8196_MM_PWR_STATUS, + .pwr_sta2nd_offs =3D MT8196_MM_PWR_STATUS_2ND, + }, + .bp_list =3D mt8196_mmpc_bp_list, + .num_bp =3D MT8196_MMPC_BP_NR, + .post_probe =3D mt8196_mmpc_post_probe, +}; + /* * scpsys driver init */ @@ -1664,6 +2287,12 @@ static const struct of_device_id of_scpsys_match_tbl= [] =3D { }, { .compatible =3D "mediatek,mt8173-scpsys", .data =3D &mt8173_data, + }, { + .compatible =3D "mediatek,mt8196-scpsys", + .data =3D &mt8196_spm_vote_data, + }, { + .compatible =3D "mediatek,mt8196-hfrpsys", + .data =3D &mt8196_mmpc_vote_data, }, { /* sentinel */ } --=20 2.45.2