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Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 1a80c1537a43..d53bd07a6804 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -25,6 +25,7 @@ =20 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) +#define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -56,6 +57,8 @@ #define PWR_ON_BIT BIT(2) #define PWR_ON_2ND_BIT BIT(3) #define PWR_CLK_DIS_BIT BIT(4) +#define PWR_SRAM_CLKISO_BIT BIT(5) +#define PWR_SRAM_ISOINT_B_BIT BIT(6) =20 #define PWR_STATUS_CONN BIT(1) #define PWR_STATUS_DISP BIT(3) @@ -257,6 +260,14 @@ static int scpsys_sram_enable(struct scp_domain *scpd,= void __iomem *ctl_addr) return ret; } =20 + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { + val =3D readl(ctl_addr) | PWR_SRAM_ISOINT_B_BIT; + writel(val, ctl_addr); + udelay(1); + val &=3D ~PWR_SRAM_CLKISO_BIT; + writel(val, ctl_addr); + } + return 0; } =20 @@ -266,6 +277,14 @@ static int scpsys_sram_disable(struct scp_domain *scpd= , void __iomem *ctl_addr) u32 pdn_ack =3D scpd->data->sram_pdn_ack_bits; int tmp; =20 + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { + val =3D readl(ctl_addr) | PWR_SRAM_CLKISO_BIT; + writel(val, ctl_addr); + val &=3D ~PWR_SRAM_ISOINT_B_BIT; + writel(val, ctl_addr); + udelay(1); + } + val =3D readl(ctl_addr); val |=3D scpd->data->sram_pdn_bits; writel(val, ctl_addr); --=20 2.45.2 From nobody Mon Feb 9 03:52:09 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6B2418E750; Fri, 7 Mar 2025 03:45:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=60.244.123.138 ARC-Seal: i=1; a=rsa-sha256; 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charset="utf-8" Support sram enter/exit low power mode. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 36 ++++++++++++++++++++------ 1 file changed, 28 insertions(+), 8 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index d53bd07a6804..9d03249284d6 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -26,6 +26,7 @@ #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) #define MTK_SCPD_SRAM_ISO BIT(2) +#define MTK_SCPD_SRAM_SLP BIT(3) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -118,6 +119,8 @@ static const char * const clk_names[] =3D { * @ctl_offs: The offset for main power control register. * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. + * @sram_slp_bits: The mask for sram low power control bits. + * @sram_slp_ack_bits: The mask for sram low power control acked bits. * @bus_prot_mask: The mask for single step bus protection. * @clk_id: The basic clocks required by this power domain. * @caps: The flag for active wake-up action. @@ -128,6 +131,8 @@ struct scp_domain_data { int ctl_offs; u32 sram_pdn_bits; u32 sram_pdn_ack_bits; + u32 sram_slp_bits; + u32 sram_slp_ack_bits; u32 bus_prot_mask; enum clk_id clk_id[MAX_CLKS]; u8 caps; @@ -236,11 +241,19 @@ static int scpsys_clk_enable(struct clk *clk[], int m= ax_num) static int scpsys_sram_enable(struct scp_domain *scpd, void __iomem *ctl_a= ddr) { u32 val; - u32 pdn_ack =3D scpd->data->sram_pdn_ack_bits; + u32 ack_mask, ack_sta; int tmp; =20 - val =3D readl(ctl_addr); - val &=3D ~scpd->data->sram_pdn_bits; + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_SLP)) { + ack_mask =3D scpd->data->sram_slp_ack_bits; + ack_sta =3D ack_mask; + val =3D readl(ctl_addr) | scpd->data->sram_slp_bits; + } else { + ack_mask =3D scpd->data->sram_pdn_ack_bits; + ack_sta =3D 0; + val =3D readl(ctl_addr) & ~scpd->data->sram_pdn_bits; + } + writel(val, ctl_addr); =20 /* Either wait until SRAM_PDN_ACK all 0 or have a force wait */ @@ -254,7 +267,7 @@ static int scpsys_sram_enable(struct scp_domain *scpd, = void __iomem *ctl_addr) } else { /* Either wait until SRAM_PDN_ACK all 1 or 0 */ int ret =3D readl_poll_timeout(ctl_addr, tmp, - (tmp & pdn_ack) =3D=3D 0, + (tmp & ack_mask) =3D=3D ack_sta, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret < 0) return ret; @@ -274,7 +287,7 @@ static int scpsys_sram_enable(struct scp_domain *scpd, = void __iomem *ctl_addr) static int scpsys_sram_disable(struct scp_domain *scpd, void __iomem *ctl_= addr) { u32 val; - u32 pdn_ack =3D scpd->data->sram_pdn_ack_bits; + u32 ack_mask, ack_sta; int tmp; =20 if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_ISO)) { @@ -285,13 +298,20 @@ static int scpsys_sram_disable(struct scp_domain *scp= d, void __iomem *ctl_addr) udelay(1); } =20 - val =3D readl(ctl_addr); - val |=3D scpd->data->sram_pdn_bits; + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_SRAM_SLP)) { + ack_mask =3D scpd->data->sram_slp_ack_bits; + ack_sta =3D 0; + val =3D readl(ctl_addr) & ~scpd->data->sram_slp_bits; + } else { + ack_mask =3D scpd->data->sram_pdn_ack_bits; + ack_sta =3D ack_mask; + val =3D readl(ctl_addr) | scpd->data->sram_pdn_bits; + } writel(val, ctl_addr); =20 /* Either wait until SRAM_PDN_ACK all 1 or 0 */ return readl_poll_timeout(ctl_addr, tmp, - (tmp & pdn_ack) =3D=3D pdn_ack, + (tmp & ack_mask) =3D=3D ack_sta, MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); 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Fri, 7 Mar 2025 11:44:59 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 7 Mar 2025 11:44:58 +0800 From: Guangjie Song To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson CC: , , , , , Guangjie Song , Subject: [PATCH 03/13] pmdomain: mediatek: Support power on bypass Date: Fri, 7 Mar 2025 11:44:27 +0800 Message-ID: <20250307034454.12243-4-guangjie.song@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250307034454.12243-1-guangjie.song@mediatek.com> References: <20250307034454.12243-1-guangjie.song@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support power on bypass in pmdomain driver probe. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 6 +++++- 1 file changed, 5 insertions(+), 1 deletion(-) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 9d03249284d6..3c8b5d8e7ee9 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -27,6 +27,7 @@ #define MTK_SCPD_FWAIT_SRAM BIT(1) #define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_SRAM_SLP BIT(3) +#define MTK_SCPD_BYPASS_INIT_ON BIT(4) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -569,7 +570,10 @@ static void mtk_register_power_domains(struct platform= _device *pdev, * software. The unused domains will be switched off during * late_init time. */ - on =3D !WARN_ON(genpd->power_on(genpd) < 0); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_BYPASS_INIT_ON)) + on =3D false; + else + on =3D !WARN_ON(genpd->power_on(genpd) < 0); =20 pm_genpd_init(genpd, NULL, !on); } --=20 2.45.2 From nobody Mon Feb 9 03:52:09 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 8CDF5190696; Fri, 7 Mar 2025 03:45:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=210.61.82.184 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741319109; cv=none; b=badNZRfUF/6ASbVj0jsgvyDsg+7/ApB8BVXv+IBY9TE4Zf/yZDzk5C37CaZLryLiPRgpLJg1f6IU9YD17LbAIddwJUn/WB+JmaxItRqkEJbDni+Ev+H1/VJq0NmlnvqP6KRaQ6UvJYm6LQUIsL9EHBJAmqn5afvUyaKw1vXqa+s= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741319109; c=relaxed/simple; bh=mJdPZ8cW8+CXFt0YQNQFQ0nsuc7GJonfa1zkNscDGOo=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Nkp8rcKbQzS9fSwox5fGe9bQ7Z4lz0S5f1bhut81ykeuFG20hHL83BkTVMlPWoZ51TuoXTvnp95X317PkV5N/u2dhhVpRabsBz+F60qNAy8ggGbRMdVBEZcSrYEzwn2gN1eFp6lZtfD+Qkvqe6nGn81YCpy7JY8wnF7Ivjo+5KI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com; spf=pass smtp.mailfrom=mediatek.com; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b=CbvezRpM; arc=none smtp.client-ip=210.61.82.184 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=mediatek.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=mediatek.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=mediatek.com header.i=@mediatek.com header.b="CbvezRpM" X-UUID: 8c72d894fb0611ef8eb9c36241bbb6fb-20250307 DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=mediatek.com; s=dk; h=Content-Type:Content-Transfer-Encoding:MIME-Version:References:In-Reply-To:Message-ID:Date:Subject:CC:To:From; bh=prxJuUSE8fevIr/DHvhqqrbFA9h0A7CHVLzUycKX/Po=; b=CbvezRpMVUsqogrQzAuv4SlM4VmXgn6Zs1G+a3d3cyCujs/boEzkjbwlEHQeQEAfqQoeRE9Lz+Yaln+I3qBmcjpbfUbi8h8IshJiOAIFWsgaq4TU3nozlyMFQJloOUMH57DPWWrb1XUvFv3gcgMAchsyemZ1k0LPY3zE/hLENTc=; X-CID-P-RULE: Release_Ham X-CID-O-INFO: VERSION:1.2.1,REQID:c5c9d0cb-deac-474e-a115-116bd80da8de,IP:0,UR L:0,TC:0,Content:0,EDM:0,RT:0,SF:0,FILE:0,BULK:0,RULE:Release_Ham,ACTION:r elease,TS:0 X-CID-META: VersionHash:0ef645f,CLOUDID:3697108c-f5b8-47d5-8cf3-b68fe7530c9a,B ulkID:nil,BulkQuantity:0,Recheck:0,SF:81|82|102,TC:nil,Content:0|50,EDM:-3 ,IP:nil,URL:0,File:nil,RT:nil,Bulk:nil,QS:nil,BEC:nil,COL:0,OSI:0,OSA:0,AV :0,LES:1,SPR:NO,DKR:0,DKP:0,BRR:0,BRE:0,ARC:0 X-CID-BVR: 0,NGT X-CID-BAS: 0,NGT,0,_ X-CID-FACTOR: TF_CID_SPAM_SNR X-UUID: 8c72d894fb0611ef8eb9c36241bbb6fb-20250307 Received: from mtkmbs11n1.mediatek.inc [(172.21.101.185)] by mailgw02.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-GCM-SHA384 256/256) with ESMTP id 3490628; Fri, 07 Mar 2025 11:45:01 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by MTKMBS09N2.mediatek.inc (172.21.101.94) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 7 Mar 2025 11:45:00 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 7 Mar 2025 11:44:59 +0800 From: Guangjie Song To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson CC: , , , , , Guangjie Song , Subject: [PATCH 04/13] pmdomain: mediatek: Support check power on/off ack Date: Fri, 7 Mar 2025 11:44:28 +0800 Message-ID: <20250307034454.12243-5-guangjie.song@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250307034454.12243-1-guangjie.song@mediatek.com> References: <20250307034454.12243-1-guangjie.song@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Support check ack bits for pmdomain on/off. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 50 +++++++++++++++++++++++--- 1 file changed, 46 insertions(+), 4 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 3c8b5d8e7ee9..2f75c606f7ba 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -22,12 +22,14 @@ =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC +#define MTK_ACK_DELAY_US 50 =20 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) #define MTK_SCPD_SRAM_ISO BIT(2) #define MTK_SCPD_SRAM_SLP BIT(3) #define MTK_SCPD_BYPASS_INIT_ON BIT(4) +#define MTK_SCPD_IS_PWR_CON_ON BIT(5) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -61,6 +63,8 @@ #define PWR_CLK_DIS_BIT BIT(4) #define PWR_SRAM_CLKISO_BIT BIT(5) #define PWR_SRAM_ISOINT_B_BIT BIT(6) +#define PWR_ACK BIT(30) +#define PWR_ACK_2ND BIT(31) =20 #define PWR_STATUS_CONN BIT(1) #define PWR_STATUS_DISP BIT(3) @@ -200,6 +204,20 @@ static int scpsys_domain_is_on(struct scp_domain *scpd) return -EINVAL; } =20 +static int scpsys_pwr_ack_is_on(struct scp_domain *scpd) +{ + u32 status =3D readl(scpd->scp->base + scpd->data->ctl_offs) & PWR_ACK; + + return status ? true : false; +} + +static int scpsys_pwr_ack_2nd_is_on(struct scp_domain *scpd) +{ + u32 status =3D readl(scpd->scp->base + scpd->data->ctl_offs) & PWR_ACK_2N= D; + + return status ? true : false; +} + static int scpsys_regulator_enable(struct scp_domain *scpd) { if (!scpd->supply) @@ -360,12 +378,25 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) val =3D readl(ctl_addr); val |=3D PWR_ON_BIT; writel(val, ctl_addr); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_IS_PWR_CON_ON)) { + ret =3D readx_poll_timeout_atomic(scpsys_pwr_ack_is_on, scpd, tmp, tmp >= 0, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) + goto err_pwr_ack; + + udelay(MTK_ACK_DELAY_US); + } + val |=3D PWR_ON_2ND_BIT; writel(val, ctl_addr); =20 /* wait until PWR_ACK =3D 1 */ - ret =3D readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp > 0, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_IS_PWR_CON_ON)) + ret =3D readx_poll_timeout_atomic(scpsys_pwr_ack_2nd_is_on, scpd, tmp, t= mp > 0, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + else + ret =3D readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp > 0, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); if (ret < 0) goto err_pwr_ack; =20 @@ -428,12 +459,23 @@ static int scpsys_power_off(struct generic_pm_domain = *genpd) val &=3D ~PWR_ON_BIT; writel(val, ctl_addr); =20 + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_IS_PWR_CON_ON)) { + ret =3D readx_poll_timeout_atomic(scpsys_pwr_ack_is_on, scpd, tmp, tmp = =3D=3D 0, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) + goto out; + } + val &=3D ~PWR_ON_2ND_BIT; writel(val, ctl_addr); =20 /* wait until PWR_ACK =3D 0 */ - ret =3D readx_poll_timeout(scpsys_domain_is_on, scpd, tmp, tmp =3D=3D 0, - MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_IS_PWR_CON_ON)) + ret =3D readx_poll_timeout_atomic(scpsys_pwr_ack_2nd_is_on, scpd, tmp, t= mp =3D=3D 0, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); 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charset="utf-8" Power domain supports voting mechanism. If any xPU votes power domain on, the power domain keep on. Add power domain vote support. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 207 ++++++++++++++++++++++++- 1 file changed, 205 insertions(+), 2 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 2f75c606f7ba..df9cd012006c 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -10,6 +10,7 @@ #include #include #include +#include #include #include =20 @@ -22,7 +23,12 @@ =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC +#define MTK_POLL_TIMEOUT_300MS (300 * USEC_PER_MSEC) +#define MTK_POLL_IRQ_TIMEOUT USEC_PER_SEC +#define MTK_POLL_VOTE_PREPARE_CNT 2500 +#define MTK_POLL_VOTE_PREPARE_US 2 #define MTK_ACK_DELAY_US 50 +#define MTK_STABLE_DELAY_US 100 =20 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) @@ -30,6 +36,7 @@ #define MTK_SCPD_SRAM_SLP BIT(3) #define MTK_SCPD_BYPASS_INIT_ON BIT(4) #define MTK_SCPD_IS_PWR_CON_ON BIT(5) +#define MTK_SCPD_VOTE_OPS BIT(6) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -120,8 +127,18 @@ static const char * const clk_names[] =3D { /** * struct scp_domain_data - scp domain data for power on/off flow * @name: The domain name. + * @vote_comp: The vote name. * @sta_mask: The mask for power on/off status bit. * @ctl_offs: The offset for main power control register. + * @vote_done_ofs: The offset for vote done register. + * @vote_ofs: The offset for vote register. + * @vote_set_ofs: The offset for vote set register. + * @vote_clr_ofs: The offset for vote clear register. + * @vote_en_ofs: The offset for voted register. + * @vote_set_sta_ofs: The offset for vote set status register. + * @vote_clr_sta_ofs: The offset for vote clear status register. + * @vote_ack_ofs: The offset for power control ack register. + * @vote_shift: The bit of vote. * @sram_pdn_bits: The mask for sram power control bits. * @sram_pdn_ack_bits: The mask for sram power control acked bits. * @sram_slp_bits: The mask for sram low power control bits. @@ -132,8 +149,18 @@ static const char * const clk_names[] =3D { */ struct scp_domain_data { const char *name; + const char *vote_comp; u32 sta_mask; int ctl_offs; + u32 vote_done_ofs; + u32 vote_ofs; + u32 vote_set_ofs; + u32 vote_clr_ofs; + u32 vote_en_ofs; + u32 vote_set_sta_ofs; + u32 vote_clr_sta_ofs; + u32 vote_ack_ofs; + u8 vote_shift; u32 sram_pdn_bits; u32 sram_pdn_ack_bits; u32 sram_slp_bits; @@ -151,6 +178,7 @@ struct scp_domain { struct clk *clk[MAX_CLKS]; const struct scp_domain_data *data; struct regulator *supply; + struct regmap *vote_regmap; }; =20 struct scp_ctrl_reg { @@ -493,6 +521,154 @@ static int scpsys_power_off(struct generic_pm_domain = *genpd) return ret; } =20 +static int mtk_vote_is_done(struct scp_domain *scpd) +{ + u32 val =3D 0, mask =3D 0; + + regmap_read(scpd->vote_regmap, scpd->data->vote_done_ofs, &val); + mask =3D BIT(scpd->data->vote_shift); + if ((val & mask) =3D=3D mask) + return 1; + + return 0; +} + +static int mtk_vote_is_enable_done(struct scp_domain *scpd) +{ + u32 done =3D 0, en =3D 0, set_sta =3D 0, mask =3D 0, ack =3D 0; + + regmap_read(scpd->vote_regmap, scpd->data->vote_done_ofs, &done); + regmap_read(scpd->vote_regmap, scpd->data->vote_en_ofs, &en); + regmap_read(scpd->vote_regmap, scpd->data->vote_set_sta_ofs, &set_sta); + mask =3D BIT(scpd->data->vote_shift); + + if ((done & mask) && (en & mask) && !(set_sta & mask)) { + if (scpd->data->vote_ack_ofs) { + regmap_read(scpd->vote_regmap, scpd->data->vote_ack_ofs, &ack); + if (!(ack & mask)) + return 0; + } + + return 1; + } + + return 0; +} + +static int mtk_vote_is_disable_done(struct scp_domain *scpd) +{ + u32 val =3D 0, val2 =3D 0; + + regmap_read(scpd->vote_regmap, scpd->data->vote_done_ofs, &val); + regmap_read(scpd->vote_regmap, scpd->data->vote_clr_sta_ofs, &val2); + + if ((val & BIT(scpd->data->vote_shift)) && + ((val2 & BIT(scpd->data->vote_shift)) =3D=3D 0x0)) + return 1; + + return 0; +} + +static int scpsys_vote_power_on(struct generic_pm_domain *genpd) +{ + struct scp_domain *scpd =3D container_of(genpd, struct scp_domain, genpd); + struct scp *scp =3D scpd->scp; + u32 val =3D 0; + int ret =3D 0; + int tmp; + int i =3D 0; + + ret =3D scpsys_regulator_enable(scpd); + if (ret < 0) + goto out; + + ret =3D scpsys_clk_enable(scpd->clk, MAX_CLKS); + if (ret) + goto out; + + ret =3D readx_poll_timeout_atomic(mtk_vote_is_done, scpd, tmp, tmp > 0, + MTK_POLL_DELAY_US, MTK_POLL_IRQ_TIMEOUT); + if (ret < 0) + goto out; + + val =3D BIT(scpd->data->vote_shift); + regmap_write(scpd->vote_regmap, scpd->data->vote_set_ofs, val); + do { + regmap_read(scpd->vote_regmap, scpd->data->vote_set_ofs, &val); + if ((val & BIT(scpd->data->vote_shift)) !=3D 0) + break; + + if (i > MTK_POLL_VOTE_PREPARE_CNT) + goto out; + + udelay(MTK_POLL_VOTE_PREPARE_US); + i++; + } while (1); + + /* add debounce time */ + udelay(1); + + /* wait until VOTER_ACK =3D 1 */ + ret =3D readx_poll_timeout_atomic(mtk_vote_is_enable_done, scpd, tmp, tmp= > 0, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT_300MS); + if (ret < 0) + goto out; + + return 0; +out: + dev_err(scp->dev, "Failed to power on domain %s(%d)\n", genpd->name, ret); + return ret; +} + +static int scpsys_vote_power_off(struct generic_pm_domain *genpd) +{ + struct scp_domain *scpd =3D container_of(genpd, struct scp_domain, genpd); + struct scp *scp =3D scpd->scp; + u32 val =3D 0; + int ret =3D 0; + int tmp; + int i =3D 0; + + ret =3D readx_poll_timeout_atomic(mtk_vote_is_done, scpd, tmp, tmp > 0, + MTK_POLL_DELAY_US, MTK_POLL_IRQ_TIMEOUT); + if (ret < 0) + goto out; + + val =3D BIT(scpd->data->vote_shift); + regmap_write(scpd->vote_regmap, scpd->data->vote_clr_ofs, val); + do { + regmap_read(scpd->vote_regmap, scpd->data->vote_clr_ofs, &val); + if ((val & BIT(scpd->data->vote_shift)) =3D=3D 0) + break; + + if (i > MTK_POLL_VOTE_PREPARE_CNT) + goto out; + + i++; + udelay(MTK_POLL_VOTE_PREPARE_US); + } while (1); + + /* delay 100us for stable status */ + udelay(MTK_STABLE_DELAY_US); + + /* wait until VOTER_ACK =3D 0 */ + ret =3D readx_poll_timeout_atomic(mtk_vote_is_disable_done, scpd, tmp, tm= p > 0, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT_300MS); + if (ret < 0) + goto out; + + scpsys_clk_disable(scpd->clk, MAX_CLKS); + + ret =3D scpsys_regulator_disable(scpd); + if (ret < 0) + goto out; + + return 0; +out: + dev_err(scp->dev, "Failed to power off domain %s(%d)\n", genpd->name, ret= ); + return ret; +} + static void init_clks(struct platform_device *pdev, struct clk **clk) { int i; @@ -501,6 +677,21 @@ static void init_clks(struct platform_device *pdev, st= ruct clk **clk) clk[i] =3D devm_clk_get(&pdev->dev, clk_names[i]); } =20 +static int mtk_pd_get_regmap(struct platform_device *pdev, struct regmap *= *regmap, + const char *name) +{ + *regmap =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_node, name); + if (PTR_ERR(*regmap) =3D=3D -ENODEV) { + dev_notice(&pdev->dev, "%s regmap is null(%ld)\n", name, PTR_ERR(*regmap= )); + *regmap =3D NULL; + } else if (IS_ERR(*regmap)) { + dev_notice(&pdev->dev, "Cannot find %s controller: %ld\n", name, PTR_ERR= (*regmap)); + return PTR_ERR(*regmap); + } + + return 0; +} + static struct scp *init_scp(struct platform_device *pdev, const struct scp_domain_data *scp_domain_data, int num, const struct scp_ctrl_reg *scp_ctrl_reg, @@ -510,6 +701,7 @@ static struct scp *init_scp(struct platform_device *pde= v, int i, j; struct scp *scp; struct clk *clk[CLK_MAX]; + int ret; =20 scp =3D devm_kzalloc(&pdev->dev, sizeof(*scp), GFP_KERNEL); if (!scp) @@ -585,9 +777,20 @@ static struct scp *init_scp(struct platform_device *pd= ev, scpd->clk[j] =3D c; } =20 + if (data->vote_comp) { + ret =3D mtk_pd_get_regmap(pdev, &scpd->vote_regmap, data->vote_comp); + if (ret) + return ERR_PTR(ret); + } + genpd->name =3D data->name; - genpd->power_off =3D scpsys_power_off; - genpd->power_on =3D scpsys_power_on; + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_VOTE_OPS)) { + genpd->power_on =3D scpsys_vote_power_on; + genpd->power_off =3D scpsys_vote_power_off; + } else { + genpd->power_off =3D scpsys_power_off; + genpd->power_on =3D scpsys_power_on; + } if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP)) genpd->flags |=3D GENPD_FLAG_ACTIVE_WAKEUP; } --=20 2.45.2 From nobody Mon Feb 9 03:52:09 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id AA0041917D9; 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charset="utf-8" Support trigger subsys save/restore registers during power domain on/off. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 106 ++++++++++++++++++++++++- 1 file changed, 105 insertions(+), 1 deletion(-) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index df9cd012006c..0ae4c617b5a6 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -28,6 +28,7 @@ #define MTK_POLL_VOTE_PREPARE_CNT 2500 #define MTK_POLL_VOTE_PREPARE_US 2 #define MTK_ACK_DELAY_US 50 +#define MTK_RTFF_DELAY_US 10 #define MTK_STABLE_DELAY_US 100 =20 #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) @@ -37,6 +38,10 @@ #define MTK_SCPD_BYPASS_INIT_ON BIT(4) #define MTK_SCPD_IS_PWR_CON_ON BIT(5) #define MTK_SCPD_VOTE_OPS BIT(6) +#define MTK_SCPD_NON_CPU_RTFF BIT(7) +#define MTK_SCPD_PEXTP_PHY_RTFF BIT(8) +#define MTK_SCPD_UFS_RTFF BIT(9) +#define MTK_SCPD_RTFF_DELAY BIT(10) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -70,6 +75,11 @@ #define PWR_CLK_DIS_BIT BIT(4) #define PWR_SRAM_CLKISO_BIT BIT(5) #define PWR_SRAM_ISOINT_B_BIT BIT(6) +#define PWR_RTFF_SAVE BIT(24) +#define PWR_RTFF_NRESTORE BIT(25) +#define PWR_RTFF_CLK_DIS BIT(26) +#define PWR_RTFF_SAVE_FLAG BIT(27) +#define PWR_RTFF_UFS_CLK_DIS BIT(28) #define PWR_ACK BIT(30) #define PWR_ACK_2ND BIT(31) =20 @@ -167,7 +177,7 @@ struct scp_domain_data { u32 sram_slp_ack_bits; u32 bus_prot_mask; enum clk_id clk_id[MAX_CLKS]; - u8 caps; + u32 caps; }; =20 struct scp; @@ -179,6 +189,7 @@ struct scp_domain { const struct scp_domain_data *data; struct regulator *supply; struct regmap *vote_regmap; + bool rtff_flag; }; =20 struct scp_ctrl_reg { @@ -428,15 +439,72 @@ static int scpsys_power_on(struct generic_pm_domain *= genpd) if (ret < 0) goto err_pwr_ack; =20 + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_PEXTP_PHY_RTFF) && scpd->rtff_flag) { + val |=3D PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + } + val &=3D ~PWR_CLK_DIS_BIT; writel(val, ctl_addr); =20 val &=3D ~PWR_ISO_BIT; writel(val, ctl_addr); =20 + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_RTFF_DELAY) && scpd->rtff_flag) + udelay(MTK_RTFF_DELAY_US); + val |=3D PWR_RST_B_BIT; writel(val, ctl_addr); =20 + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_NON_CPU_RTFF)) { + val =3D readl(ctl_addr); + if (val & PWR_RTFF_SAVE_FLAG) { + val &=3D ~PWR_RTFF_SAVE_FLAG; + writel(val, ctl_addr); + + val |=3D PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val |=3D PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + } + } else if (MTK_SCPD_CAPS(scpd, MTK_SCPD_PEXTP_PHY_RTFF)) { + val =3D readl(ctl_addr); + if (val & PWR_RTFF_SAVE_FLAG) { + val &=3D ~PWR_RTFF_SAVE_FLAG; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val |=3D PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + } + } else if (MTK_SCPD_CAPS(scpd, MTK_SCPD_UFS_RTFF) && scpd->rtff_flag) { + val |=3D PWR_RTFF_UFS_CLK_DIS; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val |=3D PWR_RTFF_NRESTORE; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_UFS_CLK_DIS; + writel(val, ctl_addr); + + scpd->rtff_flag =3D false; + } + ret =3D scpsys_sram_enable(scpd, ctl_addr); if (ret < 0) goto err_pwr_ack; @@ -475,9 +543,45 @@ static int scpsys_power_off(struct generic_pm_domain *= genpd) =20 /* subsys power off */ val =3D readl(ctl_addr); + + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_NON_CPU_RTFF) || + MTK_SCPD_CAPS(scpd, MTK_SCPD_PEXTP_PHY_RTFF)) { + val |=3D PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + + val |=3D PWR_RTFF_SAVE; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_SAVE; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_CLK_DIS; + writel(val, ctl_addr); + + val |=3D PWR_RTFF_SAVE_FLAG; + writel(val, ctl_addr); + } else if (MTK_SCPD_CAPS(scpd, MTK_SCPD_UFS_RTFF)) { + val |=3D PWR_RTFF_UFS_CLK_DIS; + writel(val, ctl_addr); + + val |=3D PWR_RTFF_SAVE; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_SAVE; + writel(val, ctl_addr); + + val &=3D ~PWR_RTFF_UFS_CLK_DIS; + writel(val, ctl_addr); + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_UFS_RTFF)) + scpd->rtff_flag =3D true; + } + val |=3D PWR_ISO_BIT; writel(val, ctl_addr); =20 + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_RTFF_DELAY) && scpd->rtff_flag) + udelay(1); + val &=3D ~PWR_RST_B_BIT; writel(val, ctl_addr); =20 --=20 2.45.2 From nobody Mon Feb 9 03:52:09 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 735D117DFF3; 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charset="utf-8" Support power domain is irq safe with MTK_SCPD_IRQ_SAFE. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 0ae4c617b5a6..467c54e24bea 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -42,6 +42,7 @@ #define MTK_SCPD_PEXTP_PHY_RTFF BIT(8) #define MTK_SCPD_UFS_RTFF BIT(9) #define MTK_SCPD_RTFF_DELAY BIT(10) +#define MTK_SCPD_IRQ_SAFE BIT(11) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -897,6 +898,8 @@ static struct scp *init_scp(struct platform_device *pde= v, } if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ACTIVE_WAKEUP)) genpd->flags |=3D GENPD_FLAG_ACTIVE_WAKEUP; + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_IRQ_SAFE)) + genpd->flags |=3D GENPD_FLAG_IRQ_SAFE; } =20 return scp; --=20 2.45.2 From nobody Mon Feb 9 03:52:09 2026 Received: from mailgw02.mediatek.com (unknown [210.61.82.184]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0F6A2DF59; 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charset="utf-8" Support power domain always on with MTK_SCPD_ALWAYS_ON. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 467c54e24bea..f0a5e1653b5f 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -43,6 +43,7 @@ #define MTK_SCPD_UFS_RTFF BIT(9) #define MTK_SCPD_RTFF_DELAY BIT(10) #define MTK_SCPD_IRQ_SAFE BIT(11) +#define MTK_SCPD_ALWAYS_ON BIT(12) #define MTK_SCPD_CAPS(_scpd, _x) ((_scpd)->data->caps & (_x)) =20 #define SPM_VDE_PWR_CON 0x0210 @@ -900,6 +901,8 @@ static struct scp *init_scp(struct platform_device *pde= v, genpd->flags |=3D GENPD_FLAG_ACTIVE_WAKEUP; if (MTK_SCPD_CAPS(scpd, MTK_SCPD_IRQ_SAFE)) genpd->flags |=3D GENPD_FLAG_IRQ_SAFE; + if (MTK_SCPD_CAPS(scpd, MTK_SCPD_ALWAYS_ON)) + genpd->flags |=3D GENPD_FLAG_ALWAYS_ON; } =20 return scp; --=20 2.45.2 From nobody Mon Feb 9 03:52:09 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D49E71A314E; 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charset="utf-8" Refactor parameters of init_scp which will use other fields of soc data. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 28 +++++++++++--------------- 1 file changed, 12 insertions(+), 16 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index f0a5e1653b5f..47d5d5abcaee 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -798,10 +798,7 @@ static int mtk_pd_get_regmap(struct platform_device *p= dev, struct regmap **regma return 0; } =20 -static struct scp *init_scp(struct platform_device *pdev, - const struct scp_domain_data *scp_domain_data, int num, - const struct scp_ctrl_reg *scp_ctrl_reg, - bool bus_prot_reg_update) +static struct scp *init_scp(struct platform_device *pdev, const struct scp= _soc_data *soc) { struct genpd_onecell_data *pd_data; int i, j; @@ -813,10 +810,10 @@ static struct scp *init_scp(struct platform_device *p= dev, if (!scp) return ERR_PTR(-ENOMEM); =20 - scp->ctrl_reg.pwr_sta_offs =3D scp_ctrl_reg->pwr_sta_offs; - scp->ctrl_reg.pwr_sta2nd_offs =3D scp_ctrl_reg->pwr_sta2nd_offs; + scp->ctrl_reg.pwr_sta_offs =3D soc->regs.pwr_sta_offs; + scp->ctrl_reg.pwr_sta2nd_offs =3D soc->regs.pwr_sta2nd_offs; =20 - scp->bus_prot_reg_update =3D bus_prot_reg_update; + scp->bus_prot_reg_update =3D soc->bus_prot_reg_update; =20 scp->dev =3D &pdev->dev; =20 @@ -825,14 +822,14 @@ static struct scp *init_scp(struct platform_device *p= dev, return ERR_CAST(scp->base); =20 scp->domains =3D devm_kcalloc(&pdev->dev, - num, sizeof(*scp->domains), GFP_KERNEL); + soc->num_domains, sizeof(*scp->domains), GFP_KERNEL); if (!scp->domains) return ERR_PTR(-ENOMEM); =20 pd_data =3D &scp->pd_data; =20 pd_data->domains =3D devm_kcalloc(&pdev->dev, - num, sizeof(*pd_data->domains), GFP_KERNEL); + soc->num_domains, sizeof(*pd_data->domains), GFP_KERNEL); if (!pd_data->domains) return ERR_PTR(-ENOMEM); =20 @@ -844,9 +841,9 @@ static struct scp *init_scp(struct platform_device *pde= v, return ERR_CAST(scp->infracfg); } =20 - for (i =3D 0; i < num; i++) { + for (i =3D 0; i < soc->num_domains; i++) { struct scp_domain *scpd =3D &scp->domains[i]; - const struct scp_domain_data *data =3D &scp_domain_data[i]; + const struct scp_domain_data *data =3D &soc->domains[i]; =20 scpd->supply =3D devm_regulator_get_optional(&pdev->dev, data->name); if (IS_ERR(scpd->supply)) { @@ -857,14 +854,14 @@ static struct scp *init_scp(struct platform_device *p= dev, } } =20 - pd_data->num_domains =3D num; + pd_data->num_domains =3D soc->num_domains; =20 init_clks(pdev, clk); =20 - for (i =3D 0; i < num; i++) { + for (i =3D 0; i < soc->num_domains; i++) { struct scp_domain *scpd =3D &scp->domains[i]; struct generic_pm_domain *genpd =3D &scpd->genpd; - const struct scp_domain_data *data =3D &scp_domain_data[i]; + const struct scp_domain_data *data =3D &soc->domains[i]; =20 pd_data->domains[i] =3D genpd; scpd->scp =3D scp; @@ -1511,8 +1508,7 @@ static int scpsys_probe(struct platform_device *pdev) =20 soc =3D of_device_get_match_data(&pdev->dev); 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charset="utf-8" Support bus protect with table which can contain multiple items. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 179 ++++++++++++++++++++++++- 1 file changed, 173 insertions(+), 6 deletions(-) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 47d5d5abcaee..c10756fa1685 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -31,6 +31,8 @@ #define MTK_RTFF_DELAY_US 10 #define MTK_STABLE_DELAY_US 100 =20 +#define MTK_BUS_PROTECTION_RETY_TIMES 10 + #define MTK_SCPD_ACTIVE_WAKEUP BIT(0) #define MTK_SCPD_FWAIT_SRAM BIT(1) #define MTK_SCPD_SRAM_ISO BIT(2) @@ -106,6 +108,24 @@ #define PWR_STATUS_HIF1 BIT(26) /* MT7622 */ #define PWR_STATUS_WB BIT(27) /* MT7622 */ =20 +#define _BUS_PROT(_type, _set_ofs, _clr_ofs, \ + _en_ofs, _sta_ofs, _mask, _ack_mask, \ + _ignore_clr_ack) { \ + .type =3D _type, \ + .set_ofs =3D _set_ofs, \ + .clr_ofs =3D _clr_ofs, \ + .en_ofs =3D _en_ofs, \ + .sta_ofs =3D _sta_ofs, \ + .mask =3D _mask, \ + .ack_mask =3D _ack_mask, \ + .ignore_clr_ack =3D _ignore_clr_ack, \ + } + +#define BUS_PROT_IGN(_type, _set_ofs, _clr_ofs, \ + _en_ofs, _sta_ofs, _mask) \ + _BUS_PROT(_type, _set_ofs, _clr_ofs, \ + _en_ofs, _sta_ofs, _mask, _mask, true) + enum clk_id { CLK_NONE, CLK_MM, @@ -135,6 +155,18 @@ static const char * const clk_names[] =3D { }; =20 #define MAX_CLKS 3 +#define MAX_STEPS 3 + +struct bus_prot { + u32 type; + u32 set_ofs; + u32 clr_ofs; + u32 en_ofs; + u32 sta_ofs; + u32 mask; + u32 ack_mask; + bool ignore_clr_ack; +}; =20 /** * struct scp_domain_data - scp domain data for power on/off flow @@ -157,6 +189,7 @@ static const char * const clk_names[] =3D { * @sram_slp_ack_bits: The mask for sram low power control acked bits. * @bus_prot_mask: The mask for single step bus protection. * @clk_id: The basic clocks required by this power domain. + * @bp_table: The bus protect configs for the power domain. * @caps: The flag for active wake-up action. */ struct scp_domain_data { @@ -179,6 +212,7 @@ struct scp_domain_data { u32 sram_slp_ack_bits; u32 bus_prot_mask; enum clk_id clk_id[MAX_CLKS]; + struct bus_prot bp_table[MAX_STEPS]; u32 caps; }; =20 @@ -207,6 +241,8 @@ struct scp { struct regmap *infracfg; struct scp_ctrl_reg ctrl_reg; bool bus_prot_reg_update; + struct regmap **bp_regmap; + int num_bp; }; =20 struct scp_subdomain { @@ -221,6 +257,8 @@ struct scp_soc_data { int num_subdomains; const struct scp_ctrl_reg regs; bool bus_prot_reg_update; + const char **bp_list; + int num_bp; }; =20 static int scpsys_domain_is_on(struct scp_domain *scpd) @@ -375,10 +413,121 @@ static int scpsys_sram_disable(struct scp_domain *sc= pd, void __iomem *ctl_addr) MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); } =20 +static int set_bus_protection(struct regmap *map, struct bus_prot *bp) +{ + u32 val =3D 0; + int retry =3D 0; + int ret =3D 0; + + while (retry <=3D MTK_BUS_PROTECTION_RETY_TIMES) { + if (bp->set_ofs) + regmap_write(map, bp->set_ofs, bp->mask); + else + regmap_update_bits(map, bp->en_ofs, bp->mask, bp->mask); + + /* check bus protect enable setting */ + regmap_read(map, bp->en_ofs, &val); + if ((val & bp->mask) =3D=3D bp->mask) + break; + + retry++; + } + + ret =3D regmap_read_poll_timeout_atomic(map, bp->sta_ofs, val, + (val & bp->ack_mask) =3D=3D bp->ack_mask, + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) { + pr_err("%s val=3D0x%x, mask=3D0x%x, (val & mask)=3D0x%x\n", + __func__, val, bp->ack_mask, (val & bp->ack_mask)); + } + + return ret; +} + +static int clear_bus_protection(struct regmap *map, struct bus_prot *bp) +{ + u32 val =3D 0; + int ret =3D 0; + + if (bp->clr_ofs) + regmap_write(map, bp->clr_ofs, bp->mask); + else + regmap_update_bits(map, bp->en_ofs, bp->mask, 0); + + if (bp->ignore_clr_ack) + return 0; + + ret =3D regmap_read_poll_timeout_atomic(map, bp->sta_ofs, val, + !(val & bp->ack_mask), + MTK_POLL_DELAY_US, MTK_POLL_TIMEOUT); + if (ret < 0) { + pr_err("%s val=3D0x%x, mask=3D0x%x, (val & mask)=3D0x%x\n", + __func__, val, bp->ack_mask, (val & bp->ack_mask)); + } + return ret; +} + +static int scpsys_bus_protect_table_disable(struct scp_domain *scpd, unsig= ned int index) +{ + struct scp *scp =3D scpd->scp; + const struct bus_prot *bp_table =3D scpd->data->bp_table; + int ret =3D 0; + int i; + + for (i =3D index; i >=3D 0; i--) { + struct regmap *map; + struct bus_prot bp =3D bp_table[i]; + + if (bp.type =3D=3D 0 || bp.type >=3D scp->num_bp) + continue; + + map =3D scp->bp_regmap[bp.type]; + if (!map) + continue; + + ret =3D clear_bus_protection(map, &bp); + if (ret) + break; + } + + return ret; +} + +static int scpsys_bus_protect_table_enable(struct scp_domain *scpd) +{ + struct scp *scp =3D scpd->scp; + const struct bus_prot *bp_table =3D scpd->data->bp_table; + int ret =3D 0; + int i; + + for (i =3D 0; i < MAX_STEPS; i++) { + struct regmap *map; + struct bus_prot bp =3D bp_table[i]; + + if (bp.type =3D=3D 0 || bp.type >=3D scp->num_bp) + continue; + + map =3D scp->bp_regmap[bp.type]; + if (!map) + continue; + + ret =3D set_bus_protection(map, &bp); + if (ret) { + scpsys_bus_protect_table_disable(scpd, i); + return ret; + } + } + + return ret; +} + static int scpsys_bus_protect_enable(struct scp_domain *scpd) { struct scp *scp =3D scpd->scp; =20 + if (scp->bp_regmap && scp->num_bp > 0) + return scpsys_bus_protect_table_enable(scpd); + if (!scpd->data->bus_prot_mask) return 0; =20 @@ -391,6 +540,9 @@ static int scpsys_bus_protect_disable(struct scp_domain= *scpd) { struct scp *scp =3D scpd->scp; =20 + if (scp->bp_regmap && scp->num_bp > 0) + return scpsys_bus_protect_table_disable(scpd, MAX_STEPS - 1); + if (!scpd->data->bus_prot_mask) return 0; =20 @@ -833,12 +985,27 @@ static struct scp *init_scp(struct platform_device *p= dev, const struct scp_soc_d if (!pd_data->domains) return ERR_PTR(-ENOMEM); =20 - scp->infracfg =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_node, - "infracfg"); - if (IS_ERR(scp->infracfg)) { - dev_err(&pdev->dev, "Cannot find infracfg controller: %ld\n", - PTR_ERR(scp->infracfg)); - return ERR_CAST(scp->infracfg); + if (soc->bp_list && soc->num_bp > 0) { + scp->num_bp =3D soc->num_bp; + scp->bp_regmap =3D devm_kcalloc(&pdev->dev, scp->num_bp, + sizeof(*scp->bp_regmap), GFP_KERNEL); + if (!scp->bp_regmap) + return ERR_PTR(-ENOMEM); + + /* get bus prot regmap from dts node, 0 means invalid bus type */ + for (i =3D 1; i < scp->num_bp; i++) { + ret =3D mtk_pd_get_regmap(pdev, &scp->bp_regmap[i], soc->bp_list[i]); + if (ret) + return ERR_PTR(ret); + } + } else { + scp->infracfg =3D syscon_regmap_lookup_by_phandle(pdev->dev.of_node, + "infracfg"); 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charset="utf-8" Add post init callback. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mtk-scpsys.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index c10756fa1685..7bfe36c1a1ae 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -250,6 +250,9 @@ struct scp_subdomain { int subdomain; }; =20 +typedef int (*scp_soc_post_probe_fn)(struct platform_device *pdev, + struct scp *scp); + struct scp_soc_data { const struct scp_domain_data *domains; int num_domains; @@ -259,6 +262,7 @@ struct scp_soc_data { bool bus_prot_reg_update; const char **bp_list; int num_bp; + scp_soc_post_probe_fn post_probe; }; =20 static int scpsys_domain_is_on(struct scp_domain *scpd) @@ -1691,6 +1695,12 @@ static int scpsys_probe(struct platform_device *pdev) ret); } =20 + if (soc->post_probe) { + ret =3D soc->post_probe(pdev, scp); + if (ret) + return ret; + } + return 0; } =20 --=20 2.45.2 From nobody Mon Feb 9 03:52:09 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id ADD031C84B1; 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charset="utf-8" Add the binding documentation for power domain on MediaTek MT8196. Signed-off-by: Guangjie Song --- .../mediatek,mt8196-power-controller.yaml | 74 +++++++++++++++++++ include/dt-bindings/power/mt8196-power.h | 57 ++++++++++++++ 2 files changed, 131 insertions(+) create mode 100644 Documentation/devicetree/bindings/power/mediatek,mt8196= -power-controller.yaml create mode 100644 include/dt-bindings/power/mt8196-power.h diff --git a/Documentation/devicetree/bindings/power/mediatek,mt8196-power-= controller.yaml b/Documentation/devicetree/bindings/power/mediatek,mt8196-p= ower-controller.yaml new file mode 100644 index 000000000000..6c2867b25967 --- /dev/null +++ b/Documentation/devicetree/bindings/power/mediatek,mt8196-power-control= ler.yaml @@ -0,0 +1,74 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/power/mediatek,mt8196-power-controller.= yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT8196 Power Domains Controller + +maintainers: + - Guangjie Song + +description: | + Mediatek processors include support for multiple power domains which can= be + powered up/down by software based on different application scenes to sav= e power. + +properties: + $nodename: + pattern: '^power-controller(@[0-9a-f]+)?$' + + compatible: + enum: + - mediatek,mt8196-scpsys + - mediatek,mt8196-hfrpsys + + '#power-domain-cells': + const: 1 + + reg: + description: Address range of the power controller. + + clocks: + description: | + A number of phandles to clocks that need to be enabled during domain + power-up sequencing. + + clock-names: + description: | + List of names of clock. + + domain-supply: + description: domain regulator supply. + + spm: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the spm register range. + + mmpc: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the mmpc register range. + + vote-regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the vote register range. + + mm-vote-regmap: + $ref: /schemas/types.yaml#/definitions/phandle + description: phandle to the device containing the mm-vote register ran= ge. + +required: + - compatible + +additionalProperties: false + +examples: + - | + #include + + scpsys: power-controller@1c004000 { + compatible =3D "mediatek,mt8196-scpsys", "syscon"; + reg =3D <0 0x1c004000 0 0x1000>; + #power-domain-cells =3D <1>; + spm =3D <&scpsys_bus>; + vote-regmap =3D <&vote>; + }; diff --git a/include/dt-bindings/power/mt8196-power.h b/include/dt-bindings= /power/mt8196-power.h new file mode 100644 index 000000000000..b0db89cc435d --- /dev/null +++ b/include/dt-bindings/power/mt8196-power.h @@ -0,0 +1,57 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause */ +/* + * Copyright (c) 2023 MediaTek Inc. + * Author: Chong-ming Wei + */ + +#ifndef _DT_BINDINGS_POWER_MT8196_POWER_H +#define _DT_BINDINGS_POWER_MT8196_POWER_H + +/* SPM */ +#define MT8196_POWER_DOMAIN_CONN 0 +#define MT8196_POWER_DOMAIN_SSUSB_P0 1 +#define MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0 2 +#define MT8196_POWER_DOMAIN_SSUSB_P1 3 +#define MT8196_POWER_DOMAIN_SSUSB_P23 4 +#define MT8196_POWER_DOMAIN_SSUSB_PHY_P2 5 +#define MT8196_POWER_DOMAIN_PEXTP_MAC0 6 +#define MT8196_POWER_DOMAIN_PEXTP_MAC1 7 +#define MT8196_POWER_DOMAIN_PEXTP_MAC2 8 +#define MT8196_POWER_DOMAIN_PEXTP_PHY0 9 +#define MT8196_POWER_DOMAIN_PEXTP_PHY1 10 +#define MT8196_POWER_DOMAIN_PEXTP_PHY2 11 +#define MT8196_POWER_DOMAIN_ADSP_AO 12 +#define MT8196_POWER_DOMAIN_ADSP_INFRA 13 +#define MT8196_POWER_DOMAIN_AUDIO 14 +#define MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT 15 +#define MT8196_POWER_DOMAIN_MM_PROC_DORMANT 16 +#define MT8196_POWER_DOMAIN_SSR 17 +#define MT8196_SPM_POWER_DOMAIN_NR 18 + +/* MMPC */ +#define MT8196_POWER_DOMAIN_MM_INFRA_AO 0 +#define MT8196_POWER_DOMAIN_MM_INFRA0 1 +#define MT8196_POWER_DOMAIN_MM_INFRA1 2 +#define MT8196_POWER_DOMAIN_VDE_VCORE0 3 +#define MT8196_POWER_DOMAIN_VDE0 4 +#define MT8196_POWER_DOMAIN_VDE1 5 +#define MT8196_POWER_DOMAIN_VEN0 6 +#define MT8196_POWER_DOMAIN_VEN1 7 +#define MT8196_POWER_DOMAIN_VEN2 8 +#define MT8196_POWER_DOMAIN_DISP_VCORE 9 +#define MT8196_POWER_DOMAIN_DIS0_DORMANT 10 +#define MT8196_POWER_DOMAIN_DIS1_DORMANT 11 +#define MT8196_POWER_DOMAIN_OVL0_DORMANT 12 +#define MT8196_POWER_DOMAIN_OVL1_DORMANT 13 +#define MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT 14 +#define MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT 15 +#define MT8196_POWER_DOMAIN_MML0_SHUTDOWN 16 +#define MT8196_POWER_DOMAIN_MML1_SHUTDOWN 17 +#define MT8196_POWER_DOMAIN_CSI_BS_RX 18 +#define MT8196_POWER_DOMAIN_CSI_LS_RX 19 +#define MT8196_POWER_DOMAIN_DSI_PHY0 20 +#define MT8196_POWER_DOMAIN_DSI_PHY1 21 +#define MT8196_POWER_DOMAIN_DSI_PHY2 22 +#define MT8196_MMPC_POWER_DOMAIN_NR 23 + +#endif /* _DT_BINDINGS_POWER_MT8196_POWER_H */ --=20 2.45.2 From nobody Mon Feb 9 03:52:09 2026 Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3E9421A841E; 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Fri, 07 Mar 2025 11:45:09 +0800 Received: from mtkmbs11n1.mediatek.inc (172.21.101.185) by mtkmbs10n2.mediatek.inc (172.21.101.183) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1258.28; Fri, 7 Mar 2025 11:45:07 +0800 Received: from mhfsdcap04.gcn.mediatek.inc (10.17.3.154) by mtkmbs11n1.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.2.1258.28 via Frontend Transport; Fri, 7 Mar 2025 11:45:07 +0800 From: Guangjie Song To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Matthias Brugger , AngeloGioacchino Del Regno , Ulf Hansson CC: , , , , , Guangjie Song , Subject: [PATCH 13/13] pmdomain: mediatek: Add MT8196 power domain support Date: Fri, 7 Mar 2025 11:44:37 +0800 Message-ID: <20250307034454.12243-14-guangjie.song@mediatek.com> X-Mailer: git-send-email 2.46.0 In-Reply-To: <20250307034454.12243-1-guangjie.song@mediatek.com> References: <20250307034454.12243-1-guangjie.song@mediatek.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add power domain support for MT8196. Signed-off-by: Guangjie Song --- drivers/pmdomain/mediatek/mt8196-scpsys.h | 114 ++++ drivers/pmdomain/mediatek/mtk-scpsys.c | 629 ++++++++++++++++++++++ 2 files changed, 743 insertions(+) create mode 100644 drivers/pmdomain/mediatek/mt8196-scpsys.h diff --git a/drivers/pmdomain/mediatek/mt8196-scpsys.h b/drivers/pmdomain/m= ediatek/mt8196-scpsys.h new file mode 100644 index 000000000000..07cb08eaa920 --- /dev/null +++ b/drivers/pmdomain/mediatek/mt8196-scpsys.h @@ -0,0 +1,114 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (c) 2024 MediaTek Inc. + * Author: Guangjie Song + */ +#ifndef __PMDOMAIN_MEDIATEK_MT8196_SCPSYS_H +#define __PMDOMAIN_MEDIATEK_MT8196_SCPSYS_H + +#define MT8196_SPM_CONN_PWR_CON 0xe04 +#define MT8196_SPM_SSUSB_DP_PHY_P0_PWR_CON 0xe18 +#define MT8196_SPM_SSUSB_P0_PWR_CON 0xe1c +#define MT8196_SPM_SSUSB_P1_PWR_CON 0xe20 +#define MT8196_SPM_SSUSB_P23_PWR_CON 0xe24 +#define MT8196_SPM_SSUSB_PHY_P2_PWR_CON 0xe28 +#define MT8196_SPM_PEXTP_MAC0_PWR_CON 0xe34 +#define MT8196_SPM_PEXTP_MAC1_PWR_CON 0xe38 +#define MT8196_SPM_PEXTP_MAC2_PWR_CON 0xe3c +#define MT8196_SPM_PEXTP_PHY0_PWR_CON 0xe40 +#define MT8196_SPM_PEXTP_PHY1_PWR_CON 0xe44 +#define MT8196_SPM_PEXTP_PHY2_PWR_CON 0xe48 +#define MT8196_SPM_AUDIO_PWR_CON 0xe4c +#define MT8196_SPM_ADSP_TOP_PWR_CON 0xe54 +#define MT8196_SPM_ADSP_INFRA_PWR_CON 0xe58 +#define MT8196_SPM_ADSP_AO_PWR_CON 0xe5c +#define MT8196_SPM_PWR_STATUS 0xf14 +#define MT8196_SPM_PWR_STATUS_2ND 0xf18 + +#define MT8196_SPM_BUS_PROTECT_EN 0xd8 +#define MT8196_SPM_BUS_PROTECT_EN_SET 0xdc +#define MT8196_SPM_BUS_PROTECT_EN_CLR 0xe0 +#define MT8196_SPM_BUS_PROTECT_RDY 0x208 + +#define MT8196_MM_PWR_STATUS 0x100 +#define MT8196_MM_PWR_STATUS_2ND 0x104 + +#define MT8196_VOTE_MTCMOS_SET0 0x218 +#define MT8196_VOTE_MTCMOS_CLR0 0x21c +#define MT8196_VOTE_MTCMOS_ENABLE0 0x1410 +#define MT8196_VOTE_MTCMOS_DONE0 0x141c +#define MT8196_VOTE_MTCMOS_SET_STATUS0 0x146c +#define MT8196_VOTE_MTCMOS_CLR_STATUS0 0x1470 + +#define MT8196_MM_VOTE_MTCMOS_SET0 0x218 +#define MT8196_MM_VOTE_MTCMOS_CLR0 0x21c +#define MT8196_MM_VOTE_MTCMOS_SET1 0x220 +#define MT8196_MM_VOTE_MTCMOS_CLR1 0x224 +#define MT8196_MM_VOTE_MTCMOS_ENABLE0 0x1410 +#define MT8196_MM_VOTE_MTCMOS_DONE0 0x141c +#define MT8196_MM_VOTE_MTCMOS_ENABLE1 0x1420 +#define MT8196_MM_VOTE_MTCMOS_DONE1 0x142c +#define MT8196_MM_VOTE_MTCMOS_SET_STATUS0 0x146c +#define MT8196_MM_VOTE_MTCMOS_CLR_STATUS0 0x1470 +#define MT8196_MM_VOTE_MTCMOS_SET_STATUS1 0x1474 +#define MT8196_MM_VOTE_MTCMOS_CLR_STATUS1 0x1478 +#define MT8196_MM_VOTE_MTCMOS_PM_ACK0 0x5514 +#define MT8196_MM_VOTE_MTCMOS_PM_ACK1 0x5518 + +#define MT8196_SPM_PROT_EN_BUS_CONN BIT(1) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0 BIT(6) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_P0 BIT(7) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_P1 BIT(8) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_P23 BIT(9) +#define MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2 BIT(10) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0 BIT(13) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1 BIT(14) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2 BIT(15) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0 BIT(16) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1 BIT(17) +#define MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2 BIT(18) +#define MT8196_SPM_PROT_EN_BUS_AUDIO BIT(19) +#define MT8196_SPM_PROT_EN_BUS_ADSP_TOP BIT(21) +#define MT8196_SPM_PROT_EN_BUS_ADSP_INFRA BIT(22) +#define MT8196_SPM_PROT_EN_BUS_ADSP_AO BIT(23) + +#define MT8196_VOTE_MM_PROC_SHIFT 0 +#define MT8196_VOTE_SSR_SHIFT 1 + +#define MT8196_MM_VOTE_VDE0_SHIFT 7 +#define MT8196_MM_VOTE_VDE1_SHIFT 8 +#define MT8196_MM_VOTE_VDE_VCORE0_SHIFT 9 +#define MT8196_MM_VOTE_VEN0_SHIFT 10 +#define MT8196_MM_VOTE_VEN1_SHIFT 11 +#define MT8196_MM_VOTE_VEN2_SHIFT 12 +#define MT8196_MM_VOTE_DISP_VCORE_SHIFT 24 +#define MT8196_MM_VOTE_DIS0_SHIFT 25 +#define MT8196_MM_VOTE_DIS1_SHIFT 26 +#define MT8196_MM_VOTE_OVL0_SHIFT 27 +#define MT8196_MM_VOTE_OVL1_SHIFT 28 +#define MT8196_MM_VOTE_DISP_EDPTX_SHIFT 29 +#define MT8196_MM_VOTE_DISP_DPTX_SHIFT 30 +#define MT8196_MM_VOTE_MML0_SHIFT 31 +#define MT8196_MM_VOTE_MML1_SHIFT 0 +#define MT8196_MM_VOTE_MM_INFRA0_SHIFT 1 +#define MT8196_MM_VOTE_MM_INFRA1_SHIFT 2 +#define MT8196_MM_VOTE_MM_INFRA_AO_SHIFT 3 +#define MT8196_MM_VOTE_CSI_BS_RX_SHIFT 5 +#define MT8196_MM_VOTE_CSI_LS_RX_SHIFT 6 +#define MT8196_MM_VOTE_DSI_PHY0_SHIFT 7 +#define MT8196_MM_VOTE_DSI_PHY1_SHIFT 8 +#define MT8196_MM_VOTE_DSI_PHY2_SHIFT 9 + +enum { + MT8196_SPM_BP_INVALID =3D 0, + MT8196_SPM_BP_SPM, + MT8196_SPM_BP_NR +}; + +enum { + MT8196_MMPC_BP_INVALID =3D 0, + MT8196_MMPC_BP_MMPC, + MT8196_MMPC_BP_NR, +}; + +#endif /* __PMDOMAIN_MEDIATEK_MT8196_SCPSYS_H */ diff --git a/drivers/pmdomain/mediatek/mtk-scpsys.c b/drivers/pmdomain/medi= atek/mtk-scpsys.c index 7bfe36c1a1ae..667e69ada125 100644 --- a/drivers/pmdomain/mediatek/mtk-scpsys.c +++ b/drivers/pmdomain/mediatek/mtk-scpsys.c @@ -20,6 +20,9 @@ #include #include #include +#include + +#include "mt8196-scpsys.h" =20 #define MTK_POLL_DELAY_US 10 #define MTK_POLL_TIMEOUT USEC_PER_SEC @@ -137,6 +140,8 @@ enum clk_id { CLK_HIFSEL, CLK_JPGDEC, CLK_AUDIO, + CLK_DISP_AO_CONFIG, + CLK_DISP_DPC, CLK_MAX, }; =20 @@ -151,6 +156,8 @@ static const char * const clk_names[] =3D { "hif_sel", "jpgdec", "audio", + "disp_ao_config", + "disp_dpc", NULL, }; =20 @@ -1575,6 +1582,594 @@ static const struct scp_subdomain scp_subdomain_mt8= 173[] =3D { {MT8173_POWER_DOMAIN_MFG_2D, MT8173_POWER_DOMAIN_MFG}, }; =20 +/* + * MT8196 power domain support + */ +static const char *mt8196_spm_bp_list[MT8196_SPM_BP_NR] =3D { + [MT8196_SPM_BP_SPM] =3D "spm", +}; + +static const struct scp_domain_data scp_domain_mt8196_spm_vote_data[] =3D { + [MT8196_POWER_DOMAIN_CONN] =3D { + .name =3D "conn", + .ctl_offs =3D MT8196_SPM_CONN_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_CONN), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_BYPA= SS_INIT_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0] =3D { + .name =3D "ssusb-dp-phy-p0", + .ctl_offs =3D MT8196_SPM_SSUSB_DP_PHY_P0_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, + MT8196_SPM_PROT_EN_BUS_SSUSB_DP_PHY_P0), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_P0] =3D { + .name =3D "ssusb-p0", + .ctl_offs =3D MT8196_SPM_SSUSB_P0_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_SSUSB_P0), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_P1] =3D { + .name =3D "ssusb-p1", + .ctl_offs =3D MT8196_SPM_SSUSB_P1_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_SSUSB_P1), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_P23] =3D { + .name =3D "ssusb-p23", + .ctl_offs =3D MT8196_SPM_SSUSB_P23_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_SSUSB_P23), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_BYPA= SS_INIT_ON, + }, + [MT8196_POWER_DOMAIN_SSUSB_PHY_P2] =3D { + .name =3D "ssusb-phy-p2", + .ctl_offs =3D MT8196_SPM_SSUSB_PHY_P2_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, + MT8196_SPM_PROT_EN_BUS_SSUSB_PHY_P2), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_BYPA= SS_INIT_ON, + }, + [MT8196_POWER_DOMAIN_PEXTP_MAC0] =3D { + .name =3D "pextp-mac0", + .ctl_offs =3D MT8196_SPM_PEXTP_MAC0_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC0), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_MAC1] =3D { + .name =3D "pextp-mac1", + .ctl_offs =3D MT8196_SPM_PEXTP_MAC1_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC1), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_MAC2] =3D { + .name =3D "pextp-mac2", + .ctl_offs =3D MT8196_SPM_PEXTP_MAC2_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_MAC2), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_PHY0] =3D { + .name =3D "pextp-phy0", + .ctl_offs =3D MT8196_SPM_PEXTP_PHY0_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY0), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_PHY1] =3D { + .name =3D "pextp-phy1", + .ctl_offs =3D MT8196_SPM_PEXTP_PHY1_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY1), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_PEXTP_PHY2] =3D { + .name =3D "pextp-phy2", + .ctl_offs =3D MT8196_SPM_PEXTP_PHY2_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_PEXTP_PHY2), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_PEXTP_PHY_RTFF | MTK_SCPD_RT= FF_DELAY, + }, + [MT8196_POWER_DOMAIN_AUDIO] =3D { + .name =3D "audio", + .ctl_offs =3D MT8196_SPM_AUDIO_PWR_CON, + .sram_pdn_bits =3D GENMASK(8, 8), + .sram_pdn_ack_bits =3D GENMASK(12, 12), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_AUDIO), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF, + }, + [MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT] =3D { + .name =3D "adsp-top-dormant", + .ctl_offs =3D MT8196_SPM_ADSP_TOP_PWR_CON, + .sram_slp_bits =3D GENMASK(9, 9), + .sram_slp_ack_bits =3D GENMASK(13, 13), + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_ADSP_TOP), + }, + .caps =3D MTK_SCPD_SRAM_ISO | MTK_SCPD_SRAM_SLP | MTK_SCPD_IS_PWR_CON_ON, + }, + [MT8196_POWER_DOMAIN_ADSP_INFRA] =3D { + .name =3D "adsp-infra", + .ctl_offs =3D MT8196_SPM_ADSP_INFRA_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_ADSP_INFRA), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_ADSP_AO] =3D { + .name =3D "adsp-ao", + .ctl_offs =3D MT8196_SPM_ADSP_AO_PWR_CON, + .bp_table =3D { + BUS_PROT_IGN(MT8196_SPM_BP_SPM, MT8196_SPM_BUS_PROTECT_EN_SET, + MT8196_SPM_BUS_PROTECT_EN_CLR, MT8196_SPM_BUS_PROTECT_EN, + MT8196_SPM_BUS_PROTECT_RDY, MT8196_SPM_PROT_EN_BUS_ADSP_AO), + }, + .caps =3D MTK_SCPD_IS_PWR_CON_ON | MTK_SCPD_NON_CPU_RTFF | MTK_SCPD_ALWA= YS_ON, + }, + [MT8196_POWER_DOMAIN_MM_PROC_DORMANT] =3D { + .name =3D "mm-proc-dormant", + .vote_comp =3D "vote-regmap", + .vote_set_ofs =3D MT8196_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_VOTE_MTCMOS_ENABLE0, + .vote_set_sta_ofs =3D MT8196_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_VOTE_MTCMOS_CLR_STATUS0, + .vote_shift =3D MT8196_VOTE_MM_PROC_SHIFT, + /* TODO: drop MTK_SCPD_ALWAYS_ON after fixing suspend issue. */ + .caps =3D MTK_SCPD_VOTE_OPS | MTK_SCPD_IRQ_SAFE | MTK_SCPD_ALWAYS_ON, + }, + [MT8196_POWER_DOMAIN_SSR] =3D { + .name =3D "ssrsys", + .vote_comp =3D "vote-regmap", + .vote_set_ofs =3D MT8196_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_VOTE_MTCMOS_ENABLE0, + .vote_set_sta_ofs =3D MT8196_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_VOTE_MTCMOS_CLR_STATUS0, + .vote_shift =3D MT8196_VOTE_SSR_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8196_spm[] =3D { + {MT8196_POWER_DOMAIN_SSUSB_P0, MT8196_POWER_DOMAIN_SSUSB_DP_PHY_P0}, + {MT8196_POWER_DOMAIN_SSUSB_P23, MT8196_POWER_DOMAIN_SSUSB_PHY_P2}, + {MT8196_POWER_DOMAIN_PEXTP_MAC0, MT8196_POWER_DOMAIN_PEXTP_PHY0}, + {MT8196_POWER_DOMAIN_PEXTP_MAC1, MT8196_POWER_DOMAIN_PEXTP_PHY1}, + {MT8196_POWER_DOMAIN_PEXTP_MAC2, MT8196_POWER_DOMAIN_PEXTP_PHY2}, + {MT8196_POWER_DOMAIN_ADSP_INFRA, MT8196_POWER_DOMAIN_AUDIO}, + {MT8196_POWER_DOMAIN_ADSP_INFRA, MT8196_POWER_DOMAIN_ADSP_TOP_DORMANT}, + {MT8196_POWER_DOMAIN_ADSP_AO, MT8196_POWER_DOMAIN_ADSP_INFRA}, +}; + +static struct generic_pm_domain *mt8196_mm_proc_domain; + +static int mt8196_spm_post_probe(struct platform_device *pdev, struct scp = *scp) +{ + mt8196_mm_proc_domain =3D scp->pd_data.domains[MT8196_POWER_DOMAIN_MM_PRO= C_DORMANT]; + + return 0; +} + +static const char *mt8196_mmpc_bp_list[MT8196_MMPC_BP_NR] =3D { + [MT8196_MMPC_BP_MMPC] =3D "mmpc", +}; + +static const struct scp_domain_data scp_domain_mt8196_mmpc_vote_data[] =3D= { + [MT8196_POWER_DOMAIN_VDE0] =3D { + .name =3D "vde0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VDE0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VDE1] =3D { + .name =3D "vde1", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VDE1_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VDE_VCORE0] =3D { + .name =3D "vde-vcore0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VDE_VCORE0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VEN0] =3D { + .name =3D "ven0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VEN0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VEN1] =3D { + .name =3D "ven1", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VEN1_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_VEN2] =3D { + .name =3D "ven2", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_VEN2_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DISP_VCORE] =3D { + .name =3D "disp-vcore", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DISP_VCORE_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DIS0_DORMANT] =3D { + .name =3D "dis0-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DIS0_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DIS1_DORMANT] =3D { + .name =3D "dis1-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DIS1_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_OVL0_DORMANT] =3D { + .name =3D "ovl0-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_OVL0_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_OVL1_DORMANT] =3D { + .name =3D "ovl1-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_OVL1_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT] =3D { + .name =3D "disp-edptx-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DISP_EDPTX_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT] =3D { + .name =3D "disp-dptx-dormant", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_DISP_DPTX_SHIFT, + .clk_id =3D {CLK_DISP_AO_CONFIG, CLK_DISP_DPC}, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_MML0_SHUTDOWN] =3D { + .name =3D "mml0-shutdown", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET0, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE0, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR0, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS0, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS0, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK0, + .vote_shift =3D MT8196_MM_VOTE_MML0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_MML1_SHUTDOWN] =3D { + .name =3D "mml1-shutdown", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_MML0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_MM_INFRA0] =3D { + .name =3D "mm-infra0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_MM_INFRA0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS | MTK_SCPD_IRQ_SAFE, + }, + [MT8196_POWER_DOMAIN_MM_INFRA1] =3D { + .name =3D "mm-infra1", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_MM_INFRA1_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS | MTK_SCPD_IRQ_SAFE, + }, + [MT8196_POWER_DOMAIN_MM_INFRA_AO] =3D { + .name =3D "mm-infra-ao", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_MM_INFRA_AO_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS | MTK_SCPD_IRQ_SAFE, + }, + [MT8196_POWER_DOMAIN_CSI_BS_RX] =3D { + .name =3D "csi-bs-rx", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_CSI_BS_RX_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_CSI_LS_RX] =3D { + .name =3D "csi-ls-rx", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_CSI_LS_RX_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DSI_PHY0] =3D { + .name =3D "dsi-phy0", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_DSI_PHY0_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DSI_PHY1] =3D { + .name =3D "dsi-phy1", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_DSI_PHY1_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, + [MT8196_POWER_DOMAIN_DSI_PHY2] =3D { + .name =3D "dsi-phy2", + .vote_comp =3D "mm-vote-regmap", + .vote_set_ofs =3D MT8196_MM_VOTE_MTCMOS_SET1, + .vote_clr_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR1, + .vote_done_ofs =3D MT8196_MM_VOTE_MTCMOS_DONE1, + .vote_en_ofs =3D MT8196_MM_VOTE_MTCMOS_ENABLE1, + .vote_set_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_SET_STATUS1, + .vote_clr_sta_ofs =3D MT8196_MM_VOTE_MTCMOS_CLR_STATUS1, + .vote_ack_ofs =3D MT8196_MM_VOTE_MTCMOS_PM_ACK1, + .vote_shift =3D MT8196_MM_VOTE_DSI_PHY2_SHIFT, + .caps =3D MTK_SCPD_VOTE_OPS, + }, +}; + +static const struct scp_subdomain scp_subdomain_mt8196_mmpc[] =3D { + {MT8196_POWER_DOMAIN_VDE_VCORE0, MT8196_POWER_DOMAIN_VDE0}, + {MT8196_POWER_DOMAIN_VDE_VCORE0, MT8196_POWER_DOMAIN_VDE1}, + {MT8196_POWER_DOMAIN_VEN0, MT8196_POWER_DOMAIN_VEN1}, + {MT8196_POWER_DOMAIN_VEN1, MT8196_POWER_DOMAIN_VEN2}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_DIS0_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_DIS1_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_OVL0_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_OVL1_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_DISP_EDPTX_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_DISP_DPTX_DORMANT}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_MML0_SHUTDOWN}, + {MT8196_POWER_DOMAIN_DISP_VCORE, MT8196_POWER_DOMAIN_MML1_SHUTDOWN}, + {MT8196_POWER_DOMAIN_MM_INFRA1, MT8196_POWER_DOMAIN_DISP_VCORE}, + {MT8196_POWER_DOMAIN_MM_INFRA1, MT8196_POWER_DOMAIN_VDE_VCORE0}, + {MT8196_POWER_DOMAIN_MM_INFRA1, MT8196_POWER_DOMAIN_VEN0}, + {MT8196_POWER_DOMAIN_MM_INFRA0, MT8196_POWER_DOMAIN_MM_INFRA1}, + {MT8196_POWER_DOMAIN_MM_INFRA_AO, MT8196_POWER_DOMAIN_MM_INFRA0}, +}; + +static int mt8196_mmpc_post_probe(struct platform_device *pdev, struct scp= *scp) +{ + int ret, i; + int subdomain[] =3D { + MT8196_POWER_DOMAIN_MM_INFRA_AO, + MT8196_POWER_DOMAIN_CSI_BS_RX, + MT8196_POWER_DOMAIN_CSI_LS_RX, + MT8196_POWER_DOMAIN_DSI_PHY0, + MT8196_POWER_DOMAIN_DSI_PHY1, + MT8196_POWER_DOMAIN_DSI_PHY2 + }; + + for (i =3D 0; i < ARRAY_SIZE(subdomain); i++) { + ret =3D pm_genpd_add_subdomain(mt8196_mm_proc_domain, scp->pd_data.domai= ns[subdomain[i]]); + if (ret && IS_ENABLED(CONFIG_PM)) { + dev_err(&pdev->dev, "Failed to add subdomain: %d\n", ret); + return ret; + } + } + + return 0; +} + static const struct scp_soc_data mt2701_data =3D { .domains =3D scp_domain_data_mt2701, .num_domains =3D ARRAY_SIZE(scp_domain_data_mt2701), @@ -1641,6 +2236,34 @@ static const struct scp_soc_data mt8173_data =3D { .bus_prot_reg_update =3D true, }; =20 +static const struct scp_soc_data mt8196_spm_vote_data =3D { + .domains =3D scp_domain_mt8196_spm_vote_data, + .num_domains =3D MT8196_SPM_POWER_DOMAIN_NR, + .subdomains =3D scp_subdomain_mt8196_spm, + .num_subdomains =3D ARRAY_SIZE(scp_subdomain_mt8196_spm), + .regs =3D { + .pwr_sta_offs =3D MT8196_SPM_PWR_STATUS, + .pwr_sta2nd_offs =3D MT8196_SPM_PWR_STATUS_2ND, + }, + .bp_list =3D mt8196_spm_bp_list, + .num_bp =3D MT8196_SPM_BP_NR, + .post_probe =3D mt8196_spm_post_probe, +}; + +static const struct scp_soc_data mt8196_mmpc_vote_data =3D { + .domains =3D scp_domain_mt8196_mmpc_vote_data, + .num_domains =3D MT8196_MMPC_POWER_DOMAIN_NR, + .subdomains =3D scp_subdomain_mt8196_mmpc, + .num_subdomains =3D ARRAY_SIZE(scp_subdomain_mt8196_mmpc), + .regs =3D { + .pwr_sta_offs =3D MT8196_MM_PWR_STATUS, + .pwr_sta2nd_offs =3D MT8196_MM_PWR_STATUS_2ND, + }, + .bp_list =3D mt8196_mmpc_bp_list, + .num_bp =3D MT8196_MMPC_BP_NR, + .post_probe =3D mt8196_mmpc_post_probe, +}; + /* * scpsys driver init */ @@ -1664,6 +2287,12 @@ static const struct of_device_id of_scpsys_match_tbl= [] =3D { }, { .compatible =3D "mediatek,mt8173-scpsys", .data =3D &mt8173_data, + }, { + .compatible =3D "mediatek,mt8196-scpsys", + .data =3D &mt8196_spm_vote_data, + }, { + .compatible =3D "mediatek,mt8196-hfrpsys", + .data =3D &mt8196_mmpc_vote_data, }, { /* sentinel */ } --=20 2.45.2