From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id E353D85270; Fri, 7 Mar 2025 00:57:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309046; cv=none; b=P2crJEMZtT8iCEYiRff8YjbnDS7HaF43MqjJXPeGXHluZqq3whvBR/HZPNxIoOtZCBJARDxmp5d8Q24zrOJ++/owCbCsgvm2bpzGCTf3jpHN1Q0Fz1imUsmqlkknOIya53J6l9sUx6lTNJt1j6mhZXnbSKJ5CZX4UW51rdHgi9M= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309046; c=relaxed/simple; bh=ENbo0gM8IwufCgggenHF+D7xLihjMCy8hfoPc/5Tpz8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=YGc+JOsN/BCdCn9iRmjyfL0dWJBzwINaybw/E0UXwgbygLJRXVaXzswWXnFUmdTfsH6L4dG0CX5hIDzc77GHiEGrTfSOyyt2oqCEyzFKu0FE3BBdO6K7DGbgb0Z1Okt26cJjG1RjjJem4IIBYS87oZSoQ1MEgfKCBZjySBid+Ro= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 51E761BC0; Thu, 6 Mar 2025 16:57:37 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C3EB83F5A1; Thu, 6 Mar 2025 16:57:22 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Ulf Hansson Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Conor Dooley Subject: [PATCH v3 01/15] dt-bindings: mmc: sunxi: Simplify compatible string listing Date: Fri, 7 Mar 2025 00:56:58 +0000 Message-ID: <20250307005712.16828-2-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" New Allwinner SoCs only occasionally update their MMC IP, leading to many pairs of compatible strings, though there are sometimes a number of them being compatible with one particular SoC. Collate the compatible string listing in the binding, to group those being compatible together. This makes the list more readable, and allows for easier addition of new SoC's MMC devices. Signed-off-by: Andre Przywara Acked-by: Conor Dooley --- .../bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 36 ++++++++----------- 1 file changed, 14 insertions(+), 22 deletions(-) diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.= yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 0ccd632d56200..8e4c77b7e4ab9 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -30,38 +30,30 @@ properties: - const: allwinner,sun50i-a100-emmc - const: allwinner,sun50i-a100-mmc - items: - - const: allwinner,sun8i-a83t-mmc + - enum: + - allwinner,sun8i-a83t-mmc + - allwinner,suniv-f1c100s-mmc - const: allwinner,sun7i-a20-mmc - items: - - const: allwinner,sun8i-r40-emmc + - enum: + - allwinner,sun8i-r40-emmc + - allwinner,sun50i-h5-emmc + - allwinner,sun50i-h6-emmc - const: allwinner,sun50i-a64-emmc - items: - - const: allwinner,sun8i-r40-mmc + - enum: + - allwinner,sun8i-r40-mmc + - allwinner,sun50i-h5-mmc + - allwinner,sun50i-h6-mmc - const: allwinner,sun50i-a64-mmc - items: - - const: allwinner,sun50i-h5-emmc - - const: allwinner,sun50i-a64-emmc - - items: - - const: allwinner,sun50i-h5-mmc - - const: allwinner,sun50i-a64-mmc - - items: - - const: allwinner,sun50i-h6-emmc - - const: allwinner,sun50i-a64-emmc - - items: - - const: allwinner,sun50i-h6-mmc - - const: allwinner,sun50i-a64-mmc - - items: - - const: allwinner,sun20i-d1-emmc - - const: allwinner,sun50i-a100-emmc - - items: - - const: allwinner,sun50i-h616-emmc + - enum: + - allwinner,sun20i-d1-emmc + - allwinner,sun50i-h616-emmc - const: allwinner,sun50i-a100-emmc - items: - const: allwinner,sun50i-h616-mmc - const: allwinner,sun50i-a100-mmc - - items: - - const: allwinner,suniv-f1c100s-mmc - - const: allwinner,sun7i-a20-mmc =20 reg: maxItems: 1 --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 242C71474DA; Fri, 7 Mar 2025 00:57:26 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309049; cv=none; b=GmzEWHPtvoFBJypmjxOTT8FXhgpqlxT6rHMWK2jw5N2GTkJdzVhRl8c6RX8iiCxpgNXEPvJix18MxVv3Qc6YCuRlMBuG/xkZMiGo4JT+feEDXNIorJuSlTcNQ9ktvz/SLzv8plkeGJng8im4b6tEqBAFpalSzDV8mYsakT4VVEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309049; c=relaxed/simple; bh=3vWWyG7MBd+DfNTEwJ/WP/VVI33rbJgw+EDHXaX/+SQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=TmmjbUZ48wA6gKk/pOPHrN9nCvTn3nV5RLvQnGTKdSNjESQgcYguEw/gD5w1XcjkJqoVzaqO08je3zlDzsED6tTvBrSMbCjMaUBlhdfxu5havnN6KBsfaUiw1p3fe0GyaC/ymtIsGwOOqjYYLaq9EwsoI+hNQxClLgmx7n2QFm0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 4FB442103; Thu, 6 Mar 2025 16:57:39 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C22943F5A1; Thu, 6 Mar 2025 16:57:24 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Ulf Hansson Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-mmc@vger.kernel.org, Conor Dooley Subject: [PATCH v3 02/15] dt-bindings: mmc: sunxi: add compatible strings for Allwinner A523 Date: Fri, 7 Mar 2025 00:56:59 +0000 Message-ID: <20250307005712.16828-3-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A523 uses the same MMC IP as the D1. Introduce the new specific compatible strings, and use them with fallbacks to the D1 strings. Signed-off-by: Andre Przywara Acked-by: Conor Dooley --- .../devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.= yaml b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml index 8e4c77b7e4ab9..9f3b1edacaa02 100644 --- a/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml +++ b/Documentation/devicetree/bindings/mmc/allwinner,sun4i-a10-mmc.yaml @@ -50,10 +50,14 @@ properties: - enum: - allwinner,sun20i-d1-emmc - allwinner,sun50i-h616-emmc + - allwinner,sun55i-a523-emmc - const: allwinner,sun50i-a100-emmc - items: - const: allwinner,sun50i-h616-mmc - const: allwinner,sun50i-a100-mmc + - items: + - const: allwinner,sun55i-a523-mmc + - const: allwinner,sun20i-d1-mmc =20 reg: maxItems: 1 --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 0A65B154433; Fri, 7 Mar 2025 00:57:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309050; cv=none; b=dTv/XcaVfYkaSSL9CAQIcv3N7dMu37MdjWCk2W4c4+CMazYSwpbyDmRvN1UDWs7DTCbEySBiJEHk3w6INq/3bi+WSOoK8kwQo0qou2cgTJ7hn21gLZoD1TgYKzuERvl6Ggne3cy22Tyz1ikKK6093Xpp5iuFxqmGfjTcbxAT8lk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309050; c=relaxed/simple; bh=fM32MIuFbhdfHzKCwFeEw51NeeHy3o+LDYOxFqpZreA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=UbISFlDNy65fqnlfuZr0FA0FLYOYcN0yBwMQ5agCRjfTDtA+Y+V+UiedShAfzVfd+q8np6JTviiJkwsbMjIkdkyb1eWWbCcrLNMbSaJSSrQI/TO8Ul908GIn5ArfN42OgE28uSBkF2dXlepeosTr9s+6MEgJDu1i4jZ+P1zeM1A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6898F1BC0; Thu, 6 Mar 2025 16:57:41 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id C08633F5A1; Thu, 6 Mar 2025 16:57:26 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Wim Van Sebroeck , Guenter Roeck Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org, Conor Dooley Subject: [PATCH v3 03/15] dt-bindings: watchdog: sunxi: add Allwinner A523 compatible string Date: Fri, 7 Mar 2025 00:57:00 +0000 Message-ID: <20250307005712.16828-4-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A523 SoC features a watchdog similar to the one used in previous SoCs, but moves some registers around (by just one word), making it incompatible to existing IPs. Add the new name to the list of compatible string, and also to the list of IP requiring two clock inputs. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec Acked-by: Conor Dooley --- .../devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10= -wdt.yaml b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-= wdt.yaml index 64c8f73938099..b35ac03d51727 100644 --- a/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.ya= ml +++ b/Documentation/devicetree/bindings/watchdog/allwinner,sun4i-a10-wdt.ya= ml @@ -32,6 +32,7 @@ properties: - items: - const: allwinner,sun20i-d1-wdt-reset - const: allwinner,sun20i-d1-wdt + - const: allwinner,sun55i-a523-wdt =20 reg: maxItems: 1 @@ -60,6 +61,7 @@ if: - allwinner,sun20i-d1-wdt-reset - allwinner,sun50i-r329-wdt - allwinner,sun50i-r329-wdt-reset + - allwinner,sun55i-a523-wdt =20 then: properties: --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 08C9016A395; Fri, 7 Mar 2025 00:57:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309052; cv=none; b=LFtIq5qlSggVK1umz2ZVTgxFfq98DtCNywL92bjDWEpfi/dEWWprVS8vQt/T6NLE24ZMAj8rRFpRmbt0ng6yaxpP3fhvF8tEAIJmztbxrBWJKlfbedqcSljxIRhUqKnSjDyVQR+S2grULuyACFMJrqkWU2vCpAfCw9nY30NQVvw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309052; c=relaxed/simple; bh=XXm9l3nOhtBu8Jy2QAjx5UHw2rmLJpcfj19w9vRNy64=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=evJDrom6bW8PKchxnxLEvaYsCEl1Q22ed2Ez8shKRX3wKvDmlFisjL2r5c0fg5VeYe8KbR3jD66pDuD3745IzQoAPBBSHRJjXAdphVxZhvKcFFAyVidDylgx0Un/aWrFojS0KZ9I9I+0+KJBARnhfCV/7690moOxrgMwjwom1Tc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 667782103; Thu, 6 Mar 2025 16:57:43 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D91003F5A1; Thu, 6 Mar 2025 16:57:28 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Wim Van Sebroeck , Guenter Roeck Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-watchdog@vger.kernel.org Subject: [PATCH v3 04/15] watchdog: sunxi_wdt: Add support for Allwinner A523 Date: Fri, 7 Mar 2025 00:57:01 +0000 Message-ID: <20250307005712.16828-5-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A523 SoC comes with a watchdog very similar to the ones in the previous Allwinner SoCs, but oddly enough moves the first half of its registers up by one word. Since we have different offsets for these registers across the other SoCs as well, this can simply be modelled by just stating the new offsets in our per-SoC struct. The rest of the IP is the same as in the D1, although the A523 moves its watchdog to a separate MMIO frame, so it's not embedded in the timer anymore. The driver can be ignorant of this, because the DT will take care of this. Add a new struct for the A523, specifying the SoC-specific details, and tie the new DT compatible string to it. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- drivers/watchdog/sunxi_wdt.c | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/drivers/watchdog/sunxi_wdt.c b/drivers/watchdog/sunxi_wdt.c index b85354a995826..b6c761acc3de6 100644 --- a/drivers/watchdog/sunxi_wdt.c +++ b/drivers/watchdog/sunxi_wdt.c @@ -236,10 +236,21 @@ static const struct sunxi_wdt_reg sun20i_wdt_reg =3D { .wdt_key_val =3D 0x16aa0000, }; =20 +static const struct sunxi_wdt_reg sun55i_wdt_reg =3D { + .wdt_ctrl =3D 0x0c, + .wdt_cfg =3D 0x10, + .wdt_mode =3D 0x14, + .wdt_timeout_shift =3D 4, + .wdt_reset_mask =3D 0x03, + .wdt_reset_val =3D 0x01, + .wdt_key_val =3D 0x16aa0000, +}; + static const struct of_device_id sunxi_wdt_dt_ids[] =3D { { .compatible =3D "allwinner,sun4i-a10-wdt", .data =3D &sun4i_wdt_reg }, { .compatible =3D "allwinner,sun6i-a31-wdt", .data =3D &sun6i_wdt_reg }, { .compatible =3D "allwinner,sun20i-d1-wdt", .data =3D &sun20i_wdt_reg }, + { .compatible =3D "allwinner,sun55i-a523-wdt", .data =3D &sun55i_wdt_reg = }, { /* sentinel */ } }; MODULE_DEVICE_TABLE(of, sunxi_wdt_dt_ids); --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C098517E019; Fri, 7 Mar 2025 00:57:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309054; cv=none; b=oula1LzZPsEYABZTGne4mT7sMGnN9smq0AAI6M0api511K9F00L+ObTJemBiFx6/ZJjOSTy33XpGlZCnh/okBw1/gPKb3ciLpu4cMEHOfNozm9xOS+CoQIzkEwrArPSluEhTCaaJqfizane2NlOIpcZfb75+4eAnn2PklVHL8O0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309054; c=relaxed/simple; bh=mkXqbcR0W4euc2u2S45LOzSywL4GY35RKPrgO19oo0o=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=gtPjRM7lJ/rE0q4qRmNCTgVk29EhaY1xkC/SRgXUJaFiBGYrcnc/6GI9QA/zqatkx+Mazuat0u9QOxZM3SL9Eu1c6A2YK897moqCDzGHefvVvzaLjB0FJPbdQrn9d7S89B82jHeqOd4psl1kv2p6QaWYgMx0NUb08D38StzIsFg= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 2F01E2247; Thu, 6 Mar 2025 16:57:45 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id D74DB3F5A1; Thu, 6 Mar 2025 16:57:30 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Thomas Gleixner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 05/15] dt-bindings: irq: sun7i-nmi: document the Allwinner A523 NMI controller Date: Fri, 7 Mar 2025 00:57:02 +0000 Message-ID: <20250307005712.16828-6-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A523 SoC contains an NMI controller very close to the one used in the recent Allwinner SoCs, but it adds another bit that needs to be toggled to actually deliver the IRQs. Sigh. Add the A523 specific name to the list of allowed compatible strings. Signed-off-by: Andre Przywara Acked-by: Rob Herring (Arm) --- .../interrupt-controller/allwinner,sun7i-a20-sc-nmi.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/interrupt-controller/allwinn= er,sun7i-a20-sc-nmi.yaml b/Documentation/devicetree/bindings/interrupt-cont= roller/allwinner,sun7i-a20-sc-nmi.yaml index f49b43f45f3d9..06e3621a8c06c 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7= i-a20-sc-nmi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/allwinner,sun7= i-a20-sc-nmi.yaml @@ -26,6 +26,7 @@ properties: deprecated: true - const: allwinner,sun7i-a20-sc-nmi - const: allwinner,sun9i-a80-nmi + - const: allwinner,sun55i-a523-nmi - items: - enum: - allwinner,sun8i-v3s-nmi --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id CA228188CD8; Fri, 7 Mar 2025 00:57:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309056; cv=none; b=mgNneHj0NnD515hFj8NvFd8jNdi9Z4LbM78kjZXdZA92KpPDivJT6NUcLjItfUChfrc1/jNgc2whM7j5W9qD/CnvTq+7hbatRmFjSXdDjsUwnzkBkmI8cSuNGVQnAd5N7kE+3kMRSxKY6Xh/ryK6Kgvb1088sSBZC/DOGwc0UX0= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309056; c=relaxed/simple; bh=RzTn2/y3Rd3RoDPi/R/UfMlv8OCJ4DsZHO6sRVU7Xgc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=kaXwGih/AFVvb4zzZQdcchG0rD4qdzkmbH72iy8EZZVwlPR70gI5Ogr6R7SVPZ4azjefxps69ACfaAxA55KrbngmGZI/6iMgRGTrWbQ7ZkoE9DVOy/YF6nuk+BHxGy9FtgKhSummESEQmj+nq3xaqArHq28VkKmg7iAKYyH2Dgw= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EC97F22BE; Thu, 6 Mar 2025 16:57:46 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 9F5163F5A1; Thu, 6 Mar 2025 16:57:32 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Thomas Gleixner Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 06/15] irqchip/sunxi-nmi: Support Allwinner A523 NMI controller Date: Fri, 7 Mar 2025 00:57:03 +0000 Message-ID: <20250307005712.16828-7-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The NMI controller in the Allwinner A523 is almost compatible to the previous versions of this IP, but requires the extra bit 31 to be set in the enable register to actually report the NMI. Add a mask to allow such an enable bit to be specified, and add this to the per-SoC data structure. As this struct was just for different register offsets so far, it was consequently named "reg_offs", which is now no longer applicable, so rename this to the more generic "data" on the way, and move the existing offsets into a struct of its own. Also add the respective Allwinner A523 compatible string, and set bit 31 in its enable mask, to add support for this SoC. Signed-off-by: Andre Przywara --- drivers/irqchip/irq-sunxi-nmi.c | 76 ++++++++++++++++++++------------- 1 file changed, 47 insertions(+), 29 deletions(-) diff --git a/drivers/irqchip/irq-sunxi-nmi.c b/drivers/irqchip/irq-sunxi-nm= i.c index 0b43121520243..b05904a147088 100644 --- a/drivers/irqchip/irq-sunxi-nmi.c +++ b/drivers/irqchip/irq-sunxi-nmi.c @@ -48,28 +48,38 @@ enum { SUNXI_SRC_TYPE_EDGE_RISING, }; =20 -struct sunxi_sc_nmi_reg_offs { - u32 ctrl; - u32 pend; - u32 enable; +struct sunxi_sc_nmi_data { + struct { + u32 ctrl; + u32 pend; + u32 enable; + } reg_offs; + u32 enable_val; }; =20 -static const struct sunxi_sc_nmi_reg_offs sun6i_reg_offs __initconst =3D { - .ctrl =3D SUN6I_NMI_CTRL, - .pend =3D SUN6I_NMI_PENDING, - .enable =3D SUN6I_NMI_ENABLE, +static const struct sunxi_sc_nmi_data sun6i_data __initconst =3D { + .reg_offs.ctrl =3D SUN6I_NMI_CTRL, + .reg_offs.pend =3D SUN6I_NMI_PENDING, + .reg_offs.enable =3D SUN6I_NMI_ENABLE, }; =20 -static const struct sunxi_sc_nmi_reg_offs sun7i_reg_offs __initconst =3D { - .ctrl =3D SUN7I_NMI_CTRL, - .pend =3D SUN7I_NMI_PENDING, - .enable =3D SUN7I_NMI_ENABLE, +static const struct sunxi_sc_nmi_data sun7i_data __initconst =3D { + .reg_offs.ctrl =3D SUN7I_NMI_CTRL, + .reg_offs.pend =3D SUN7I_NMI_PENDING, + .reg_offs.enable =3D SUN7I_NMI_ENABLE, }; =20 -static const struct sunxi_sc_nmi_reg_offs sun9i_reg_offs __initconst =3D { - .ctrl =3D SUN9I_NMI_CTRL, - .pend =3D SUN9I_NMI_PENDING, - .enable =3D SUN9I_NMI_ENABLE, +static const struct sunxi_sc_nmi_data sun9i_data __initconst =3D { + .reg_offs.ctrl =3D SUN9I_NMI_CTRL, + .reg_offs.pend =3D SUN9I_NMI_PENDING, + .reg_offs.enable =3D SUN9I_NMI_ENABLE, +}; + +static const struct sunxi_sc_nmi_data sun55i_a523_data __initconst =3D { + .reg_offs.ctrl =3D SUN9I_NMI_CTRL, + .reg_offs.pend =3D SUN9I_NMI_PENDING, + .reg_offs.enable =3D SUN9I_NMI_ENABLE, + .enable_val =3D BIT(31), }; =20 static inline void sunxi_sc_nmi_write(struct irq_chip_generic *gc, u32 off, @@ -143,7 +153,7 @@ static int sunxi_sc_nmi_set_type(struct irq_data *data,= unsigned int flow_type) } =20 static int __init sunxi_sc_nmi_irq_init(struct device_node *node, - const struct sunxi_sc_nmi_reg_offs *reg_offs) + const struct sunxi_sc_nmi_data *data) { struct irq_domain *domain; struct irq_chip_generic *gc; @@ -186,27 +196,28 @@ static int __init sunxi_sc_nmi_irq_init(struct device= _node *node, gc->chip_types[0].chip.irq_unmask =3D irq_gc_mask_set_bit; gc->chip_types[0].chip.irq_eoi =3D irq_gc_ack_set_bit; gc->chip_types[0].chip.irq_set_type =3D sunxi_sc_nmi_set_type; - gc->chip_types[0].chip.flags =3D IRQCHIP_EOI_THREADED | IRQCHIP_EOI_IF_H= ANDLED | + gc->chip_types[0].chip.flags =3D IRQCHIP_EOI_THREADED | + IRQCHIP_EOI_IF_HANDLED | IRQCHIP_SKIP_SET_WAKE; - gc->chip_types[0].regs.ack =3D reg_offs->pend; - gc->chip_types[0].regs.mask =3D reg_offs->enable; - gc->chip_types[0].regs.type =3D reg_offs->ctrl; + gc->chip_types[0].regs.ack =3D data->reg_offs.pend; + gc->chip_types[0].regs.mask =3D data->reg_offs.enable; + gc->chip_types[0].regs.type =3D data->reg_offs.ctrl; =20 gc->chip_types[1].type =3D IRQ_TYPE_EDGE_BOTH; gc->chip_types[1].chip.irq_ack =3D irq_gc_ack_set_bit; gc->chip_types[1].chip.irq_mask =3D irq_gc_mask_clr_bit; gc->chip_types[1].chip.irq_unmask =3D irq_gc_mask_set_bit; gc->chip_types[1].chip.irq_set_type =3D sunxi_sc_nmi_set_type; - gc->chip_types[1].regs.ack =3D reg_offs->pend; - gc->chip_types[1].regs.mask =3D reg_offs->enable; - gc->chip_types[1].regs.type =3D reg_offs->ctrl; + gc->chip_types[1].regs.ack =3D data->reg_offs.pend; + gc->chip_types[1].regs.mask =3D data->reg_offs.enable; + gc->chip_types[1].regs.type =3D data->reg_offs.ctrl; gc->chip_types[1].handler =3D handle_edge_irq; =20 /* Disable any active interrupts */ - sunxi_sc_nmi_write(gc, reg_offs->enable, 0); + sunxi_sc_nmi_write(gc, data->reg_offs.enable, data->enable_val); =20 /* Clear any pending NMI interrupts */ - sunxi_sc_nmi_write(gc, reg_offs->pend, SUNXI_NMI_IRQ_BIT); + sunxi_sc_nmi_write(gc, data->reg_offs.pend, SUNXI_NMI_IRQ_BIT); =20 irq_set_chained_handler_and_data(irq, sunxi_sc_nmi_handle_irq, domain); =20 @@ -221,20 +232,27 @@ static int __init sunxi_sc_nmi_irq_init(struct device= _node *node, static int __init sun6i_sc_nmi_irq_init(struct device_node *node, struct device_node *parent) { - return sunxi_sc_nmi_irq_init(node, &sun6i_reg_offs); + return sunxi_sc_nmi_irq_init(node, &sun6i_data); } IRQCHIP_DECLARE(sun6i_sc_nmi, "allwinner,sun6i-a31-sc-nmi", sun6i_sc_nmi_i= rq_init); =20 static int __init sun7i_sc_nmi_irq_init(struct device_node *node, struct device_node *parent) { - return sunxi_sc_nmi_irq_init(node, &sun7i_reg_offs); + return sunxi_sc_nmi_irq_init(node, &sun7i_data); } IRQCHIP_DECLARE(sun7i_sc_nmi, "allwinner,sun7i-a20-sc-nmi", sun7i_sc_nmi_i= rq_init); =20 static int __init sun9i_nmi_irq_init(struct device_node *node, struct device_node *parent) { - return sunxi_sc_nmi_irq_init(node, &sun9i_reg_offs); + return sunxi_sc_nmi_irq_init(node, &sun9i_data); } IRQCHIP_DECLARE(sun9i_nmi, "allwinner,sun9i-a80-nmi", sun9i_nmi_irq_init); + +static int __init sun55i_nmi_irq_init(struct device_node *node, + struct device_node *parent) +{ + return sunxi_sc_nmi_irq_init(node, &sun55i_a523_data); +} +IRQCHIP_DECLARE(sun55i_nmi, "allwinner,sun55i-a523-nmi", sun55i_nmi_irq_in= it); --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C137318C03A; Fri, 7 Mar 2025 00:57:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 101EA169E; Thu, 6 Mar 2025 16:57:49 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 67B093F5A1; Thu, 6 Mar 2025 16:57:34 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland , Vinod Koul , Kishon Vijay Abraham I Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, Conor Dooley Subject: [PATCH v3 07/15] dt-bindings: phy: document Allwinner A523 USB-2.0 PHY Date: Fri, 7 Mar 2025 00:57:04 +0000 Message-ID: <20250307005712.16828-8-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A523 SoC contains a USB-2.0 PHY fully compatible to the one used in the D1/T113s SoCs. This PHY controls the two USB-2.0 ports, there is a separate and quite different PHY for the USB-3.0 port. Add the new compatible string, with a fallback to the D1 version. Signed-off-by: Andre Przywara Acked-by: Conor Dooley --- .../devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb= -phy.yaml b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-= phy.yaml index 21209126ed008..580c3296a18d7 100644 --- a/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.ya= ml +++ b/Documentation/devicetree/bindings/phy/allwinner,sun50i-a64-usb-phy.ya= ml @@ -20,7 +20,9 @@ properties: - allwinner,sun20i-d1-usb-phy - allwinner,sun50i-a64-usb-phy - items: - - const: allwinner,sun50i-a100-usb-phy + - enum: + - allwinner,sun50i-a100-usb-phy + - allwinner,sun55i-a523-usb-phy - const: allwinner,sun20i-d1-usb-phy =20 reg: --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 651BA18DB1F; Fri, 7 Mar 2025 00:57:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309060; cv=none; b=Ad3AaYtvWUSMFHPmbEL3/+4n3hr2AmhlGKCJ2KyJB3gq10Bd6QXoLoCb8hddHRgFkD/BpzqhoL4l/00bVMeahY0TGeGmvcFnXu2rPnxpolDquXDj/BIMxu2C5d2PLcIod5AnYBdBb6vk0oW6vxspy8coLLYT+/UCbw1Tl0AB62c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309060; c=relaxed/simple; bh=u/xGFOcQmDm5i4vA5WjKGqSewjFjtp+9cUEsTuTUnis=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=WLVDFnDueXYWWpDspPZrzU7pN5cnjTIfnCZb8dXpXSOGsvmF1jhWjO64iZqyGCIaJUbS8QqVSAVmPAlhx1DqJKyD+L3CPeAxH0SCM1RFwPOX25/aLwIfjgqR4NV3lyLSK0H+ePJl8E+qRxNez8/vJYrPWthwMue2y7TrCRoh8zY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CBEDB2247; Thu, 6 Mar 2025 16:57:50 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 80B8B3F5A1; Thu, 6 Mar 2025 16:57:36 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 08/15] arm64: dts: allwinner: Add Allwinner A523 .dtsi file Date: Fri, 7 Mar 2025 00:57:05 +0000 Message-ID: <20250307005712.16828-9-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Allwinner A523, and its siblings A527 and T527, which share the same die, are a new family of SoCs introduced in 2023. They features eight Arm Cortex-A55 cores, and, among the other usual peripherals, a PCIe and USB 3.0 controller. Add the basic SoC devicetree .dtsi for the chip, describing the fundamental peripherals: the cores, GIC, timer, RTC, CCU and pinctrl. Also some other peripherals are fully compatible with previous IP, so add the USB and MMC nodes as well. The other peripherals will be added in the future, once we understand their compatibility and DT requirements. Signed-off-by: Andre Przywara Reviewed-by: Jernej Skrabec --- .../arm64/boot/dts/allwinner/sun55i-a523.dtsi | 598 ++++++++++++++++++ 1 file changed, 598 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi b/arch/arm64/bo= ot/dts/allwinner/sun55i-a523.dtsi new file mode 100644 index 0000000000000..ee485899ba0af --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-a523.dtsi @@ -0,0 +1,598 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2023-2024 Arm Ltd. + +#include +#include +#include +#include +#include +#include + +/ { + interrupt-parent =3D <&gic>; + #address-cells =3D <2>; + #size-cells =3D <2>; + + cpus { + #address-cells =3D <1>; + #size-cells =3D <0>; + + cpu0: cpu@0 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + reg =3D <0x000>; + enable-method =3D "psci"; + }; + + cpu1: cpu@100 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + reg =3D <0x100>; + enable-method =3D "psci"; + }; + + cpu2: cpu@200 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + reg =3D <0x200>; + enable-method =3D "psci"; + }; + + cpu3: cpu@300 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + reg =3D <0x300>; + enable-method =3D "psci"; + }; + + cpu4: cpu@400 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + reg =3D <0x400>; + enable-method =3D "psci"; + }; + + cpu5: cpu@500 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + reg =3D <0x500>; + enable-method =3D "psci"; + }; + + cpu6: cpu@600 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + reg =3D <0x600>; + enable-method =3D "psci"; + }; + + cpu7: cpu@700 { + compatible =3D "arm,cortex-a55"; + device_type =3D "cpu"; + reg =3D <0x700>; + enable-method =3D "psci"; + }; + }; + + osc24M: osc24M-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <24000000>; + clock-output-names =3D "osc24M"; + }; + + pmu { + compatible =3D "arm,cortex-a55-pmu"; + interrupts =3D ; + }; + + psci { + compatible =3D "arm,psci-0.2"; + method =3D "smc"; + }; + + timer { + compatible =3D "arm,armv8-timer"; + arm,no-tick-in-suspend; + interrupts =3D , + , + , + ; + }; + + soc { + compatible =3D "simple-bus"; + #address-cells =3D <1>; + #size-cells =3D <1>; + ranges =3D <0x0 0x0 0x0 0x40000000>; + + pio: pinctrl@2000000 { + compatible =3D "allwinner,sun55i-a523-pinctrl"; + reg =3D <0x2000000 0x800>; + interrupts =3D , + , + , + , + , + , + , + , + , + ; + clocks =3D <&ccu CLK_APB1>, <&osc24M>, <&rtc CLK_OSC32K>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells =3D <3>; + interrupt-controller; + #interrupt-cells =3D <3>; + + mmc0_pins: mmc0-pins { + pins =3D "PF0" ,"PF1", "PF2", "PF3", "PF4", "PF5"; + allwinner,pinmux =3D <2>; + function =3D "mmc0"; + drive-strength =3D <30>; + bias-pull-up; + }; + + /omit-if-no-ref/ + mmc1_pins: mmc1-pins { + pins =3D "PG0" ,"PG1", "PG2", "PG3", "PG4", "PG5"; + allwinner,pinmux =3D <2>; + function =3D "mmc1"; + drive-strength =3D <30>; + bias-pull-up; + }; + + mmc2_pins: mmc2-pins { + pins =3D "PC0", "PC1" ,"PC5", "PC6", "PC8", + "PC9", "PC10", "PC11", "PC13", "PC14", + "PC15", "PC16"; + allwinner,pinmux =3D <3>; + function =3D "mmc2"; + drive-strength =3D <30>; + bias-pull-up; + }; + + uart0_pb_pins: uart0-pb-pins { + pins =3D "PB9", "PB10"; + allwinner,pinmux =3D <2>; + function =3D "uart0"; + }; + }; + + ccu: clock-controller@2001000 { + compatible =3D "allwinner,sun55i-a523-ccu"; + reg =3D <0x02001000 0x1000>; + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, <&rtc CLK_OSC32K_FANOUT>; + clock-names =3D "hosc", "losc", + "iosc", "losc-fanout"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + mmc0: mmc@4020000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04020000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC0>, <&ccu CLK_MMC0>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC0>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc0_pins>; + status =3D "disabled"; + + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc1: mmc@4021000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04021000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC1>, <&ccu CLK_MMC1>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC1>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc1_pins>; + status =3D "disabled"; + + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + mmc2: mmc@4022000 { + compatible =3D "allwinner,sun55i-a523-mmc", + "allwinner,sun20i-d1-mmc"; + reg =3D <0x04022000 0x1000>; + clocks =3D <&ccu CLK_BUS_MMC2>, <&ccu CLK_MMC2>; + clock-names =3D "ahb", "mmc"; + resets =3D <&ccu RST_BUS_MMC2>; + reset-names =3D "ahb"; + interrupts =3D ; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&mmc2_pins>; + status =3D "disabled"; + + max-frequency =3D <150000000>; + cap-sd-highspeed; + cap-mmc-highspeed; + cap-sdio-irq; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + wdt: watchdog@2050000 { + compatible =3D "allwinner,sun55i-a523-wdt"; + reg =3D <0x2050000 0x20>; + interrupts =3D ; + clocks =3D <&osc24M>, <&rtc CLK_OSC32K>; + clock-names =3D "hosc", "losc"; + status =3D "okay"; + }; + + uart0: serial@2500000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x02500000 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART0>; + resets =3D <&ccu RST_BUS_UART0>; + status =3D "disabled"; + }; + + uart1: serial@2500400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x02500400 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART1>; + resets =3D <&ccu RST_BUS_UART1>; + status =3D "disabled"; + }; + + uart2: serial@2500800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x02500800 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART2>; + resets =3D <&ccu RST_BUS_UART2>; + status =3D "disabled"; + }; + + uart3: serial@2500c00 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x02500c00 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART3>; + resets =3D <&ccu RST_BUS_UART3>; + status =3D "disabled"; + }; + + uart4: serial@2501000 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x02501000 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART4>; + resets =3D <&ccu RST_BUS_UART4>; + status =3D "disabled"; + }; + + uart5: serial@2501400 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x02501400 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART5>; + resets =3D <&ccu RST_BUS_UART5>; + status =3D "disabled"; + }; + + uart6: serial@2501800 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x02501800 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART6>; + resets =3D <&ccu RST_BUS_UART6>; + status =3D "disabled"; + }; + + uart7: serial@2501c00 { + compatible =3D "snps,dw-apb-uart"; + reg =3D <0x02501c00 0x400>; + interrupts =3D ; + reg-shift =3D <2>; + reg-io-width =3D <4>; + clocks =3D <&ccu CLK_BUS_UART7>; + resets =3D <&ccu RST_BUS_UART7>; + status =3D "disabled"; + }; + + i2c0: i2c@2502000 { + compatible =3D "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C0>; + resets =3D <&ccu RST_BUS_I2C0>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c1: i2c@2502400 { + compatible =3D "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C1>; + resets =3D <&ccu RST_BUS_I2C1>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c2: i2c@2502800 { + compatible =3D "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502800 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C2>; + resets =3D <&ccu RST_BUS_I2C2>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c3: i2c@2502c00 { + compatible =3D "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2502c00 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C3>; + resets =3D <&ccu RST_BUS_I2C3>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c4: i2c@2503000 { + compatible =3D "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2503000 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C4>; + resets =3D <&ccu RST_BUS_I2C4>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + i2c5: i2c@2503400 { + compatible =3D "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x2503400 0x400>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_I2C5>; + resets =3D <&ccu RST_BUS_I2C5>; + status =3D "disabled"; + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + gic: interrupt-controller@3400000 { + compatible =3D "arm,gic-v3"; + #address-cells =3D <1>; + #interrupt-cells =3D <3>; + #size-cells =3D <1>; + ranges; + interrupt-controller; + reg =3D <0x3400000 0x10000>, + <0x3460000 0x100000>; + interrupts =3D ; + dma-noncoherent; + + its: msi-controller@3440000 { + compatible =3D "arm,gic-v3-its"; + reg =3D <0x3440000 0x20000>; + msi-controller; + #msi-cells =3D <1>; + dma-noncoherent; + }; + }; + + usb_otg: usb@4100000 { + compatible =3D "allwinner,sun55i-a523-musb", + "allwinner,sun8i-a33-musb"; + reg =3D <0x4100000 0x400>; + interrupts =3D ; + interrupt-names =3D "mc"; + clocks =3D <&ccu CLK_BUS_OTG>; + resets =3D <&ccu RST_BUS_OTG>; + extcon =3D <&usbphy 0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + usbphy: phy@4100400 { + compatible =3D "allwinner,sun55i-a523-usb-phy", + "allwinner,sun20i-d1-usb-phy"; + reg =3D <0x4100400 0x100>, + <0x4101800 0x100>, + <0x4200800 0x100>; + reg-names =3D "phy_ctrl", + "pmu0", + "pmu1"; + clocks =3D <&osc24M>, + <&osc24M>; + clock-names =3D "usb0_phy", + "usb1_phy"; + resets =3D <&ccu RST_USB_PHY0>, + <&ccu RST_USB_PHY1>; + reset-names =3D "usb0_reset", + "usb1_reset"; + status =3D "disabled"; + #phy-cells =3D <1>; + }; + + ehci0: usb@4101000 { + compatible =3D "allwinner,sun55i-a523-ehci", + "generic-ehci"; + reg =3D <0x4101000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_BUS_EHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>, + <&ccu RST_BUS_EHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci0: usb@4101400 { + compatible =3D "allwinner,sun55i-a523-ohci", + "generic-ohci"; + reg =3D <0x4101400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI0>, + <&ccu CLK_USB_OHCI0>; + resets =3D <&ccu RST_BUS_OHCI0>; + phys =3D <&usbphy 0>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ehci1: usb@4200000 { + compatible =3D "allwinner,sun55i-a523-ehci", + "generic-ehci"; + reg =3D <0x4200000 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_BUS_EHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>, + <&ccu RST_BUS_EHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + ohci1: usb@4200400 { + compatible =3D "allwinner,sun55i-a523-ohci", + "generic-ohci"; + reg =3D <0x4200400 0x100>; + interrupts =3D ; + clocks =3D <&ccu CLK_BUS_OHCI1>, + <&ccu CLK_USB_OHCI1>; + resets =3D <&ccu RST_BUS_OHCI1>; + phys =3D <&usbphy 1>; + phy-names =3D "usb"; + status =3D "disabled"; + }; + + r_ccu: clock-controller@7010000 { + compatible =3D "allwinner,sun55i-a523-r-ccu"; + reg =3D <0x7010000 0x250>; + clocks =3D <&osc24M>, + <&rtc CLK_OSC32K>, + <&rtc CLK_IOSC>, + <&ccu CLK_PLL_PERIPH0_200M>, + <&ccu CLK_PLL_AUDIO0_4X>; + clock-names =3D "hosc", + "losc", + "iosc", + "pll-periph", + "pll-audio"; + #clock-cells =3D <1>; + #reset-cells =3D <1>; + }; + + nmi_intc: interrupt-controller@7010320 { + compatible =3D "allwinner,sun55i-a523-nmi"; + reg =3D <0x07010320 0xc>; + interrupt-controller; + #interrupt-cells =3D <2>; + interrupts =3D ; + }; + + r_pio: pinctrl@7022000 { + compatible =3D "allwinner,sun55i-a523-r-pinctrl"; + reg =3D <0x7022000 0x800>; + interrupts =3D , + ; + clocks =3D <&r_ccu CLK_R_APB0>, + <&osc24M>, + <&rtc CLK_OSC32K>; + clock-names =3D "apb", "hosc", "losc"; + gpio-controller; + #gpio-cells =3D <3>; + interrupt-controller; + #interrupt-cells =3D <3>; + + r_i2c_pins: r-i2c-pins { + pins =3D "PL0" ,"PL1"; + allwinner,pinmux =3D <2>; + function =3D "r_i2c0"; + }; + }; + + r_i2c0: i2c@7081400 { + compatible =3D "allwinner,sun55i-a523-i2c", + "allwinner,sun8i-v536-i2c", + "allwinner,sun6i-a31-i2c"; + reg =3D <0x07081400 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_BUS_R_I2C0>; + resets =3D <&r_ccu RST_BUS_R_I2C0>; + pinctrl-names =3D "default"; + pinctrl-0 =3D <&r_i2c_pins>; + status =3D "disabled"; + + #address-cells =3D <1>; + #size-cells =3D <0>; + }; + + rtc: rtc@7090000 { + compatible =3D "allwinner,sun55i-a523-rtc", + "allwinner,sun50i-r329-rtc"; + reg =3D <0x7090000 0x400>; + interrupts =3D ; + clocks =3D <&r_ccu CLK_BUS_R_RTC>, + <&osc24M>, + <&r_ccu CLK_R_AHB>; + clock-names =3D "bus", "hosc", "ahb"; + #clock-cells =3D <1>; + }; + }; +}; --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 96D7418F2D8; Fri, 7 Mar 2025 00:57:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; 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Thu, 6 Mar 2025 16:57:52 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 4875C3F5A1; Thu, 6 Mar 2025 16:57:38 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Conor Dooley Subject: [PATCH v3 09/15] dt-bindings: vendor-prefixes: Add YuzukiHD name Date: Fri, 7 Mar 2025 00:57:06 +0000 Message-ID: <20250307005712.16828-10-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" YuzukiHD provides Open Source Hardware designs, and also offers ready-made builds of them: https://github.com/YuzukiHD Signed-off-by: Andre Przywara Acked-by: Conor Dooley --- Documentation/devicetree/bindings/vendor-prefixes.yaml | 2 ++ 1 file changed, 2 insertions(+) diff --git a/Documentation/devicetree/bindings/vendor-prefixes.yaml b/Docum= entation/devicetree/bindings/vendor-prefixes.yaml index 5079ca6ce1d1e..8c0991e002ee8 100644 --- a/Documentation/devicetree/bindings/vendor-prefixes.yaml +++ b/Documentation/devicetree/bindings/vendor-prefixes.yaml @@ -1737,6 +1737,8 @@ patternProperties: description: Shenzhen Yashi Changhua Intelligent Technology Co., Ltd. "^ysoft,.*": description: Y Soft Corporation a.s. + "^yuzukihd,.*": + description: YuzukiHD Open Source Hardware "^zarlink,.*": description: Zarlink Semiconductor "^zealz,.*": --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C38A018FC72; Fri, 7 Mar 2025 00:57:41 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309064; cv=none; b=KVdUfHnxj4qyqg/R9sADJZ+mBKWJ7XTWlIHEtQSnRruAmngh15z+mPMC+jRRf5vSemoTm1Y/cIjj03ETrr05RD2cbb2RKj/5vvdJNQg1U7y6nj7ZoRgCz9UGSVjUckBbjkRNnIq3rUdglw9LJC/9VHUE2Ij0ItX1IfHK7RenL8c= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309064; c=relaxed/simple; bh=8sXhQaB/gFaaPKgrUaamVTBu14GdoJq0nYw4DnuFjgc=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=LwcHAQJGREFIYeUiU/2MdBl9wWjmcXiyFTnDuj0LyscK4Xltfth+litlMPmGjGpRaAwRa+b+MtNyhomMGBKjdGVOZsIOZsIB6bRt/wgiHQCynyIp6+36NXnbXtg0X45DN8/pZ2xRLoXq9GUEHTSLkqJH6rnb/TZbmbWB4BylFvk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 5E9401BC0; Thu, 6 Mar 2025 16:57:54 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 114E73F5A1; Thu, 6 Mar 2025 16:57:39 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org, Krzysztof Kozlowski Subject: [PATCH v3 10/15] dt-bindings: arm: sunxi: Add new board names for A523 generation Date: Fri, 7 Mar 2025 00:57:07 +0000 Message-ID: <20250307005712.16828-11-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The new Allwinner A523 SoC family comes in different packages, though they all share the same die, and so the devicetree bindings. Add three board names that use a version from this SoC family: - The Avaota A1: an Open Source hardware router board. - The Radxa Cubie A5E: a typical development board - The X96QPro+: a TV box Add their compatible name to the list. Signed-off-by: Andre Przywara Acked-by: Krzysztof Kozlowski --- Documentation/devicetree/bindings/arm/sunxi.yaml | 15 +++++++++++++++ 1 file changed, 15 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentati= on/devicetree/bindings/arm/sunxi.yaml index 046536d02706f..80096819fda91 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -840,6 +840,11 @@ properties: - const: allwinner,r7-tv-dongle - const: allwinner,sun5i-a10s =20 + - description: Radxa Cubie A5E + items: + - const: radxa,cubie-a5e + - const: allwinner,sun55i-a527 + - description: Remix Mini PC items: - const: jide,remix-mini-pc @@ -961,6 +966,11 @@ properties: - const: hechuang,x96-mate - const: allwinner,sun50i-h616 =20 + - description: X96Q Pro+ + items: + - const: amediatech,x96q-pro-plus + - const: allwinner,sun55i-h728 + - description: Xunlong OrangePi items: - const: xunlong,orangepi @@ -1076,4 +1086,9 @@ properties: - const: xunlong,orangepi-zero3 - const: allwinner,sun50i-h618 =20 + - description: YuzukiHD Avaota A1 + items: + - const: yuzukihd,avaota-a1 + - const: allwinner,sun55i-t527 + additionalProperties: true --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A773F19049A; Fri, 7 Mar 2025 00:57:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309065; cv=none; b=EBcJbM8WLa3Nj1iy7P9F/shZn7NRZhm0pkldiJKeAIFf4BNS0CpJae6xTtMWTgWtP6DRDARnkerRT0JEIn3u7LJCxoE2nUHinf2CkL4qkTJEFhwSl7TywoX3Hk6F+dqlV4x3lK8GZSTcbhtWmCqvmAlj1irz665YL1jpMuBnrzI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309065; c=relaxed/simple; bh=m+Gc8jnUS7Vg6MnvyCSxMTgUK8xle1y6s35suoEZejE=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=nAJZaufpoB/ju45bKv8dgT/QpMragOSR1577BXEL1KEz2bqZ0lYllnJeKKz9alJT43LVAB5OQuRuKPpmN0k4BkQf1LZKs/TXciZPUU52mI7l1MEO4wpz6xRKcRlbF5mCOUBmjNPRjao80D8dwdsaV5VtOkRW4GuP7YSPYDYALes= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0CC42169E; Thu, 6 Mar 2025 16:57:56 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CE3E23F5A1; Thu, 6 Mar 2025 16:57:41 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 11/15] arm64: dts: allwinner: a523: add Avaota-A1 router support Date: Fri, 7 Mar 2025 00:57:08 +0000 Message-ID: <20250307005712.16828-12-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Avaota A1 router board is an Open Source hardware board, designed by YuzukiHD. Pine64 produces some boards and sells them. It uses the Allwinner A527 or T527 SoC, and comes with the following features: - Eight ARM Cortex-A55 cores, Mali-G57 MC1 GPU - 1GiB/2GiB/4GiB LPDDR4 DRAM - AXP717 + AXP323 PMIC - Raspberry-Pi-2 compatible GPIO header - 1 USB 2.0 type A host port, 1 USB 3.0 type A host post - 1 USB 2.0 type C port (OTG + serial debug) - MicroSD slot - eMMC between 16 and 128 GiB - on-board 16MiB bootable SPI NOR flash - two 1Gbps Ethernet ports (via RTL8211F PHYs) - HDMI port - DP port - camera and LCD connectors - 3.5mm headphone jack - (yet) unsupported WiFi/BT chip - 1.3" LC display, connected via SPI - 12 V barrel plug for power supply Add the devicetree file describing the currently supported features. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-t527-avaota-a1.dts | 308 ++++++++++++++++++ 2 files changed, 309 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 00bed412ee31c..0d678a7499e3c 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -52,3 +52,4 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx= -2024.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-sp.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-avaota-a1.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts b/arch= /arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts new file mode 100644 index 0000000000000..85a546aecdbe1 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-t527-avaota-a1.dts @@ -0,0 +1,308 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2024 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include + +/ { + model =3D "Avaota A1"; + compatible =3D "yuzukihd,avaota-a1", "allwinner,sun55i-t527"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "ext_osc32k"; + }; + + reg_vcc12v: vcc12v { + /* DC input jack */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-12v"; + regulator-min-microvolt =3D <12000000>; + regulator-max-microvolt =3D <12000000>; + regulator-always-on; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the 12V->5V regulator */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc12v>; + regulator-always-on; + }; + + reg_usb_vbus: vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&pio 8 12 GPIO_ACTIVE_HIGH>; /* PI12 */ + enable-active-high; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_cldo3>; + cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_DOWN)>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&mmc2 { + bus-width =3D <8>; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + non-removable; + vmmc-supply =3D <®_cldo3>; + vqmmc-supply =3D <®_cldo1>; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pb-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply =3D <®_cldo1>; + vcc-pd-supply =3D <®_dcdc4>; + vcc-pe-supply =3D <®_dcdc4>; + vcc-pf-supply =3D <®_cldo3>; /* actually switchable */ + vcc-pg-supply =3D <®_bldo1>; + vcc-ph-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply =3D <®_dcdc4>; + vcc-pj-supply =3D <®_dcdc4>; + vcc-pk-supply =3D <®_bldo3>; +}; + +&r_i2c0 { + status =3D "okay"; + + axp717: pmic@35 { + compatible =3D "x-powers,axp717"; + reg =3D <0x35>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&nmi_intc>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + vin4-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <920000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1160000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-dram"; + }; + + reg_dcdc4: dcdc4 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vdd-io"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + /* not connected */ + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-pl-pm"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pg-wifi-lvds"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-dram-1v8"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-cvp-pk-vid1v8"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pc"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-efuse"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-io-mmc-spi-ana"; + }; + + reg_cldo4: cldo4 { + /* not connected */ + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible =3D "x-powers,axp323"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&nmi_intc>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + status =3D "okay"; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + + regulators { + aldo1 { + /* not connected */ + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* Some RISC-V management core related voltage */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply =3D <®_aldo3>; + */ + vcc-pm-supply =3D <®_aldo3>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pb_pins>; + status =3D "okay"; +}; + +&usb_otg { + /* + * The CC pins of the USB-C port have two pull-down resistors + * connected to GND, which fixes this port to a peripheral role. + * There is a regulator, controlled by a GPIO, to provide VBUS power + * to the port, and a VBUSDET GPIO, to detect externally provided + * power, but without the CC pins there is no real way to do a + * runtime role detection. + */ + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb0_vbus-supply =3D <®_usb_vbus>; + usb0_vbus_det-gpios =3D <&pio 8 13 GPIO_ACTIVE_HIGH>; /* PI13 */ + status =3D "okay"; +}; --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 217EE1922FD; Fri, 7 Mar 2025 00:57:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Thu, 6 Mar 2025 16:57:57 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 7B9A03F5A1; Thu, 6 Mar 2025 16:57:43 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 12/15] arm64: dts: allwinner: a523: add X96Q-Pro+ support Date: Fri, 7 Mar 2025 00:57:09 +0000 Message-ID: <20250307005712.16828-13-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The X96QPro+ is a TV box using the Allwinner H728 SoC. That SoC seems to be a package variant of the A523 family, at least it uses the same SoC ID and is compatible as far as we can assess. It comes with the following specs: - Allwinner H728 SoC: 8 Arm Cortex-A55 cores, Mali-G57 MC1 GPU - 2 or 4GiB DDR3L DRAM - 32, 64, or 128 GiB eMMC flash - AXP717 + AXP323 PMICs - Gigabit Ethernet (using MAXIO PHY) - HDMI port - 2 * USB 2.0 ports - 1 * USB 3.0 port - microSD card slot - TOSLINK digital audio output - 3.5mm A/V port - infrared sensor - 7-segment display - 5V barrel plug power supply - power button The PCB provides holes for soldering a UART header or cable, this is connected to the debug UART0. There is another set of UART pins available. The board also features a FEL button (accessible through the 3.5mm socket) and a reset button (only accessible when case is open). This .dts just describes the basic peripherals as far as we support them at the moment. The PMIC rail assignments are reverse engineered as far as possible, by dumping them from a running Android system, and correlating them to other boards using the same SoC. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-h728-x96qpro+.dts | 287 ++++++++++++++++++ 2 files changed, 288 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 0d678a7499e3c..983be49ea6ef8 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -52,4 +52,5 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx= -2024.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-sp.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-h728-x96qpro+.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-avaota-a1.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts b/arch/= arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts new file mode 100644 index 0000000000000..c0bce3f4fa925 --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-h728-x96qpro+.dts @@ -0,0 +1,287 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2024 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include + +/ { + model =3D "X96Q Pro+"; + compatible =3D "amediatech,x96q-pro-plus", "allwinner,sun55i-h728"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "ext_osc32k"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the barrel plug */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; + + reg_vcc3v3: vcc3v3 { + /* 3.3V dummy supply for the SD card */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-3v3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + vin-supply =3D <®_vcc5v>; + regulator-always-on; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_vcc3v3>; + cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_DOWN)>; /* PF6 */ + bus-width =3D <4>; + disable-wp; + status =3D "okay"; +}; + +&mmc2 { + vmmc-supply =3D <®_cldo3>; + vqmmc-supply =3D <®_cldo1>; + bus-width =3D <8>; + non-removable; + cap-mmc-hw-reset; + mmc-ddr-1_8v; + mmc-hs200-1_8v; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pb-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply =3D <®_cldo1>; + vcc-pd-supply =3D <®_dcdc4>; + vcc-pe-supply =3D <®_dcdc4>; + vcc-pf-supply =3D <®_cldo3>; /* actually switchable */ + vcc-pg-supply =3D <®_bldo1>; + vcc-ph-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply =3D <®_dcdc4>; + vcc-pj-supply =3D <®_dcdc4>; + vcc-pk-supply =3D <®_bldo3>; +}; + +&r_i2c0 { + status =3D "okay"; + + axp717: pmic@34 { + compatible =3D "x-powers,axp717"; + reg =3D <0x34>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&nmi_intc>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + vin4-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.0(?) GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <920000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1360000>; + regulator-max-microvolt =3D <1360000>; + regulator-name =3D "vdd-dram"; + }; + + reg_dcdc4: dcdc4 { + regulator-min-microvolt =3D <1000000>; + regulator-max-microvolt =3D <1000000>; + regulator-name =3D "vdd-dcdc4"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + /* not connected */ + }; + + reg_aldo3: aldo3 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-aldo3"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pg-wifi-lvds"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-dram-1v8"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt =3D <2800000>; + regulator-max-microvolt =3D <2800000>; + regulator-name =3D "vcc-bldo3"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-codec-sd"; + }; + + reg_cldo2: cldo2 { + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-codec-eth-sd"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-eth-phy"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible =3D "x-powers,axp323"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&nmi_intc>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + status =3D "okay"; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + + regulators { + aldo1 { + /* not connected */ + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1050000>; + regulator-max-microvolt =3D <1050000>; + regulator-name =3D "vdd-dcdc3"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply =3D <®_aldo3>; + */ + vcc-pm-supply =3D <®_aldo3>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pb_pins>; + status =3D "okay"; +}; + +&usb_otg { + /* USB0 is a USB-A receptacle, always powered, so force host mode. */ + dr_mode =3D "host"; + status =3D "okay"; +}; + +&usbphy { + status =3D "okay"; +}; --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id C12B4193425; Fri, 7 Mar 2025 00:57:46 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309068; cv=none; b=Q4I4Ei5J9U+MbX0UqaHxTwwxc8YN9a2f/itzo5tMKrxl0qNzNOp4VqN85RmvmQjfKNuTOrdNTbHavwWT4aMzK+3M5G1DLC3Oo8k2O9VCw4qgah2Z7YLXuWXEKHikbQdKR8IyObNZ0UkfxHN4fPsh3wwRWEeclgkvbGG4l4khmTU= ARC-Message-Signature: i=1; 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Thu, 6 Mar 2025 16:57:45 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 13/15] arm64: dts: allwinner: a523: add Radxa A5E support Date: Fri, 7 Mar 2025 00:57:10 +0000 Message-ID: <20250307005712.16828-14-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Radxa A5E is a development board using the Allwinner A527 SoC, which is using the same die as the A523 SoC, just exposing the pins of more peripherals (like HDMI or the 2nd MAC). The board features: - Allwinner A527/T527 SoC: 8 ARM Cortex-A55 cores, Mali-G57 MC1 GPU - 1GiB/2GiB/4GiB LPDDR4 DRAM - AXP717 + AXP323 PMICs - Raspberry-Pi-2 compatible 40pin GPIO header - 1 USB 2.0 type C port (OTG), also power supply - 1 USB 3.0 type A host port (multiplexed with M.2 slot) - 1 M.2 M-key 2230 slot, with 1 PCIe2.1 lane connected (multiplexed with USB 3.0 port) - MicroSD slot - optional eMMC, 8, 16 or 32GB available - optional on-board 16MiB bootable SPI NOR flash - two 1Gbps Ethernet ports (via MAXIO MAE0621A PHYs) - PoE header for optional supply circuit on one Ethernet port - WiFi 802.11 a/b/g/n/ac/ax (LB-Link BL-M8800DS2 module using AIC8800) - HDMI port - camera and LCD connectors - power supply via USB-C connector (but no PD) or GPIO header pins This .dts describes the devices as far as we support them at the moment. The PMIC rails have been assigned as per the schematics. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../dts/allwinner/sun55i-a527-radxa-a5e.dts | 299 ++++++++++++++++++ 2 files changed, 300 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 983be49ea6ef8..9d5e14695af0b 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -52,5 +52,6 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx= -2024.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-plus.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-sp.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-a527-radxa-a5e.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-h728-x96qpro+.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun55i-t527-avaota-a1.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts b/arch= /arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts new file mode 100644 index 0000000000000..912e1bda974ce --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun55i-a527-radxa-a5e.dts @@ -0,0 +1,299 @@ +// SPDX-License-Identifier: (GPL-2.0-only OR MIT) +// Copyright (C) 2025 Arm Ltd. + +/dts-v1/; + +#include "sun55i-a523.dtsi" + +#include + +/ { + model =3D "Radxa A5E"; + compatible =3D "radxa,cubie-a5e", "allwinner,sun55i-a527"; + + aliases { + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + ext_osc32k: ext-osc32k-clk { + #clock-cells =3D <0>; + compatible =3D "fixed-clock"; + clock-frequency =3D <32768>; + clock-output-names =3D "ext_osc32k"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply from the USB-C connector */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; + + reg_usb_vbus: vbus { + compatible =3D "regulator-fixed"; + regulator-name =3D "usb-vbus"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + vin-supply =3D <®_vcc5v>; + gpio =3D <&r_pio 0 8 GPIO_ACTIVE_HIGH>; /* PL8 */ + enable-active-high; + }; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&mmc0 { + vmmc-supply =3D <®_cldo3>; + cd-gpios =3D <&pio 5 6 (GPIO_ACTIVE_LOW | GPIO_PULL_DOWN)>; /* PF6 */ + bus-width =3D <4>; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&pio { + vcc-pb-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pc-supply =3D <®_cldo1>; + vcc-pd-supply =3D <®_cldo3>; + vcc-pe-supply =3D <®_aldo2>; + vcc-pf-supply =3D <®_cldo3>; /* actually switchable */ + vcc-pg-supply =3D <®_bldo1>; + vcc-ph-supply =3D <®_cldo3>; /* via VCC-IO */ + vcc-pi-supply =3D <®_cldo3>; + vcc-pj-supply =3D <®_cldo4>; + vcc-pk-supply =3D <®_cldo1>; +}; + +&r_i2c0 { + status =3D "okay"; + + axp717: pmic@34 { + compatible =3D "x-powers,axp717"; + reg =3D <0x34>; + interrupt-controller; + #interrupt-cells =3D <1>; + interrupt-parent =3D <&nmi_intc>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + vin4-supply =3D <®_vcc5v>; + aldoin-supply =3D <®_vcc5v>; + bldoin-supply =3D <®_vcc5v>; + cldoin-supply =3D <®_vcc5v>; + + regulators { + /* Supplies the "little" cluster (1.4 GHz cores) */ + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpul"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <920000>; + regulator-max-microvolt =3D <920000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1100000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vdd-dram"; + }; + + reg_aldo1: aldo1 { + /* not connected */ + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pe"; + }; + + reg_aldo3: aldo3 { + /* supplies the I2C pins for this PMIC */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-pl-usb"; + }; + + reg_aldo4: aldo4 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pll-dxco-avcc"; + }; + + reg_bldo1: bldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pg-iowifi"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pm-lpddr4"; + }; + + reg_bldo3: bldo3 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-mipi-cam"; + }; + + reg_bldo4: bldo4 { + /* not connected */ + }; + + reg_cldo1: cldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-pc-and-their-dog"; + }; + + reg_cldo2: cldo2 { + /* not connected */ + }; + + reg_cldo3: cldo3 { + /* IO, USB-2, 3V3, card, NAND, sensor, PI */ + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-io-mmc-spi-ana"; + }; + + reg_cldo4: cldo4 { + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc-pj-phy"; + }; + + reg_cpusldo: cpusldo { + /* supplies the management core */ + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-cpus"; + }; + }; + }; + + axp323: pmic@36 { + compatible =3D "x-powers,axp323"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&nmi_intc>; + interrupts =3D <0 IRQ_TYPE_LEVEL_LOW>; + status =3D "okay"; + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + + regulators { + aldo1 { + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc-mipi-dsi"; + }; + + dldo1 { + /* not connected */ + }; + + /* Supplies the "big" cluster (1.8 GHz cores) */ + reg_dcdc1_323: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <1160000>; + regulator-name =3D "vdd-cpub"; + }; + + /* DCDC2 is polyphased with DCDC1 */ + + /* RISC-V management core supply */ + reg_dcdc3_323: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <900000>; + regulator-max-microvolt =3D <900000>; + regulator-name =3D "vdd-dnr"; + }; + }; + }; +}; + +&r_pio { +/* + * Specifying the supply would create a circular dependency. + * + * vcc-pl-supply =3D <®_aldo3>; + */ + vcc-pm-supply =3D <®_aldo3>; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_pb_pins>; + status =3D "okay"; +}; + +&usb_otg { + /* + * The USB-C port is the primary power supply, so in this configuration + * relies on the other end of the USB cable to supply the VBUS power. + * So use this port in peripheral mode. + * It is possible to supply the board with the 5V pins on the GPIO + * header, and since the DCIN_5V line is hardwired to the USB-C VBUS + * pins, the port turns into a host port, unconditionally supplying + * power. The dr_mode property should be changed to "host" here, if + * users choose this setup. + */ + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +/* + * The schematic describes USB0_ID (PL10), measuring VBUS_5V, which looks = to + * be always on. Also there is USB-VBUSDET (PL2), which is measuring the s= ame + * VBUS_5V. There is also DCIN_DET, which measures DCIN_5V, so the power + * input rail. + * None of them seem to make any sense in relation to detecting USB devices + * or whether there is power provided via any USB pins: they would always + * report high, otherwise the system wouldn't be running. + * The AXP717C provides proper USB-C CC pin functionality, but the PMIC is + * not connected to those pins of the USB-C connector. + */ +&usbphy { + usb0_vbus-supply =3D <®_vcc5v>; + usb1_vbus-supply =3D <®_usb_vbus>; + status =3D "okay"; +}; --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id A1915198A06; Fri, 7 Mar 2025 00:57:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309070; cv=none; b=shHcNnneNnkRz0cjaJbFb1POVNxWP0CX20pyb+ejJLIsM7XmaiH4d0ssRUnZZhENfJI65JxBQo0xjhjf24fidLMMa64NpSQA9h9lFclTJdUeBvrBH4UM6eolLJ6SF9yLPsArY8S3jOrt7UR2TyU8NfNNp78YjSlPtaRWEBg0CGo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309070; c=relaxed/simple; bh=Nrub3qkRA+TgomjJTI2MZjvgOCSj3Qk4NBzAijrfWTI=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=I1hzErpkRCBeH2MnnLcqTw7RidsFqkb4rZRQQNJD0eUcMrLlTAv4hdrR+fneCtHRDHpmrOu1Kxv86WOa3iGg3r9jAKrhJSmAAntbqoGazy3Y5HRJBrUqzBENTWagqOvu23tpkxBdty8lj6PoHGIKhhTo4g9eAqWmG9WoktsAuHE= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 07C4D1BC0; Thu, 6 Mar 2025 16:58:01 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id CADB33F5A1; Thu, 6 Mar 2025 16:57:46 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 14/15] dt-bindings: arm: sunxi: Add YuzukiHD Chameleon board name Date: Fri, 7 Mar 2025 00:57:11 +0000 Message-ID: <20250307005712.16828-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Chameleon is an Open Source hardware board designed by YuzkuiHD, using the Allwinner H618 SoC: https://github.com/YuzukiHD/YuzukiChameleon Add its compatible name to the list of valid board name. Signed-off-by: Andre Przywara Acked-by: Rob Herring (Arm) --- Documentation/devicetree/bindings/arm/sunxi.yaml | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/arm/sunxi.yaml b/Documentati= on/devicetree/bindings/arm/sunxi.yaml index 80096819fda91..cce31492b0f11 100644 --- a/Documentation/devicetree/bindings/arm/sunxi.yaml +++ b/Documentation/devicetree/bindings/arm/sunxi.yaml @@ -1091,4 +1091,9 @@ properties: - const: yuzukihd,avaota-a1 - const: allwinner,sun55i-t527 =20 + - description: YuzukiHD Chameleon + items: + - const: yuzukihd,chameleon + - const: allwinner,sun50i-h618 + additionalProperties: true --=20 2.46.3 From nobody Wed Dec 17 10:49:55 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 1FD2E199921; Fri, 7 Mar 2025 00:57:50 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309072; cv=none; b=bxQzN3EhWHkU37J18KHwaM7mzuDmeFA0OIAVhAvr8XSkWiUrFjlqQzC11qGwC6VWbZhoc37z94UHd2oLKV6rPeSSUe1t4DYJqgC5LqAgYo+LRzk26N+fiEpXF6ztqvtSf6al4rc/obIZFhPCX0gfQGpOoHwR4/Rt4SEjxGa16jc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741309072; c=relaxed/simple; bh=b6ac9gsryn/biv+Qm9Qm5Kp4+Sp/ecGafckN2AXquo8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=jZfyxrQWc4cgGVKvccQJFl0EffMiNIegFTCUOeGT0CKQyOBKuTxNiGvEbBHr3aesoosPis5HiOPMRgpBj/pFvS6/DDICLuxMEvWTJIwBXVaP3CfSnJ21jXZJww4JqruXDGphYGP2ZJiqnB2bxHFh890b1ilyTBNqrcmwLFkTtEo= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id ABB9B2103; Thu, 6 Mar 2025 16:58:02 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 789303F5A1; Thu, 6 Mar 2025 16:57:48 -0800 (PST) From: Andre Przywara To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 15/15] arm64: dts: allwinner: h616: add YuzukiHD Chameleon support Date: Fri, 7 Mar 2025 00:57:12 +0000 Message-ID: <20250307005712.16828-16-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250307005712.16828-1-andre.przywara@arm.com> References: <20250307005712.16828-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The Chameleon board is an OpenHardware devboard made by YuzukiTsuru. The form factor resembles the Raspberry Pi Model A boards, though it differs significantly in its features: - Allwinner H618 SoC (4 * Arm Cortex-A53 cores, 1MB L2 cache, 1.4 GHz) - between 512MiB and 2GiB DDR3 DRAM - up to 128 GiB eMMC flash - AXP313a PMIC - 100 Mbit/s Ethernet pins on a header - XR829 WIFI+Bluetooth chip - 4 * USB 2.0 USB-C ports - microSD card slot - 3.5mm A/V port Add the devicetree describing the board's peripherals and their connections. Signed-off-by: Andre Przywara Acked-by: Jernej Skrabec --- arch/arm64/boot/dts/allwinner/Makefile | 1 + .../sun50i-h618-yuzukihd-chameleon.dts | 222 ++++++++++++++++++ 2 files changed, 223 insertions(+) create mode 100644 arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-cham= eleon.dts diff --git a/arch/arm64/boot/dts/allwinner/Makefile b/arch/arm64/boot/dts/a= llwinner/Makefile index 9d5e14695af0b..c15f6a0d8d55a 100644 --- a/arch/arm64/boot/dts/allwinner/Makefile +++ b/arch/arm64/boot/dts/allwinner/Makefile @@ -48,6 +48,7 @@ dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-longanpi-3h.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-orangepi-zero2w.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-orangepi-zero3.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-transpeed-8k618-t.dtb +dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h618-yuzukihd-chameleon.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-2024.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-h.dtb dtb-$(CONFIG_ARCH_SUNXI) +=3D sun50i-h700-anbernic-rg35xx-plus.dtb diff --git a/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.d= ts b/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts new file mode 100644 index 0000000000000..eae56908b9b4e --- /dev/null +++ b/arch/arm64/boot/dts/allwinner/sun50i-h618-yuzukihd-chameleon.dts @@ -0,0 +1,222 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2024 Arm Ltd. + */ + +/dts-v1/; + +#include "sun50i-h616.dtsi" +#include "sun50i-h616-cpu-opp.dtsi" + +#include +#include + +/ { + model =3D "Yuzuki Chameleon"; + compatible =3D "yuzukihd,chameleon", "allwinner,sun50i-h618"; + + aliases { + ethernet1 =3D &sdio_wifi; + serial0 =3D &uart0; + }; + + chosen { + stdout-path =3D "serial0:115200n8"; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the USB-C socket */ + compatible =3D "regulator-fixed"; + regulator-name =3D "vcc-5v"; + regulator-min-microvolt =3D <5000000>; + regulator-max-microvolt =3D <5000000>; + regulator-always-on; + }; + + wifi_pwrseq: pwrseq { + compatible =3D "mmc-pwrseq-simple"; + clocks =3D <&rtc CLK_OSC32K_FANOUT>; + clock-names =3D "ext_clock"; + pinctrl-0 =3D <&x32clk_fanout_pin>; + pinctrl-names =3D "default"; + reset-gpios =3D <&pio 6 11 GPIO_ACTIVE_LOW>; /* PG11 */ + }; +}; + +&codec { + allwinner,audio-routing =3D "Line Out", "LINEOUT"; + status =3D "okay"; +}; + +&cpu0 { + cpu-supply =3D <®_dcdc2>; +}; + +&ehci0 { + status =3D "okay"; +}; + +&ehci1 { + status =3D "okay"; +}; + +&ehci2 { + status =3D "okay"; +}; + +&ehci3 { + status =3D "okay"; +}; + +&mmc0 { + bus-width =3D <4>; + cd-gpios =3D <&pio 5 6 GPIO_ACTIVE_LOW>; /* PF6 */ + disable-wp; + vmmc-supply =3D <®_dldo1>; + status =3D "okay"; +}; + +&mmc1 { + bus-width =3D <4>; + mmc-pwrseq =3D <&wifi_pwrseq>; + non-removable; + vmmc-supply =3D <®_dldo1>; + vqmmc-supply =3D <®_dldo1>; + status =3D "okay"; + + sdio_wifi: wifi@1 { + reg =3D <1>; + interrupt-parent =3D <&pio>; + interrupts =3D <6 12 IRQ_TYPE_LEVEL_LOW>; /* PG12 */ + interrupt-names =3D "host-wake"; + }; +}; + +&mmc2 { + bus-width =3D <8>; + cap-mmc-hw-reset; + mmc-ddr-3_3v; + non-removable; + vmmc-supply =3D <®_dldo1>; + vqmmc-supply =3D <®_dldo1>; + status =3D "okay"; +}; + +&ohci0 { + status =3D "okay"; +}; + +&ohci1 { + status =3D "okay"; +}; + +&ohci2 { + status =3D "okay"; +}; + +&ohci3 { + status =3D "okay"; +}; + +&pio { + vcc-pc-supply =3D <®_dldo1>; + vcc-pf-supply =3D <®_dldo1>; /* via VCC_IO */ + vcc-pg-supply =3D <®_dldo1>; + vcc-ph-supply =3D <®_dldo1>; /* via VCC_IO */ + vcc-pi-supply =3D <®_dldo1>; +}; + +&r_i2c { + status =3D "okay"; + + axp313: pmic@36 { + compatible =3D "x-powers,axp313a"; + reg =3D <0x36>; + #interrupt-cells =3D <1>; + interrupt-controller; + interrupt-parent =3D <&pio>; + interrupts =3D <2 2 IRQ_TYPE_LEVEL_LOW>; /* PC2 */ + + vin1-supply =3D <®_vcc5v>; + vin2-supply =3D <®_vcc5v>; + vin3-supply =3D <®_vcc5v>; + + regulators { + /* Supplies VCC-PLL, so needs to be always on. */ + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + regulator-name =3D "vcc1v8"; + }; + + /* Supplies VCC-IO, so needs to be always on. */ + reg_dldo1: dldo1 { + regulator-always-on; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + regulator-name =3D "vcc3v3"; + }; + + reg_dcdc1: dcdc1 { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <990000>; + regulator-name =3D "vdd-gpu-sys"; + }; + + reg_dcdc2: dcdc2 { + regulator-always-on; + regulator-min-microvolt =3D <810000>; + regulator-max-microvolt =3D <1100000>; + regulator-name =3D "vdd-cpu"; + }; + + reg_dcdc3: dcdc3 { + regulator-always-on; + regulator-min-microvolt =3D <1500000>; + regulator-max-microvolt =3D <1500000>; + regulator-name =3D "vdd-dram"; + }; + }; + }; +}; + +&uart0 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart0_ph_pins>; + status =3D "okay"; +}; + +/* Connected to the Bluetooth UART pins of the XR829 Wifi/BT chip. */ +&uart1 { + pinctrl-names =3D "default"; + pinctrl-0 =3D <&uart1_pins>, <&uart1_rts_cts_pins>; + uart-has-rtscts; + status =3D "okay"; +}; + +&usbotg { + /* + * PHY0 pins are connected to a USB-C socket, but a role switch + * is not implemented: both CC pins are pulled to GND. + * The VBUS pins power the device, so a fixed peripheral mode + * is the best choice. + * The board can be powered via GPIOs, in this case port0 *can* + * act as a host (with a cable/adapter ignoring CC), as VBUS is + * then provided by the GPIOs. Any user of this setup would + * need to adjust the DT accordingly: dr_mode set to "host", + * enabling OHCI0 and EHCI0. + */ + dr_mode =3D "peripheral"; + status =3D "okay"; +}; + +&usbphy { + usb0_id_det-gpios =3D <&pio 6 18 GPIO_ACTIVE_HIGH>; /* PG18 */ + usb0_vbus-supply =3D <®_vcc5v>; + usb1_vbus-supply =3D <®_vcc5v>; + usb2_vbus-supply =3D <®_vcc5v>; + usb3_vbus-supply =3D <®_vcc5v>; + status =3D "okay"; +}; --=20 2.46.3