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Fri, 07 Mar 2025 02:55:37 -0800 (PST) From: Akihiko Odaki Date: Fri, 07 Mar 2025 19:55:28 +0900 Subject: [PATCH v2 1/3] KVM: arm64: PMU: Fix SET_ONE_REG for vPMC regs Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250307-pmc-v2-1-6c3375a5f1e4@daynix.com> References: <20250307-pmc-v2-0-6c3375a5f1e4@daynix.com> In-Reply-To: <20250307-pmc-v2-0-6c3375a5f1e4@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.14.2 Reload the perf event when setting the vPMU counter (vPMC) registers (PMCCNTR_EL0 and PMEVCNTR_EL0). This is a change corresponding to commit 9228b26194d1 ("KVM: arm64: PMU: Fix GET_ONE_REG for vPMC regs to return the current value") but for SET_ONE_REG. Values of vPMC registers are saved in sysreg files on certain occasions. These saved values don't represent the current values of the vPMC registers if the perf events for the vPMCs count events after the save. The current values of those registers are the sum of the sysreg file value and the current perf event counter value. But, when userspace writes those registers (using KVM_SET_ONE_REG), KVM only updates the sysreg file value and leaves the current perf event counter value as is. Fix this by releasing the current perf event and trigger recreating one with KVM_REQ_RELOAD_PMU. Fixes: 051ff581ce70 ("arm64: KVM: Add access handler for event counter regi= ster") Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 16 ++++++++++++++++ arch/arm64/kvm/sys_regs.c | 20 +++++++++++++++++++- include/kvm/arm_pmu.h | 1 + 3 files changed, 36 insertions(+), 1 deletion(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index e3e82b66e2268d37d5e2630e47ddf085a6846e1c..1402cce5625bffa706aabe5e612= 1d1f3817a0aaf 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -191,6 +191,22 @@ void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, = u64 select_idx, u64 val) kvm_pmu_set_pmc_value(kvm_vcpu_idx_to_pmc(vcpu, select_idx), val, false); } =20 +/** + * kvm_pmu_set_counter_value_user - set PMU counter value from user + * @vcpu: The vcpu pointer + * @select_idx: The counter index + * @val: The counter value + */ +void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, u64 select_idx,= u64 val) +{ + if (!kvm_vcpu_has_pmu(vcpu)) + return; + + kvm_pmu_release_perf_event(kvm_vcpu_idx_to_pmc(vcpu, select_idx)); + __vcpu_sys_reg(vcpu, counter_index_to_reg(select_idx)) =3D val; + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); +} + /** * kvm_pmu_release_perf_event - remove the perf event * @pmc: The PMU counter pointer diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 42791971f75887796afab905cc12f49fead39e10..27418dac791df9a89124f867879= e899db175e506 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1035,6 +1035,22 @@ static int get_pmu_evcntr(struct kvm_vcpu *vcpu, con= st struct sys_reg_desc *r, return 0; } =20 +static int set_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc= *r, + u64 val) +{ + u64 idx; + + if (r->CRn =3D=3D 9 && r->CRm =3D=3D 13 && r->Op2 =3D=3D 0) + /* PMCCNTR_EL0 */ + idx =3D ARMV8_PMU_CYCLE_IDX; + else + /* PMEVCNTRn_EL0 */ + idx =3D ((r->CRm & 3) << 3) | (r->Op2 & 7); + + kvm_pmu_set_counter_value_user(vcpu, idx, val); + return 0; +} + static bool access_pmu_evcntr(struct kvm_vcpu *vcpu, struct sys_reg_params *p, const struct sys_reg_desc *r) @@ -1328,6 +1344,7 @@ static int set_pmcr(struct kvm_vcpu *vcpu, const stru= ct sys_reg_desc *r, #define PMU_PMEVCNTR_EL0(n) \ { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \ .reset =3D reset_pmevcntr, .get_user =3D get_pmu_evcntr, \ + .set_user =3D set_pmu_evcntr, \ .access =3D access_pmu_evcntr, .reg =3D (PMEVCNTR0_EL0 + n), } =20 /* Macro to expand the PMEVTYPERn_EL0 register */ @@ -2682,7 +2699,8 @@ static const struct sys_reg_desc sys_reg_descs[] =3D { .access =3D access_pmceid, .reset =3D NULL }, { PMU_SYS_REG(PMCCNTR_EL0), .access =3D access_pmu_evcntr, .reset =3D reset_unknown, - .reg =3D PMCCNTR_EL0, .get_user =3D get_pmu_evcntr}, + .reg =3D PMCCNTR_EL0, .get_user =3D get_pmu_evcntr, + .set_user =3D set_pmu_evcntr }, { PMU_SYS_REG(PMXEVTYPER_EL0), .access =3D access_pmu_evtyper, .reset =3D NULL }, { PMU_SYS_REG(PMXEVCNTR_EL0), diff --git a/include/kvm/arm_pmu.h b/include/kvm/arm_pmu.h index 28b380ad8dfa942c4275e0c7ed3535d309b81b2f..9c062756ebfad5ea55536215445= 9ffe9f8311c6d 100644 --- a/include/kvm/arm_pmu.h +++ b/include/kvm/arm_pmu.h @@ -41,6 +41,7 @@ bool kvm_supports_guest_pmuv3(void); #define kvm_arm_pmu_irq_initialized(v) ((v)->arch.pmu.irq_num >=3D VGIC_NR= _SGIS) u64 kvm_pmu_get_counter_value(struct kvm_vcpu *vcpu, u64 select_idx); void kvm_pmu_set_counter_value(struct kvm_vcpu *vcpu, u64 select_idx, u64 = val); +void kvm_pmu_set_counter_value_user(struct kvm_vcpu *vcpu, u64 select_idx,= u64 val); u64 kvm_pmu_valid_counter_mask(struct kvm_vcpu *vcpu); u64 kvm_pmu_get_pmceid(struct kvm_vcpu *vcpu, bool pmceid1); void kvm_pmu_vcpu_init(struct kvm_vcpu *vcpu); --=20 2.48.1 From nobody Sun Feb 8 09:27:32 2026 Received: from mail-pl1-f176.google.com (mail-pl1-f176.google.com [209.85.214.176]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 18A18212D9D for ; Fri, 7 Mar 2025 10:55:43 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.176 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741344945; 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Fri, 07 Mar 2025 02:55:43 -0800 (PST) Received: from localhost ([157.82.205.237]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-736ab812cb0sm1257087b3a.164.2025.03.07.02.55.40 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Mar 2025 02:55:42 -0800 (PST) From: Akihiko Odaki Date: Fri, 07 Mar 2025 19:55:29 +0900 Subject: [PATCH v2 2/3] KVM: arm64: PMU: Reload when user modifies registers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250307-pmc-v2-2-6c3375a5f1e4@daynix.com> References: <20250307-pmc-v2-0-6c3375a5f1e4@daynix.com> In-Reply-To: <20250307-pmc-v2-0-6c3375a5f1e4@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.14.2 Commit d0c94c49792c ("KVM: arm64: Restore PMU configuration on first run") added the code to reload the PMU configuration on first run. Trigger the code when a user modifies a PMU register instead so that PMU configuration changes made by users will be applied also after the first run. Signed-off-by: Akihiko Odaki --- arch/arm64/kvm/pmu-emul.c | 3 --- arch/arm64/kvm/sys_regs.c | 5 +++++ 2 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/arm64/kvm/pmu-emul.c b/arch/arm64/kvm/pmu-emul.c index 1402cce5625bffa706aabe5e6121d1f3817a0aaf..04eb3856b96576fad5afc8927c8= 916ff9738f9d7 100644 --- a/arch/arm64/kvm/pmu-emul.c +++ b/arch/arm64/kvm/pmu-emul.c @@ -888,9 +888,6 @@ int kvm_arm_pmu_v3_enable(struct kvm_vcpu *vcpu) return -EINVAL; } =20 - /* One-off reload of the PMU on first run */ - kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); - return 0; } =20 diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 27418dac791df9a89124f867879e899db175e506..51054b7befc0b4bd822cecf717e= e4a4740c4a685 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1162,6 +1162,8 @@ static int set_pmreg(struct kvm_vcpu *vcpu, const str= uct sys_reg_desc *r, u64 va else __vcpu_sys_reg(vcpu, r->reg) &=3D ~val; =20 + kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); 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Fri, 07 Mar 2025 02:55:47 -0800 (PST) Received: from localhost ([157.82.205.237]) by smtp.gmail.com with UTF8SMTPSA id d2e1a72fcca58-736985191cfsm3016761b3a.145.2025.03.07.02.55.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 07 Mar 2025 02:55:47 -0800 (PST) From: Akihiko Odaki Date: Fri, 07 Mar 2025 19:55:30 +0900 Subject: [PATCH v2 3/3] KVM: arm64: PMU: Set raw values from user to PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR} Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250307-pmc-v2-3-6c3375a5f1e4@daynix.com> References: <20250307-pmc-v2-0-6c3375a5f1e4@daynix.com> In-Reply-To: <20250307-pmc-v2-0-6c3375a5f1e4@daynix.com> To: Marc Zyngier , Oliver Upton , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Catalin Marinas , Will Deacon , Andrew Jones , Shannon Zhao Cc: linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, devel@daynix.com, Akihiko Odaki X-Mailer: b4 0.14.2 Commit a45f41d754e0 ("KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CLR}, PMOVS{SET,CLR}") changed KVM_SET_ONE_REG to update the mentioned registers in a way matching with the behavior of guest register writes. This is a breaking change of a UAPI though the new semantics looks cleaner and VMMs are not prepared for this. Firecracker, QEMU, and crosvm perform migration by listing registers with KVM_GET_REG_LIST, getting their values with KVM_GET_ONE_REG and setting them with KVM_SET_ONE_REG. This algorithm assumes KVM_SET_ONE_REG restores the values retrieved with KVM_GET_ONE_REG without any alteration. However, bit operations added by the earlier commit do not preserve the values retried with KVM_GET_ONE_REG and potentially break migration. Remove the bit operations that alter the values retrieved with KVM_GET_ONE_REG. Fixes: a45f41d754e0 ("KVM: arm64: Add {get,set}_user for PM{C,I}NTEN{SET,CL= R}, PMOVS{SET,CLR}") Signed-off-by: Akihiko Odaki Acked-by: Marc Zyngier --- arch/arm64/kvm/sys_regs.c | 21 +-------------------- 1 file changed, 1 insertion(+), 20 deletions(-) diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index 51054b7befc0b4bd822cecf717ee4a4740c4a685..2f44d4d4f54112787683dd75ea9= 3fd60e92dd31f 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1142,26 +1142,7 @@ static bool access_pmu_evtyper(struct kvm_vcpu *vcpu= , struct sys_reg_params *p, =20 static int set_pmreg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r, = u64 val) { - bool set; - - val &=3D kvm_pmu_valid_counter_mask(vcpu); - - switch (r->reg) { - case PMOVSSET_EL0: - /* CRm[1] being set indicates a SET register, and CLR otherwise */ - set =3D r->CRm & 2; - break; - default: - /* Op2[0] being set indicates a SET register, and CLR otherwise */ - set =3D r->Op2 & 1; - break; - } - - if (set) - __vcpu_sys_reg(vcpu, r->reg) |=3D val; - else - __vcpu_sys_reg(vcpu, r->reg) &=3D ~val; - + __vcpu_sys_reg(vcpu, r->reg) =3D val & kvm_pmu_valid_counter_mask(vcpu); kvm_make_request(KVM_REQ_RELOAD_PMU, vcpu); =20 return 0; --=20 2.48.1