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Fri, 07 Mar 2025 02:29:25 -0800 (PST) From: Peter Griffin Date: Fri, 07 Mar 2025 10:29:05 +0000 Subject: [PATCH v4 1/4] pinctrl: samsung: add support for eint_fltcon_offset Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250307-pinctrl-fltcon-suspend-v4-1-2d775e486036@linaro.org> References: <20250307-pinctrl-fltcon-suspend-v4-0-2d775e486036@linaro.org> In-Reply-To: <20250307-pinctrl-fltcon-suspend-v4-0-2d775e486036@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, kernel-team@android.com, jaewon02.kim@samsung.com, Peter Griffin , stable@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA On gs101 SoC the fltcon0 (filter configuration 0) offset isn't at a fixed offset like previous SoCs as the fltcon1 register only exists when there are more than 4 pins in the bank. Add a eint_fltcon_offset and new GS101_PIN_BANK_EINT* macros that take an additional fltcon_offs variable. This can then be used in suspend/resume callbacks to save and restore the fltcon0 and fltcon1 registers. Fixes: 4a8be01a1a7a ("pinctrl: samsung: Add gs101 SoC pinctrl configuration= ") Cc: stable@vger.kernel.org Reviewed-by: Andr=C3=A9 Draszik Signed-off-by: Peter Griffin --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 98 +++++++++++++---------= ---- drivers/pinctrl/samsung/pinctrl-exynos.h | 22 ++++++ drivers/pinctrl/samsung/pinctrl-samsung.c | 1 + drivers/pinctrl/samsung/pinctrl-samsung.h | 4 ++ 4 files changed, 76 insertions(+), 49 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index 3ea7106ce5eae3c21f11790b5a40037042c1d407..e28fe81776466b693417c66bb15= 752d609b79eb1 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1370,83 +1370,83 @@ const struct samsung_pinctrl_of_match_data fsd_of_d= ata __initconst =3D { =20 /* pin banks of gs101 pin-controller (ALIVE) */ static const struct samsung_pin_bank_data gs101_pin_alive[] =3D { - EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00), - EXYNOS850_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04), - EXYNOS850_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08), - EXYNOS850_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c), - EXYNOS850_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10), - EXYNOS850_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14), - EXYNOS850_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18), - EXYNOS850_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c), + GS101_PIN_BANK_EINTW(8, 0x0, "gpa0", 0x00, 0x00), + GS101_PIN_BANK_EINTW(7, 0x20, "gpa1", 0x04, 0x08), + GS101_PIN_BANK_EINTW(5, 0x40, "gpa2", 0x08, 0x10), + GS101_PIN_BANK_EINTW(4, 0x60, "gpa3", 0x0c, 0x18), + GS101_PIN_BANK_EINTW(4, 0x80, "gpa4", 0x10, 0x1c), + GS101_PIN_BANK_EINTW(7, 0xa0, "gpa5", 0x14, 0x20), + GS101_PIN_BANK_EINTW(8, 0xc0, "gpa9", 0x18, 0x28), + GS101_PIN_BANK_EINTW(2, 0xe0, "gpa10", 0x1c, 0x30), }; =20 /* pin banks of gs101 pin-controller (FAR_ALIVE) */ static const struct samsung_pin_bank_data gs101_pin_far_alive[] =3D { - EXYNOS850_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00), - EXYNOS850_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04), - EXYNOS850_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08), - EXYNOS850_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c), + GS101_PIN_BANK_EINTW(8, 0x0, "gpa6", 0x00, 0x00), + GS101_PIN_BANK_EINTW(4, 0x20, "gpa7", 0x04, 0x08), + GS101_PIN_BANK_EINTW(8, 0x40, "gpa8", 0x08, 0x0c), + GS101_PIN_BANK_EINTW(2, 0x60, "gpa11", 0x0c, 0x14), }; =20 /* pin banks of gs101 pin-controller (GSACORE) */ static const struct samsung_pin_bank_data gs101_pin_gsacore[] =3D { - EXYNOS850_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00), - EXYNOS850_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04), - EXYNOS850_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08), + GS101_PIN_BANK_EINTG(2, 0x0, "gps0", 0x00, 0x00), + GS101_PIN_BANK_EINTG(8, 0x20, "gps1", 0x04, 0x04), + GS101_PIN_BANK_EINTG(3, 0x40, "gps2", 0x08, 0x0c), }; =20 /* pin banks of gs101 pin-controller (GSACTRL) */ static const struct samsung_pin_bank_data gs101_pin_gsactrl[] =3D { - EXYNOS850_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00), + GS101_PIN_BANK_EINTW(6, 0x0, "gps3", 0x00, 0x00), }; =20 /* pin banks of gs101 pin-controller (PERIC0) */ static const struct samsung_pin_bank_data gs101_pin_peric0[] =3D { - EXYNOS850_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00), - EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04), - EXYNOS850_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08), - EXYNOS850_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c), - EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10), - EXYNOS850_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14), - EXYNOS850_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18), - EXYNOS850_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c), - EXYNOS850_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20), - EXYNOS850_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24), - EXYNOS850_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28), - EXYNOS850_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c), - EXYNOS850_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30), - EXYNOS850_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34), - EXYNOS850_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38), - EXYNOS850_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c), - EXYNOS850_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40), - EXYNOS850_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44), - EXYNOS850_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48), - EXYNOS850_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c), + GS101_PIN_BANK_EINTG(5, 0x0, "gpp0", 0x00, 0x00), + GS101_PIN_BANK_EINTG(4, 0x20, "gpp1", 0x04, 0x08), + GS101_PIN_BANK_EINTG(4, 0x40, "gpp2", 0x08, 0x0c), + GS101_PIN_BANK_EINTG(2, 0x60, "gpp3", 0x0c, 0x10), + GS101_PIN_BANK_EINTG(4, 0x80, "gpp4", 0x10, 0x14), + GS101_PIN_BANK_EINTG(2, 0xa0, "gpp5", 0x14, 0x18), + GS101_PIN_BANK_EINTG(4, 0xc0, "gpp6", 0x18, 0x1c), + GS101_PIN_BANK_EINTG(2, 0xe0, "gpp7", 0x1c, 0x20), + GS101_PIN_BANK_EINTG(4, 0x100, "gpp8", 0x20, 0x24), + GS101_PIN_BANK_EINTG(2, 0x120, "gpp9", 0x24, 0x28), + GS101_PIN_BANK_EINTG(4, 0x140, "gpp10", 0x28, 0x2c), + GS101_PIN_BANK_EINTG(2, 0x160, "gpp11", 0x2c, 0x30), + GS101_PIN_BANK_EINTG(4, 0x180, "gpp12", 0x30, 0x34), + GS101_PIN_BANK_EINTG(2, 0x1a0, "gpp13", 0x34, 0x38), + GS101_PIN_BANK_EINTG(4, 0x1c0, "gpp14", 0x38, 0x3c), + GS101_PIN_BANK_EINTG(2, 0x1e0, "gpp15", 0x3c, 0x40), + GS101_PIN_BANK_EINTG(4, 0x200, "gpp16", 0x40, 0x44), + GS101_PIN_BANK_EINTG(2, 0x220, "gpp17", 0x44, 0x48), + GS101_PIN_BANK_EINTG(4, 0x240, "gpp18", 0x48, 0x4c), + GS101_PIN_BANK_EINTG(4, 0x260, "gpp19", 0x4c, 0x50), }; =20 /* pin banks of gs101 pin-controller (PERIC1) */ static const struct samsung_pin_bank_data gs101_pin_peric1[] =3D { - EXYNOS850_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00), - EXYNOS850_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04), - EXYNOS850_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08), - EXYNOS850_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c), - EXYNOS850_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10), - EXYNOS850_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14), - EXYNOS850_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18), - EXYNOS850_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c), + GS101_PIN_BANK_EINTG(8, 0x0, "gpp20", 0x00, 0x00), + GS101_PIN_BANK_EINTG(4, 0x20, "gpp21", 0x04, 0x08), + GS101_PIN_BANK_EINTG(2, 0x40, "gpp22", 0x08, 0x0c), + GS101_PIN_BANK_EINTG(8, 0x60, "gpp23", 0x0c, 0x10), + GS101_PIN_BANK_EINTG(4, 0x80, "gpp24", 0x10, 0x18), + GS101_PIN_BANK_EINTG(4, 0xa0, "gpp25", 0x14, 0x1c), + GS101_PIN_BANK_EINTG(5, 0xc0, "gpp26", 0x18, 0x20), + GS101_PIN_BANK_EINTG(4, 0xe0, "gpp27", 0x1c, 0x28), }; =20 /* pin banks of gs101 pin-controller (HSI1) */ static const struct samsung_pin_bank_data gs101_pin_hsi1[] =3D { - EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00), - EXYNOS850_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04), + GS101_PIN_BANK_EINTG(6, 0x0, "gph0", 0x00, 0x00), + GS101_PIN_BANK_EINTG(7, 0x20, "gph1", 0x04, 0x08), }; =20 /* pin banks of gs101 pin-controller (HSI2) */ static const struct samsung_pin_bank_data gs101_pin_hsi2[] =3D { - EXYNOS850_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00), - EXYNOS850_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04), - EXYNOS850_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08), + GS101_PIN_BANK_EINTG(6, 0x0, "gph2", 0x00, 0x00), + GS101_PIN_BANK_EINTG(2, 0x20, "gph3", 0x04, 0x08), + GS101_PIN_BANK_EINTG(6, 0x40, "gph4", 0x08, 0x0c), }; =20 static const struct samsung_pin_ctrl gs101_pin_ctrl[] __initconst =3D { diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/sam= sung/pinctrl-exynos.h index 7b7ff7ffeb56bdde2504ec90c8df13bdd1ace70e..33df21d5c9d61e852834031570d= 4a0ac0e51f6a4 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -175,6 +175,28 @@ .name =3D id \ } =20 +#define GS101_PIN_BANK_EINTG(pins, reg, id, offs, fltcon_offs) \ + { \ + .type =3D &exynos850_bank_type_off, \ + .pctl_offset =3D reg, \ + .nr_pins =3D pins, \ + .eint_type =3D EINT_TYPE_GPIO, \ + .eint_offset =3D offs, \ + .eint_fltcon_offset =3D fltcon_offs, \ + .name =3D id \ + } + +#define GS101_PIN_BANK_EINTW(pins, reg, id, offs, fltcon_offs) \ + { \ + .type =3D &exynos850_bank_type_alive, \ + .pctl_offset =3D reg, \ + .nr_pins =3D pins, \ + .eint_type =3D EINT_TYPE_WKUP, \ + .eint_offset =3D offs, \ + .eint_fltcon_offset =3D fltcon_offs, \ + .name =3D id \ + } + /** * struct exynos_weint_data: irq specific data for all the wakeup interrup= ts * generated by the external wakeup interrupt controller. diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/sa= msung/pinctrl-samsung.c index cfced7afd4ca6e99c7e72a588d780f0542990ed9..963060920301ec90affb2ee6d75= 8d3d602ffb4a9 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1230,6 +1230,7 @@ samsung_pinctrl_get_soc_data(struct samsung_pinctrl_d= rv_data *d, bank->eint_con_offset =3D bdata->eint_con_offset; bank->eint_mask_offset =3D bdata->eint_mask_offset; bank->eint_pend_offset =3D bdata->eint_pend_offset; + bank->eint_fltcon_offset =3D bdata->eint_fltcon_offset; bank->name =3D bdata->name; =20 raw_spin_lock_init(&bank->slock); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index bb0689d52ea0b4392714fa9bcdcbae8d253c73a1..371e4f02bbfb375964b7833beb9= bbc098a51f4a3 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -144,6 +144,7 @@ struct samsung_pin_bank_type { * @eint_con_offset: ExynosAuto SoC-specific EINT control register offset = of bank. * @eint_mask_offset: ExynosAuto SoC-specific EINT mask register offset of= bank. * @eint_pend_offset: ExynosAuto SoC-specific EINT pend register offset of= bank. + * @eint_fltcon_offset: GS101 SoC-specific EINT filter config register off= set. * @name: name to be prefixed for each pin in this pin bank. */ struct samsung_pin_bank_data { @@ -158,6 +159,7 @@ struct samsung_pin_bank_data { u32 eint_con_offset; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA gs101 needs it's own suspend/resume callbacks to use the newly added eint_fltcon_offset for saving & restoring fltcon0 & fltcon1 registers. It also differs to previous SoCs in that fltcon1 register doesn't always exist for each bank. exynosautov920 also has dedicated logic for using eint_con_offset and eint_mask_offset for saving & restoring it's registers. Refactor the existing platform specific suspend/resume callback so that each SoC variant has their own callback containing the SoC specific logic. Additionally we now call drvdata->suspend() & drvdata->resume() from within the loop that iterates the banks in samsung_pinctrl_suspend() and samsung_pinctrl_resume(). This simplifies the logic, and allows us to remove the clk_enable() and clk_disable() from the callbacks. Reviewed-by: Andr=C3=A9 Draszik Signed-off-by: Peter Griffin --- Changes since v3: * save->eint_fltcon1 is an argument to pr_debug(), not readl() change alignment accordingly (Andre) Changes since v2: * Remove useless init (Andre) * make it clear set_wakeup is conditional on bank->eint_type (Andre) Changes since v1: * Split code refactor & gs101 parts into separate patches (Andre) --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 28 ++-- drivers/pinctrl/samsung/pinctrl-exynos.c | 201 ++++++++++-----------= ---- drivers/pinctrl/samsung/pinctrl-exynos.h | 6 +- drivers/pinctrl/samsung/pinctrl-samsung.c | 11 +- drivers/pinctrl/samsung/pinctrl-samsung.h | 8 +- 5 files changed, 109 insertions(+), 145 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index e28fe81776466b693417c66bb15752d609b79eb1..57c98d2451b54b00d50e0e948e2= 72ed53d386c34 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1112,8 +1112,8 @@ static const struct samsung_pin_ctrl exynosautov920_p= in_ctrl[] =3D { .pin_banks =3D exynosautov920_pin_banks0, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks0), .eint_wkup_init =3D exynos_eint_wkup_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, .retention_data =3D &exynosautov920_retention_data, }, { /* pin-controller instance 1 AUD data */ @@ -1124,43 +1124,43 @@ static const struct samsung_pin_ctrl exynosautov920= _pin_ctrl[] =3D { .pin_banks =3D exynosautov920_pin_banks2, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks2), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 3 HSI1 data */ .pin_banks =3D exynosautov920_pin_banks3, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks3), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 4 HSI2 data */ .pin_banks =3D exynosautov920_pin_banks4, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks4), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 5 HSI2UFS data */ .pin_banks =3D exynosautov920_pin_banks5, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks5), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 6 PERIC0 data */ .pin_banks =3D exynosautov920_pin_banks6, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks6), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 7 PERIC1 data */ .pin_banks =3D exynosautov920_pin_banks7, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks7), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, }; =20 diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/sam= sung/pinctrl-exynos.c index ac6dc22b37c98ed5b7fca3335764f19abb2f71cc..75b9ab19e4e8f81bf85cd755734= 85b7f2e717e7b 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -761,153 +761,114 @@ __init int exynos_eint_wkup_init(struct samsung_pin= ctrl_drv_data *d) return 0; } =20 -static void exynos_pinctrl_suspend_bank( - struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) +static void exynos_set_wakeup(struct samsung_pin_bank *bank) { - struct exynos_eint_gpio_save *save =3D bank->soc_priv; - const void __iomem *regs =3D bank->eint_base; + struct exynos_irq_chip *irq_chip; =20 - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for saving state\n"); - return; + if (bank->irq_chip) { + irq_chip =3D bank->irq_chip; + irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); } - - save->eint_con =3D readl(regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset); - save->eint_fltcon0 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset); - save->eint_fltcon1 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4); - save->eint_mask =3D readl(regs + bank->irq_chip->eint_mask - + bank->eint_offset); - - clk_disable(bank->drvdata->pclk); - - pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); - pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); - pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); - pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); } =20 -static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_dat= a *drvdata, - struct samsung_pin_bank *bank) +void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; const void __iomem *regs =3D bank->eint_base; =20 - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for saving state\n"); - return; - } - - save->eint_con =3D readl(regs + bank->pctl_offset + bank->eint_con_offset= ); - save->eint_mask =3D readl(regs + bank->pctl_offset + bank->eint_mask_offs= et); - - clk_disable(bank->drvdata->pclk); - - pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); - pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + save->eint_con =3D readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + save->eint_fltcon0 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + save->eint_fltcon1 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + save->eint_mask =3D readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); + + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", + bank->name, save->eint_fltcon0); + pr_debug("%s: save fltcon1 %#010x\n", + bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) + exynos_set_wakeup(bank); } =20 -void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) +void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) { - struct samsung_pin_bank *bank =3D drvdata->pin_banks; - struct exynos_irq_chip *irq_chip =3D NULL; - int i; + struct exynos_eint_gpio_save *save =3D bank->soc_priv; + const void __iomem *regs =3D bank->eint_base; =20 - for (i =3D 0; i < drvdata->nr_banks; ++i, ++bank) { - if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { - if (bank->eint_con_offset) - exynosauto_pinctrl_suspend_bank(drvdata, bank); - else - exynos_pinctrl_suspend_bank(drvdata, bank); - } - else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) { - if (!irq_chip) { - irq_chip =3D bank->irq_chip; - irq_chip->set_eint_wakeup_mask(drvdata, - irq_chip); - } - } - } + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + save->eint_con =3D readl(regs + bank->pctl_offset + + bank->eint_con_offset); + save->eint_mask =3D readl(regs + bank->pctl_offset + + bank->eint_mask_offset); + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) + exynos_set_wakeup(bank); } =20 -static void exynos_pinctrl_resume_bank( - struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) +void exynos_pinctrl_resume(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; void __iomem *regs =3D bank->eint_base; =20 - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for restoring state\n"); - return; + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset), save->eint_fltcon0); + pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4), + save->eint_fltcon1); + pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); } - - pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset), save->eint_con); - pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset), save->eint_fltcon0); - pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4), save->eint_fltcon1); - pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, - readl(regs + bank->irq_chip->eint_mask - + bank->eint_offset), save->eint_mask); - - writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset); - writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset); - writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4); - writel(save->eint_mask, regs + bank->irq_chip->eint_mask - + bank->eint_offset); - - clk_disable(bank->drvdata->pclk); } =20 -static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data= *drvdata, - struct samsung_pin_bank *bank) +void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; void __iomem *regs =3D bank->eint_base; =20 - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for restoring state\n"); - return; + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + /* exynosautov920 has eint_con_offset for all but one bank */ + if (!bank->eint_con_offset) + exynos_pinctrl_resume(bank); + + pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, + readl(regs + bank->pctl_offset + bank->eint_con_offset), + save->eint_con); + pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, + readl(regs + bank->pctl_offset + + bank->eint_mask_offset), save->eint_mask); + + writel(save->eint_con, + regs + bank->pctl_offset + bank->eint_con_offset); + writel(save->eint_mask, + regs + bank->pctl_offset + bank->eint_mask_offset); } - - pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, - readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con= ); - pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, - readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_ma= sk); - - writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); - writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset= ); - - clk_disable(bank->drvdata->pclk); -} - -void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) -{ - struct samsung_pin_bank *bank =3D drvdata->pin_banks; - int i; - - for (i =3D 0; i < drvdata->nr_banks; ++i, ++bank) - if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { - if (bank->eint_con_offset) - exynosauto_pinctrl_resume_bank(drvdata, bank); - else - exynos_pinctrl_resume_bank(drvdata, bank); - } } =20 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvda= ta) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/sam= sung/pinctrl-exynos.h index 33df21d5c9d61e852834031570d4a0ac0e51f6a4..35c2bc4ea488bda600ebfbda149= 2f5f49dbd9849 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -221,8 +221,10 @@ struct exynos_muxed_weint_data { =20 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); -void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); -void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); +void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank); +void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank); +void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); +void exynos_pinctrl_resume(struct samsung_pin_bank *bank); struct samsung_retention_ctrl * exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, const struct samsung_retention_data *data); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/sa= msung/pinctrl-samsung.c index 963060920301ec90affb2ee6d758d3d602ffb4a9..375634d8cc79d6533603e3eed56= 2452181e2ee25 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1349,6 +1349,9 @@ static int __maybe_unused samsung_pinctrl_suspend(str= uct device *dev) const u8 *widths =3D bank->type->fld_width; enum pincfg_type type; =20 + if (drvdata->suspend) + drvdata->suspend(bank); + /* Registers without a powerdown config aren't lost */ if (!widths[PINCFG_TYPE_CON_PDN]) continue; @@ -1373,8 +1376,6 @@ static int __maybe_unused samsung_pinctrl_suspend(str= uct device *dev) =20 clk_disable(drvdata->pclk); =20 - if (drvdata->suspend) - drvdata->suspend(drvdata); if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable) drvdata->retention_ctrl->enable(drvdata); =20 @@ -1406,9 +1407,6 @@ static int __maybe_unused samsung_pinctrl_resume(stru= ct device *dev) return ret; } =20 - if (drvdata->resume) - drvdata->resume(drvdata); - for (i =3D 0; i < drvdata->nr_banks; i++) { struct samsung_pin_bank *bank =3D &drvdata->pin_banks[i]; void __iomem *reg =3D bank->pctl_base + bank->pctl_offset; @@ -1416,6 +1414,9 @@ static int __maybe_unused samsung_pinctrl_resume(stru= ct device *dev) const u8 *widths =3D bank->type->fld_width; enum pincfg_type type; =20 + if (drvdata->resume) + drvdata->resume(bank); + /* Registers without a powerdown config aren't lost */ if (!widths[PINCFG_TYPE_CON_PDN]) continue; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index 371e4f02bbfb375964b7833beb9bbc098a51f4a3..e939e5bb0347458ae4a9014fd96= 57fc59c5c3994 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -285,8 +285,8 @@ struct samsung_pin_ctrl { int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA gs101 differs to other SoCs in that fltcon1 register doesn't always exist. Additionally the offset of fltcon0 is not fixed and needs to use the newly added eint_fltcon_offset variable. Fixes: 4a8be01a1a7a ("pinctrl: samsung: Add gs101 SoC pinctrl configuration= ") Cc: stable@vger.kernel.org Reviewed-by: Andr=C3=A9 Draszik Signed-off-by: Peter Griffin --- Changes since v2: * make it clear exynos_set_wakeup(bank) is conditional on bank type (Andre) * align style where the '+' is placed (Andre) * remove unnecessary braces (Andre) --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 24 ++++----- drivers/pinctrl/samsung/pinctrl-exynos.c | 70 ++++++++++++++++++++++= ++++ drivers/pinctrl/samsung/pinctrl-exynos.h | 2 + 3 files changed, 84 insertions(+), 12 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index 57c98d2451b54b00d50e0e948e272ed53d386c34..fca447ebc5f5956b7e8d2f2d08f= 23622095b1ee6 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1455,15 +1455,15 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl= [] __initconst =3D { .pin_banks =3D gs101_pin_alive, .nr_banks =3D ARRAY_SIZE(gs101_pin_alive), .eint_wkup_init =3D exynos_eint_wkup_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (FAR_ALIVE) */ .pin_banks =3D gs101_pin_far_alive, .nr_banks =3D ARRAY_SIZE(gs101_pin_far_alive), .eint_wkup_init =3D exynos_eint_wkup_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (GSACORE) */ .pin_banks =3D gs101_pin_gsacore, @@ -1477,29 +1477,29 @@ static const struct samsung_pin_ctrl gs101_pin_ctrl= [] __initconst =3D { .pin_banks =3D gs101_pin_peric0, .nr_banks =3D ARRAY_SIZE(gs101_pin_peric0), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (PERIC1) */ .pin_banks =3D gs101_pin_peric1, .nr_banks =3D ARRAY_SIZE(gs101_pin_peric1), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (HSI1) */ .pin_banks =3D gs101_pin_hsi1, .nr_banks =3D ARRAY_SIZE(gs101_pin_hsi1), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, { /* pin banks of gs101 pin-controller (HSI2) */ .pin_banks =3D gs101_pin_hsi2, .nr_banks =3D ARRAY_SIZE(gs101_pin_hsi2), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D gs101_pinctrl_suspend, + .resume =3D gs101_pinctrl_resume, }, }; =20 diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/sam= sung/pinctrl-exynos.c index 75b9ab19e4e8f81bf85cd75573485b7f2e717e7b..5f0045d03346600557fa6735bad= 709897c71935c 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -798,6 +798,40 @@ void exynos_pinctrl_suspend(struct samsung_pin_bank *b= ank) exynos_set_wakeup(bank); } =20 +void gs101_pinctrl_suspend(struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save =3D bank->soc_priv; + const void __iomem *regs =3D bank->eint_base; + + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + save->eint_con =3D readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + + save->eint_fltcon0 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset); + + /* fltcon1 register only exists for pins 4-7 */ + if (bank->nr_pins > 4) + save->eint_fltcon1 =3D readl(regs + + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset + 4); + + save->eint_mask =3D readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); + + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", + bank->name, save->eint_fltcon0); + if (bank->nr_pins > 4) + pr_debug("%s: save fltcon1 %#010x\n", + bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) + exynos_set_wakeup(bank); +} + void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; @@ -816,6 +850,42 @@ void exynosautov920_pinctrl_suspend(struct samsung_pin= _bank *bank) exynos_set_wakeup(bank); } =20 +void gs101_pinctrl_resume(struct samsung_pin_bank *bank) +{ + struct exynos_eint_gpio_save *save =3D bank->soc_priv; + + void __iomem *regs =3D bank->eint_base; + void __iomem *eint_fltcfg0 =3D regs + EXYNOS_GPIO_EFLTCON_OFFSET + + bank->eint_fltcon_offset; + + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + + pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, + readl(eint_fltcfg0), save->eint_fltcon0); + + /* fltcon1 register only exists for pins 4-7 */ + if (bank->nr_pins > 4) + pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, + readl(eint_fltcfg0 + 4), save->eint_fltcon1); + + pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, eint_fltcfg0); + + if (bank->nr_pins > 4) + writel(save->eint_fltcon1, eint_fltcfg0 + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); + } +} + void exynos_pinctrl_resume(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/sam= sung/pinctrl-exynos.h index 35c2bc4ea488bda600ebfbda1492f5f49dbd9849..773f161a82a38cbaad05fcbc09a= 936300f5c7595 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -225,6 +225,8 @@ void exynosautov920_pinctrl_resume(struct samsung_pin_b= ank *bank); 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA Newer Exynos based SoCs have a filter selection bitfield in the filter configuration registers on alive bank pins. This allows the selection of a digital or analog delay filter for each pin. Add support for selecting and enabling the filter. On suspend we set the analog filter to all pins in the bank (as the digital filter relies on a clock). On resume the digital filter is reapplied to all pins in the bank. The digital filter is working via a clock and has an adjustable filter delay flt_width bitfield, whereas the analog filter uses a fixed delay. The filter determines to what extent signal fluctuations received through the pad are considered glitches. The code path can be exercised using echo mem > /sys/power/state And then wake the device using a eint gpio Reviewed-by: Andr=C3=A9 Draszik Signed-off-by: Peter Griffin --- Changes since v2: * Ensure EXYNOS_FLTCON_DIGITAL bit is cleared (Andre) * Make it obvious that exynos_eint_set_filter() is conditional on bank type= (Andre) Changes since v1: * Remove eint_flt_selectable bool as it can be deduced from EINT_TYPE_WKUP = (Peter) * Move filter config comment to header (Andre) * Rename EXYNOS_FLTCON_DELAY to EXYNOS_FLTCON_ANALOG (Andre) * Remove misleading old comment (Andre) * Refactor exynos_eint_update_flt_reg() into a loop (Andre) Note: this patch was previously sent as part of the initial gs101/ Pixel 6 series and was dropped in v6. This new version incorporates the review feedback from Sam Protsenko here in v5. Link: https://lore.kernel.org/all/20231201160925.3136868-1-peter.griffin@li= naro.org/T/#m79ced98939e895c840d812c8b4c2b3f33ce604c8 Changes since previous version * Drop fltcon_type enum and use bool eint_flt_selectable (Sam) * Refactor and add exynos_eint_update_flt_reg() (Sam) * Rename function to exynos_eint_set_filter() for easier readability (Sam) * Remove comments and `if bank->fltcon_type !=3D FLT_DEFAULT)` checks and i= ndentation (Sam) --- drivers/pinctrl/samsung/pinctrl-exynos.c | 37 ++++++++++++++++++++++++++++= +++- drivers/pinctrl/samsung/pinctrl-exynos.h | 20 +++++++++++++++++ 2 files changed, 56 insertions(+), 1 deletion(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/sam= sung/pinctrl-exynos.c index 5f0045d03346600557fa6735bad709897c71935c..1d2a4f4b825fce4be3f3d337145= f2a4128315f0b 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -369,6 +369,37 @@ struct exynos_eint_gpio_save { u32 eint_mask; }; =20 +static void exynos_eint_update_flt_reg(void __iomem *reg, int cnt, int con) +{ + unsigned int val, shift; + int i; + + val =3D readl(reg); + for (i =3D 0; i < cnt; i++) { + shift =3D i * EXYNOS_FLTCON_LEN; + val &=3D ~(EXYNOS_FLTCON_DIGITAL << shift); + val |=3D con << shift; + } + writel(val, reg); +} + +/* + * Set the desired filter (digital or analog delay) and enable it to + * every pin in the bank. Note the filter selection bitfield is only + * found on alive banks. The filter determines to what extent signal + * fluctuations received through the pad are considered glitches. + */ +static void exynos_eint_set_filter(struct samsung_pin_bank *bank, int filt= er) +{ + unsigned int off =3D EXYNOS_GPIO_EFLTCON_OFFSET + bank->eint_fltcon_offse= t; + void __iomem *reg =3D bank->drvdata->virt_base + off; + unsigned int con =3D EXYNOS_FLTCON_EN | filter; + + for (int n =3D 0; n < bank->nr_pins; n +=3D 4) + exynos_eint_update_flt_reg(reg + n, + min(bank->nr_pins - n, 4), con); +} + /* * exynos_eint_gpio_init() - setup handling of external gpio interrupts. * @d: driver data of samsung pinctrl driver. @@ -828,8 +859,10 @@ void gs101_pinctrl_suspend(struct samsung_pin_bank *ba= nk) bank->name, save->eint_fltcon1); pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); - } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) + } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) { exynos_set_wakeup(bank); + exynos_eint_set_filter(bank, EXYNOS_FLTCON_ANALOG); + } } =20 void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) @@ -883,6 +916,8 @@ void gs101_pinctrl_resume(struct samsung_pin_bank *bank) writel(save->eint_fltcon1, eint_fltcfg0 + 4); writel(save->eint_mask, regs + bank->irq_chip->eint_mask + bank->eint_offset); + } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) { + exynos_eint_set_filter(bank, EXYNOS_FLTCON_DIGITAL); } } =20 diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/sam= sung/pinctrl-exynos.h index 773f161a82a38cbaad05fcbc09a936300f5c7595..66acbd08d3445ca6ee7358d3c4a= 6cb2be5d82842 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -52,6 +52,26 @@ #define EXYNOS_EINT_MAX_PER_BANK 8 #define EXYNOS_EINT_NR_WKUP_EINT =20 +/* + * EINT filter configuration register (on alive banks) has + * the following layout. + * + * BitfieldName[PinNum][Bit:Bit] + * FLT_EN[3][31] FLT_SEL[3][30] FLT_WIDTH[3][29:24] + * FLT_EN[2][23] FLT_SEL[2][22] FLT_WIDTH[2][21:16] + * FLT_EN[1][15] FLT_SEL[1][14] FLT_WIDTH[1][13:8] + * FLT_EN[0][7] FLT_SEL[0][6] FLT_WIDTH[0][5:0] + * + * FLT_EN 0x0 =3D Disable, 0x1=3DEnable + * FLT_SEL 0x0 =3D Analog delay filter, 0x1 Digital filter (clock count) + * FLT_WIDTH Filtering width. Valid when FLT_SEL is 0x1 + */ + +#define EXYNOS_FLTCON_EN BIT(7) +#define EXYNOS_FLTCON_DIGITAL BIT(6) +#define EXYNOS_FLTCON_ANALOG (0 << 6) +#define EXYNOS_FLTCON_LEN 8 + #define EXYNOS_PIN_BANK_EINTN(pins, reg, id) \ { \ .type =3D &bank_type_off, \ --=20 2.49.0.rc0.332.g42c0ae87b1-goog