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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 11/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2 Date: Thu, 6 Mar 2025 21:49:59 +0100 Message-ID: <20250306205000.227399-12-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV file from v2.0 to v2.2, as generated by the x86-cpuid-db project. * v2.1 changes summary: - Use a standardized style for all x86 trademarks, registers, opcodes, byte units, hexadecimal digits, and x86 technical terms. This was enforced by a number of x86-specfic hunspell(5) dictionary and affix files at the x86-cpuid-db project's CI pipeline. - Expand abbreviated terms that might be OK in code but not in official listings (e.g., "addr", "instr", "reg", "virt", etc.) - Add new Zen5 SoC bits to leaf 0x80000020 and leaf 0x80000021. * v2.2 changes summary: - Per Ingo Molnar's feedback on a related Linux kernel patch queue, it is desired to always use CPUID in its capitalized form. That quick v2.2 release fixed all instances of small case "cpuid" at the XML database, and thus the generated kcpuid CSV file. Signed-off-by: Ahmed S. Darwish Link: https://lkml.kernel.org/r/Z8hJhgGVduJWFqRE@lx-t490 Link: https://lkml.kernel.org/r/Z8bHK391zKE4gUEW@gmail.com --- Notes: No ANNOUNCE link for v2.2, as it was a very minor release and I didn't want to spam people inboxes. tools/arch/x86/kcpuid/cpuid.csv | 189 +++++++++++++++++--------------- 1 file changed, 100 insertions(+), 89 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index d0f7159f99ba..9613e09cbfb3 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v2.0 +# Generator: x86-cpuid-db v2.2 =20 # # Auto-generated file. @@ -12,7 +12,7 @@ # Leaf 0H # Maximum standard leaf number + CPU vendor string =20 - 0x0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported + 0x0, 0, eax, 31:0, max_std_leaf , Highest = standard CPUID leaf supported 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 @@ -28,7 +28,7 @@ 0x1, 0, eax, 27:20, ext_family , Extended= CPU family ID 0x1, 0, ebx, 7:0, brand_id , Brand in= dex 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size - 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count + 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU count 0x1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID 0x1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) 0x1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support @@ -41,7 +41,7 @@ 0x1, 0, ecx, 8, tm2 , Thermal = Monitor 2 0x1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 0x1, 0, ecx, 10, cid , L1 Conte= xt ID - 0x1, 0, ecx, 11, sdbg , Sillicon= Debug + 0x1, 0, ecx, 11, sdbg , Silicon = Debug 0x1, 0, ecx, 12, fma , FMA exte= nsions using YMM state 0x1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support 0x1, 0, ecx, 14, xtpr , xTPR Upd= ate Control @@ -89,13 +89,13 @@ 0x1, 0, edx, 27, ss , Self Sno= op 0x1, 0, edx, 28, ht , Hyper-th= reading 0x1, 0, edx, 29, tm , Thermal = Monitor - 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved + 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now reserved 0x1, 0, edx, 31, pbe , Pending = Break Enable =20 # Leaf 2H # Intel cache and TLB information one-byte descriptors =20 - 0x2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried + 0x2, 0, eax, 7:0, iteration_count , Number o= f times this leaf must be queried 0x2, 0, eax, 15:8, desc1 , Descript= or #1 0x2, 0, eax, 23:16, desc2 , Descript= or #2 0x2, 0, eax, 30:24, desc3 , Descript= or #3 @@ -129,7 +129,7 @@ =20 0x4, 31:0, eax, 4:0, cache_type , Cache ty= pe field 0x4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) - 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level + 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tializing cache level 0x4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache 0x4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache 0x4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package @@ -160,7 +160,7 @@ # Leaf 6H # Thermal and Power Management enumeration =20 - 0x6, 0, eax, 0, dtherm , Digital = temprature sensor + 0x6, 0, eax, 0, dtherm , Digital = temperature sensor 0x6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost 0x6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) 0x6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event @@ -187,13 +187,13 @@ 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting - 0x6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages - 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based + 0x6, 0, edx, 11:8, feedback_sz , Feedback= interface structure size, in 4K pages + 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU hardware feedback interface index =20 # Leaf 7H # Extended CPU features enumeration =20 - 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves + 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f leaf 0x7 subleaves 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported 0x7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) @@ -209,7 +209,7 @@ 0x7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring 0x7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) 0x7, 0, ebx, 14, mpx , Intel me= mory protection extensions - 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent + 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcement 0x7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions 0x7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions 0x7, 0, ebx, 18, rdseed , RDSEED i= nstruction @@ -220,27 +220,27 @@ 0x7, 0, ebx, 24, clwb , CLWB ins= truction 0x7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace 0x7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions - 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs - 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs + 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instructions + 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instructions 0x7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions - 0x7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions + 0x7, 0, ebx, 30, avx512bw , AVX-512 = byte/word instructions 0x7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions 0x7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) - 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs + 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instructions 0x7, 0, ecx, 2, umip , User mod= e instruction protection 0x7, 0, ecx, 3, pku , Protecti= on keys for user-space 0x7, 0, ecx, 4, ospke , OS prote= ction keys enable 0x7, 0, ecx, 5, waitpkg , WAITPKG = instructions - 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 + 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instructions group 2 0x7, 0, ecx, 7, cet_ss , CET shad= ow stack features 0x7, 0, ecx, 8, gfni , Galois f= ield new instructions - 0x7, 0, ecx, 9, vaes , Vector A= ES instrs + 0x7, 0, ecx, 9, vaes , Vector A= ES instructions 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support 0x7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions - 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle + 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bitwise algorithms 0x7, 0, ecx, 13, tme , Intel to= tal memory encryption - 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW - 0x7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) + 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DWORD/QWORD + 0x7, 0, ecx, 16, la57 , 57-bit l= inear addresses (five-level paging) 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode 0x7, 0, ecx, 22, rdpid , RDPID in= struction 0x7, 0, ecx, 23, key_locker , Intel ke= y locker support @@ -278,16 +278,16 @@ 0x7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable 0x7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions - 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions + 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bfloat16 instructions 0x7, 1, eax, 6, lass , Linear a= ddress space separation 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions - 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: leaf 0x23 is supported 0x7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB 0x7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB 0x7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions 0x7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS - 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) + 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instruction (WRMSR-non-serializing) 0x7, 1, eax, 20, nmi_src , NMI-sour= ce reporting with FRED event data 0x7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations 0x7, 1, eax, 22, hreset , History = reset support @@ -319,7 +319,7 @@ 0xa, 0, eax, 7:0, pmu_version , Performa= nce monitoring unit version ID 0xa, 0, eax, 15:8, pmu_n_gcounters , Number o= f general PMU counters per logical CPU 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth= of PMU general counters - 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length o= f cpuid leaf 0xa EBX bit vector + 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length o= f leaf 0xa EBX bit vector 0xa, 0, ebx, 0, no_core_cycle_evt , Core cyc= le event not available 0xa, 0, ebx, 1, no_insn_retired_evt , Instruct= ion retired event not available 0xa, 0, ebx, 2, no_refcycle_evt , Referenc= e cycles event not available @@ -348,18 +348,18 @@ 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87= (bit 0) supported 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE= (bit 1) supported 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX= (bit 2) supported - 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS (bit 3) supported (MPX BND0-BND3 regs) - 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) - 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK (bit 5) supported (AVX-512 k0-k7 regs) - 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) - 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) - 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U (bit 9) supported (XSAVE PKRU reg) - 0xd, 0, eax, 11, xcr0_cet_u , AMD XCR0= .CET_U (bit 11) supported (CET supervisor state) - 0xd, 0, eax, 12, xcr0_cet_s , AMD XCR0= .CET_S (bit 12) support (CET user state) + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS (bit 3) supported (MPX BND0-BND3 registers) + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK (bit 5) supported (AVX-512 k0-k7 registers) + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U (bit 9) supported (XSAVE PKRU registers) + 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET= _U (bit 11) supported (CET user state) + 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET= _S (bit 12) supported (CET supervisor state) 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TIL= ECONFIG (bit 17) supported (AMX can manage TILECONFIG) 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TIL= EDATA (bit 18) supported (AMX can manage TILEDATA) - 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XR= STR area byte size, for XCR0 enabled features - 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XR= STR area max byte size, all CPU features + 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XR= STOR area byte size, for XCR0 enabled features + 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XR= STOR area max byte size, all CPU features 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0= .LWP (bit 62) supported (Light-weight Profiling) 0xd, 1, eax, 0, xsaveopt , XSAVEOPT= instruction 0xd, 1, eax, 1, xsavec , XSAVEC i= nstruction @@ -378,7 +378,7 @@ 0xd, 63:2, eax, 31:0, xsave_sz , Size of = save area for subleaf-N feature, in bytes 0xd, 63:2, ebx, 31:0, xsave_offset , Offset o= f save area for subleaf-N feature, in bytes 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf = N describes an XSS bit, otherwise XCR0 bit - 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N feature xsave area is 64-byte aligned + 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N feature XSAVE area is 64-byte aligned =20 # Leaf FH # Intel RDT / AMD PQoS resource monitoring @@ -435,17 +435,17 @@ 0x12, 1, ecx, 0, xfrm_x87 , Enclave = XFRM.X87 (bit 0) supported 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SEE (bit 1) supported 0x12, 1, ecx, 2, xfrm_avx , Enclave = XFRM.AVX (bit 2) supported - 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs) - 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) - 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs) - 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) - 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) - 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (bit 9) supported (XSAVE PKRU reg) + 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) + 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) + 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) + 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) + 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) + 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (bit 9) supported (XSAVE PKRU registers) 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave = XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) 0x12, 1, ecx, 18, xfrm_tiledata , Enclave = XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA) 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf = type (dictates output layout) - 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sect= ion base addr, bits[12:31] - 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sect= ion base addr, bits[32:51] + 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sect= ion base address, bits[12:31] + 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sect= ion base address, bits[32:51] 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC sect= ion type / property encoding 0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC sect= ion size, bits[12:31] 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC sect= ion size, bits[32:51] @@ -453,7 +453,7 @@ # Leaf 14H # Intel Processor Trace enumeration =20 - 0x14, 0, eax, 31:0, pt_max_subleaf , Max cpui= d 0x14 subleaf + 0x14, 0, eax, 31:0, pt_max_subleaf , Maximum = leaf 0x14 subleaf 0x14, 0, ebx, 0, cr3_filtering , IA32_RTI= T_CR3_MATCH is accessible 0x14, 0, ebx, 1, psb_cyc , Configur= able PSB and cycle-accurate mode 0x14, 0, ebx, 2, ip_filtering , IP/Trace= Stop filtering; Warm-reset PT MSRs preservation @@ -481,7 +481,7 @@ 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core cry= stal clock nominal frequency, in Hz =20 # Leaf 16H -# Intel processor fequency enumeration +# Intel processor frequency enumeration =20 0x16, 0, eax, 15:0, cpu_base_mhz , Processo= r base frequency, in MHz 0x16, 0, ebx, 15:0, cpu_max_mhz , Processo= r max frequency, in MHz @@ -490,9 +490,9 @@ # Leaf 17H # Intel SoC vendor attributes enumeration =20 - 0x17, 0, eax, 31:0, soc_max_subleaf , Max cpui= d leaf 0x17 subleaf + 0x17, 0, eax, 31:0, soc_max_subleaf , Maximum = leaf 0x17 subleaf 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vend= or ID - 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumaeratoion scheme (not Intel) + 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumeration scheme (not Intel) 0x17, 0, ecx, 31:0, soc_proj_id , SoC proj= ect ID, assigned by vendor 0x17, 0, edx, 31:0, soc_stepping_id , Soc proj= ect stepping ID, assigned by vendor 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor B= rand ID string, bytes subleaf_nr * (0 -> 3) @@ -503,18 +503,18 @@ # Leaf 18H # Intel determenestic address translation (TLB) parameters =20 - 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Max cpui= d 0x18 subleaf + 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum = leaf 0x18 subleaf 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-= page entries supported 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-= page entries supported 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-= page entries supported 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-= page entries supported - 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/So= ft) partitioning between logical CPUs sharing this struct + 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/So= ft) partitioning between logical CPUs sharing this structure 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of = associativity 0x18, 31:0, ecx, 31:0, n_sets , Number o= f sets 0x18, 31:0, edx, 4:0, tlb_type , Translat= ion cache type (TLB type) 0x18, 31:0, edx, 7:5, tlb_cache_level , Translat= ion cache level (1-based) 0x18, 31:0, edx, 8, is_fully_associative , Fully-as= sociative structure - 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max num = of addressible IDs for logical CPUs sharing this TLB - 1 + 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max numb= er of addressable IDs for logical CPUs sharing this TLB - 1 =20 # Leaf 19H # Intel Key Locker enumeration @@ -577,7 +577,7 @@ # Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration =20 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL uni= t maximum height, K (rows or columns) - 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL uni= t maxiumum SIMD dimension, N (column bytes) + 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL uni= t maximum SIMD dimension, N (column bytes) =20 # Leaf 1FH # Intel extended topology enumeration v2 @@ -634,7 +634,7 @@ # Leaf 80000000H # Maximum extended leaf number + AMD/Transmeta CPU vendor string =20 -0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended cpuid leaf supported +0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended CPUID leaf supported 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor I= D string bytes 8 - 11 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor I= D string bytes 4 - 7 @@ -669,7 +669,7 @@ 0x80000001, 0, ecx, 17, tce , Translat= ion cache extension 0x80000001, 0, ecx, 19, nodeid_msr , NodeId M= SR (0xc001100c) 0x80000001, 0, ecx, 21, tbm , Trailing= bit manipulations -0x80000001, 0, ecx, 22, topoext , Topology= Extensions (cpuid leaf 0x8000001d) +0x80000001, 0, ecx, 22, topoext , Topology= Extensions (leaf 0x8000001d) 0x80000001, 0, ecx, 23, perfctr_core , Core per= formance counter extensions 0x80000001, 0, ecx, 24, perfctr_nb , NB/DF pe= rformance counter extensions 0x80000001, 0, ecx, 26, bpext , Data acc= ess breakpoint extension @@ -733,9 +733,9 @@ # Leaf 80000005H # AMD/Transmeta L1 cache and L1 TLB enumeration =20 -0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entires, 2M and 4M pages +0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entries, 2M and 4M pages 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages -0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB = #entires, 2M and 4M pages +0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB = #entries, 2M and 4M pages 0x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB = associativity, 2M and 4M pages 0x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB = #entries, 4K pages 0x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB = associativity, 4K pages @@ -774,11 +774,11 @@ # CPU power management (mostly AMD) and AMD RAS enumeration =20 0x80000007, 0, ebx, 0, overflow_recov , MCA over= flow conditions not fatal -0x80000007, 0, ebx, 1, succor , Software= containment of UnCORRectable errors +0x80000007, 0, ebx, 1, succor , Software= containment of uncorrectable errors 0x80000007, 0, ebx, 2, hw_assert , Hardware= assert MSRs 0x80000007, 0, ebx, 3, smca , Scalable= MCA (MCAX MSRs) 0x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU powe= r sample time ratio -0x80000007, 0, edx, 0, digital_temp , Digital = temprature sensor +0x80000007, 0, edx, 0, digital_temp , Digital = temperature sensor 0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW= ! frequency scaling 0x80000007, 0, edx, 2, powernow_volt_id , PowerNOW= ! voltage scaling 0x80000007, 0, edx, 3, thermal_trip , THERMTRI= P (Thermal Trip) @@ -821,7 +821,7 @@ 0x80000008, 0, ebx, 23, amd_ppin , Protecte= d Processor Inventory Number 0x80000008, 0, ebx, 24, amd_ssbd , Speculat= ive Store Bypass Disable 0x80000008, 0, ebx, 25, virt_ssbd , virtuali= zed SSBD (Speculative Store Bypass Disable) -0x80000008, 0, ebx, 26, amd_ssb_no , SSBD not= needed (fixed in HW) +0x80000008, 0, ebx, 26, amd_ssb_no , SSBD is = not needed (fixed in hardware) 0x80000008, 0, ebx, 27, cppc , Collabor= ative Processor Performance Control 0x80000008, 0, ebx, 28, amd_psfd , Predicti= ve Store Forward Disable 0x80000008, 0, ebx, 29, btc_no , CPU not = affected by Branch Type Confusion @@ -849,7 +849,7 @@ 0x8000000a, 0, edx, 10, pausefilter , Pause in= tercept filter 0x8000000a, 0, edx, 12, pfthreshold , Pause fi= lter threshold 0x8000000a, 0, edx, 13, avic , Advanced= virtual interrupt controller -0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual = VMSAVE/VMLOAD (nested virt) +0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual = VMSAVE/VMLOAD (nested virtualization) 0x8000000a, 0, edx, 16, vgif , Virtuali= ze the Global Interrupt Flag 0x8000000a, 0, edx, 17, gmet , Guest mo= de execution trap 0x8000000a, 0, edx, 18, x2avic , Virtual = x2APIC @@ -861,7 +861,7 @@ 0x8000000a, 0, edx, 25, vnmi , NMI virt= ualization 0x8000000a, 0, edx, 26, ibs_virt , IBS Virt= ualization 0x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended= LVT offset fault change -0x8000000a, 0, edx, 28, svme_addr_chk , Guest SV= ME addr check +0x8000000a, 0, edx, 28, svme_addr_chk , Guest SV= ME address check =20 # Leaf 80000019H # AMD TLB 1G-pages enumeration @@ -902,20 +902,20 @@ # AMD LWP (Lightweight Profiling) =20 0x8000001c, 0, eax, 0, os_lwp_avail , LWP is a= vailable to application programs (supported by OS) -0x8000001c, 0, eax, 1, os_lpwval , LWPVAL i= nstruction (EventId=3D1) is supported by OS -0x8000001c, 0, eax, 2, os_lwp_ire , Instruct= ions Retired Event (EventId=3D2) is supported by OS -0x8000001c, 0, eax, 3, os_lwp_bre , Branch R= etired Event (EventId=3D3) is supported by OS -0x8000001c, 0, eax, 4, os_lwp_dme , DCache M= iss Event (EventId=3D4) is supported by OS -0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Cloc= ks Not Halted event (EventId=3D5) is supported by OS -0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refe= rence clocks Not Halted event (EventId=3D6) is supported by OS +0x8000001c, 0, eax, 1, os_lpwval , LWPVAL i= nstruction is supported by OS +0x8000001c, 0, eax, 2, os_lwp_ire , Instruct= ions Retired Event is supported by OS +0x8000001c, 0, eax, 3, os_lwp_bre , Branch R= etired Event is supported by OS +0x8000001c, 0, eax, 4, os_lwp_dme , Dcache M= iss Event is supported by OS +0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Cloc= ks Not Halted event is supported by OS +0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refe= rence clocks Not Halted event is supported by OS 0x8000001c, 0, eax, 29, os_lwp_cont , LWP samp= ling in continuous mode is supported by OS 0x8000001c, 0, eax, 30, os_lwp_ptsc , Performa= nce Time Stamp Counter in event records is supported by OS 0x8000001c, 0, eax, 31, os_lwp_int , Interrup= t on threshold overflow is supported by OS 0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Cont= rol Block size, in quadwords 0x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP even= t record size, in bytes -0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max = supported EventId value (EventID 255 not included) +0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max = supported EventID value (EventID 255 not included) 0x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP even= ts area offset in the LWP Control Block -0x8000001c, 0, ecx, 4:0, lwp_latency_max , Num of b= its in cache latency counters (10 to 31) +0x8000001c, 0, ecx, 4:0, lwp_latency_max , Number o= f bits in cache latency counters (10 to 31) 0x8000001c, 0, ecx, 5, lwp_data_adddr , Cache mi= ss events report the data address of the reference 0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount b= y which cache latency is rounded 0x8000001c, 0, ecx, 15:9, lwp_version , LWP impl= ementation version @@ -924,16 +924,16 @@ 0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filte= ring (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-re= lated events can be filtered by cache level 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-re= lated events can be filtered by latency -0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is a= vailable in Hardware -0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL i= nstruction (EventId=3D1) is available in HW -0x8000001c, 0, edx, 2, hw_lwp_ire , Instruct= ions Retired Event (EventId=3D2) is available in HW -0x8000001c, 0, edx, 3, hw_lwp_bre , Branch R= etired Event (EventId=3D3) is available in HW -0x8000001c, 0, edx, 4, hw_lwp_dme , DCache M= iss Event (EventId=3D4) is available in HW -0x8000001c, 0, edx, 5, hw_lwp_cnh , CPU Cloc= ks Not Halted event (EventId=3D5) is available in HW -0x8000001c, 0, edx, 6, hw_lwp_rnh , CPU Refe= rence clocks Not Halted event (EventId=3D6) is available in HW -0x8000001c, 0, edx, 29, hw_lwp_cont , LWP samp= ling in continuous mode is available in HW -0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performa= nce Time Stamp Counter in event records is available in HW -0x8000001c, 0, edx, 31, hw_lwp_int , Interrup= t on threshold overflow is available in HW +0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is a= vailable in hardware +0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL i= nstruction is available in hardware +0x8000001c, 0, edx, 2, hw_lwp_ire , Instruct= ions Retired Event is available in hardware +0x8000001c, 0, edx, 3, hw_lwp_bre , Branch R= etired Event is available in hardware +0x8000001c, 0, edx, 4, hw_lwp_dme , Dcache M= iss Event is available in hardware +0x8000001c, 0, edx, 5, hw_lwp_cnh , Clocks N= ot Halted event is available in hardware +0x8000001c, 0, edx, 6, hw_lwp_rnh , Referenc= e clocks Not Halted event is available in hardware +0x8000001c, 0, edx, 29, hw_lwp_cont , LWP samp= ling in continuous mode is available in hardware +0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performa= nce Time Stamp Counter in event records is available in hardware +0x8000001c, 0, edx, 31, hw_lwp_int , Interrup= t on threshold overflow is available in hardware =20 # Leaf 8000001DH # AMD deterministic cache parameters @@ -969,10 +969,10 @@ 0x8000001f, 0, eax, 4, sev_nested_paging , SEV secu= re nested paging supported 0x8000001f, 0, eax, 5, vm_permission_levels , VMPL sup= ported 0x8000001f, 0, eax, 6, rpmquery , RPMQUERY= instruction supported -0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadwo stack supported +0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadow stack supported 0x8000001f, 0, eax, 8, secure_tsc , Secure T= SC supported 0x8000001f, 0, eax, 9, v_tsc_aux , Hardware= virtualizes TSC_AUX -0x8000001f, 0, eax, 10, sme_coherent , HW enfor= ces cache coherency across encryption domains +0x8000001f, 0, eax, 10, sme_coherent , Cache co= herency is enforced across encryption domains 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV gues= t mandates 64-bit hypervisor 0x8000001f, 0, eax, 12, restricted_injection , Restrict= ed Injection supported 0x8000001f, 0, eax, 13, alternate_injection , Alternat= e Injection supported @@ -984,13 +984,13 @@ 0x8000001f, 0, eax, 19, virt_ibs , IBS stat= e virtualization is supported for SEV-ES guests 0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA reg= ister protection is supported 0x8000001f, 0, eax, 25, smt_protection , SMT prot= ection is supported -0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR (0xc001f000h) is supported +0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR (0xc001f000) is supported 0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMP= UPDATE/VIRT_PSMASH MSRs are supported 0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit = number used to enable memory encryption 0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduct= ion of phys address space when encryption is enabled, in bits 0x8000001f, 0, ebx, 15:12, vmpl_count , Number o= f VM permission levels (VMPL) supported 0x8000001f, 0, ecx, 31:0, enc_guests_max , Max supp= orted number of simultaneous encrypted guests -0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum = ASID for SEV-enabled SEV-ES-disabled guest +0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Minimum = ASID for SEV-enabled SEV-ES-disabled guest =20 # Leaf 80000020H # AMD Platform QoS extended feature IDs @@ -999,6 +999,8 @@ 0x80000020, 0, ebx, 2, smba , Slow Mem= ory Bandwidth Allocation support 0x80000020, 0, ebx, 3, bmec , Bandwidt= h Monitoring Event Configuration support 0x80000020, 0, ebx, 4, l3rr , L3 Range= Reservation support +0x80000020, 0, ebx, 5, abmc , Assignab= le Bandwidth Monitoring Counters +0x80000020, 0, ebx, 6, sdciae , Smart Da= ta Cache Injection (SDCI) Allocation Enforcement 0x80000020, 1, eax, 31:0, mba_limit_len , MBA enfo= rcement limit size 0x80000020, 1, edx, 31:0, mba_cos_max , MBA max = Class of Service number (zero-based) 0x80000020, 2, eax, 31:0, smba_limit_len , SMBA enf= orcement limit size @@ -1023,12 +1025,21 @@ 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore Enable bit supported 0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS enable bit supported 0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR (0xc0010116) is not present -0x80000021, 0, eax, 10, fsrs_supported , Fast Sho= rt Rep Stosb (FSRS) is supported -0x80000021, 0, eax, 11, fsrc_supported , Fast Sho= rt Repe Cmpsb (FSRC) is supported +0x80000021, 0, eax, 10, fsrs_supported , Fast Sho= rt Rep STOSB (FSRS) is supported +0x80000021, 0, eax, 11, fsrc_supported , Fast Sho= rt Rep CMPSB (FSRC) is supported 0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR is supported +0x80000021, 0, eax, 16, opcode_reclaim , Reserves= opcode space 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 is supported 0x80000021, 0, eax, 18, epsf_supported , Enhanced= Predictive Store Forwarding (EPSF) is supported -0x80000021, 0, ebx, 11:0, microcode_patch_size , Size of = microcode patch, in 16-byte units +0x80000021, 0, eax, 22, wl_feedback , Workload= -based heuristic feedback to OS +0x80000021, 0, eax, 24, eraps_support , Enhanced= Return Address Predictor Security +0x80000021, 0, eax, 27, sbpb , Support = for the Selective Branch Predictor Barrier +0x80000021, 0, eax, 28, ibpb_brtype , Branch p= redictions flushed from CPU branch predictor +0x80000021, 0, eax, 29, srso_no , CPU is n= ot subject to the SRSO vulnerability +0x80000021, 0, eax, 30, srso_uk_no , CPU is n= ot vulnerable to SRSO at user-kernel boundary +0x80000021, 0, eax, 31, srso_msr_fix , Software= may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO +0x80000021, 0, ebx, 15:0, microcode_patch_size , Size of = microcode patch, in 16-byte units +0x80000021, 0, ebx, 23:16, rap_size , Return A= ddress Predictor size =20 # Leaf 80000022H # AMD Performance Monitoring v2 enumeration @@ -1036,7 +1047,7 @@ 0x80000022, 0, eax, 0, perfmon_v2 , Performa= nce monitoring v2 supported 0x80000022, 0, eax, 1, lbr_v2 , Last Bra= nch Record v2 extensions (LBR Stack) 0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing= core performance counters / LBR Stack supported -0x80000022, 0, ebx, 3:0, n_pmc_core , Number o= f core perfomance counters +0x80000022, 0, ebx, 3:0, n_pmc_core , Number o= f core performance counters 0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number o= f available LBR stack entries 0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number o= f available northbridge (data fabric) performance counters 0x80000022, 0, ebx, 21:16, n_pmc_umc , Number o= f available UMC performance counters @@ -1046,7 +1057,7 @@ # AMD Secure Multi-key Encryption enumeration =20 0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK = encryption mode is supported -0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK = mode: total num of available encryption keys +0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK = mode: total number of available encryption keys =20 # Leaf 80000026H # AMD extended topology enumeration v2 @@ -1134,7 +1145,7 @@ =20 0x80860007, 0, eax, 31:0, cpu_cur_mhz , Current = CPU frequency, in MHz 0x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current = CPU voltage, in millivolts -0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current = CPU performance percentage, 0 - 100d +0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current = CPU performance percentage, 0 - 100 0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current = CPU gate delay, in femtoseconds =20 # Leaf C0000000H --=20 2.48.1