From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7663326BD82 for ; Thu, 6 Mar 2025 20:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294232; cv=none; b=uSzCrtpC1k6jbS7iGpWlDHYnJ6i6qOiTWZENExXurBIH3HLNEYK2UxuZH0AVVMV6xlzS4ZSozok+nlfopzeTs8i8PHuvayejfZr22RpatZoqB0E5xYJMuYMcqVETsQGDq5SHV4iYuuHV5de0MBCZV/o3ZZXZFgvyS4adtEV7REc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294232; c=relaxed/simple; bh=Sj8ehWyrASLJgEund+Zuejdi3dIiwuMMC4gFlwFkq0Q=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=DdV/5B6pN1CJlYoU3uNEc1SJ3uypZ5DnMD/bQExt0Lc9so2Geo4LCsWGM3m6p/t2JR8wNsgikad8eWOPhLm/JlFOET/M51CjsE13XW5uI9BB9jTIZ+s4NlAD/B+IQHqhQLHvFVzAX9VgXMvwbYyeQ87VcXz/KNmKfaSkHNUqfm4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=WF7clCWO; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=/NVMlQ52; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="WF7clCWO"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="/NVMlQ52" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741294222; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qrZ9M2b7UwXQTxopgU+2U3Wtm3uX6MOzB4ctL4A5ucs=; b=WF7clCWOVQjZ9s3XJNMy1f0FKUFdVXB3UjbiIVvCvLqkzTL30n/L44knwiZ13HfkLW1x2Y K3dT2KLfktMnO2H0nSn3RNPKp5SB9mB5CEo2i59sTtuoH8coQCQuXhq9lznh3v9sAbQjdc zIi6Fwv/qSRl9NL8LPi/HaAOqs0jSzvgESlQ/F67uD6dtyRy6MZcm2FdnyEFP1uGg+Mvku 9fd+j440Lz6v6DB24hH9uUcyuDVcakESM1tbofWa3QEwAFzI6gdwZqWs4AGz4o80XVrNis K10kImqPWzt43w6q0Id2HGUSOFfH6VznGur7rgeIN+HfUfDT5lXh1C8zK6jW2A== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741294222; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qrZ9M2b7UwXQTxopgU+2U3Wtm3uX6MOzB4ctL4A5ucs=; b=/NVMlQ52ZXD0VtEEm8jJklXs8XFITGOdFDY9DzM5uFbQORC1jIXZZo+r/IwYwDjYGtygpN mUP+SE00nw8AHpCA== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 01/12] tools/x86/kcpuid: Fix error handling Date: Thu, 6 Mar 2025 21:49:49 +0100 Message-ID: <20250306205000.227399-2-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Error handling in kcpuid is unreliable. On malloc() failures, the code prints an error then just goes on. The error messages are also printed to standard output instead of standard error. Use err() and errx() from to direct all error messages to standard error and automatically exit the program. Use err() to include the errno information, and errx() otherwise. Use warnx() for warnings. While at it, alphabetically reorder the header includes. Fixes: c6b2f240bf8d ("tools/x86: Add a kcpuid tool to show raw CPU features= ") Closes: https://lkml.kernel.org/r/20240926223557.2048-1-rbrasga@uci.edu Reported-by: Remington Brasga Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 47 +++++++++++++++++----------------- 1 file changed, 23 insertions(+), 24 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 1b25c0a95d3f..abfeecce5aa8 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -1,11 +1,12 @@ // SPDX-License-Identifier: GPL-2.0 #define _GNU_SOURCE =20 -#include +#include +#include #include +#include #include #include -#include =20 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #define min(a, b) (((a) < (b)) ? (a) : (b)) @@ -145,14 +146,14 @@ static bool cpuid_store(struct cpuid_range *range, u3= 2 f, int subleaf, if (!func->leafs) { func->leafs =3D malloc(sizeof(struct subleaf)); if (!func->leafs) - perror("malloc func leaf"); + err(EXIT_FAILURE, NULL); =20 func->nr =3D 1; } else { s =3D func->nr; func->leafs =3D realloc(func->leafs, (s + 1) * sizeof(*leaf)); if (!func->leafs) - perror("realloc f->leafs"); + err(EXIT_FAILURE, NULL); =20 func->nr++; } @@ -211,7 +212,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) =20 range =3D malloc(sizeof(struct cpuid_range)); if (!range) - perror("malloc range"); + err(EXIT_FAILURE, NULL); =20 if (input_eax & 0x80000000) range->is_ext =3D true; @@ -220,7 +221,7 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) =20 range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) - perror("malloc range->funcs"); + err(EXIT_FAILURE, NULL); =20 range->nr =3D idx_func; memset(range->funcs, 0, sizeof(struct cpuid_func) * idx_func); @@ -395,8 +396,8 @@ static int parse_line(char *line) return 0; =20 err_exit: - printf("Warning: wrong line format:\n"); - printf("\tline[%d]: %s\n", flines, line); + warnx("Wrong line format:\n" + "\tline[%d]: %s", flines, line); return -1; } =20 @@ -418,10 +419,8 @@ static void parse_text(void) file =3D fopen("./cpuid.csv", "r"); } =20 - if (!file) { - printf("Fail to open '%s'\n", filename); - return; - } + if (!file) + err(EXIT_FAILURE, "%s", filename); =20 while (1) { ret =3D getline(&line, &len, file); @@ -530,7 +529,7 @@ static inline struct cpuid_func *index_to_func(u32 inde= x) func_idx =3D index & 0xffff; =20 if ((func_idx + 1) > (u32)range->nr) { - printf("ERR: invalid input index (0x%x)\n", index); + warnx("Invalid input index (0x%x)", index); return NULL; } return &range->funcs[func_idx]; @@ -562,7 +561,7 @@ static void show_info(void) return; } =20 - printf("ERR: invalid input subleaf (0x%x)\n", user_sub); + warnx("Invalid input subleaf (0x%x)", user_sub); } =20 show_func(func); @@ -593,15 +592,15 @@ static void setup_platform_cpuid(void) =20 static void usage(void) { - printf("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" - "\t-a|--all Show both bit flags and complex bit fields info\= n" - "\t-b|--bitflags Show boolean flags only\n" - "\t-d|--detail Show details of the flag/fields (default)\n" - "\t-f|--flags Specify the cpuid csv file\n" - "\t-h|--help Show usage info\n" - "\t-l|--leaf=3Dindex Specify the leaf you want to check\n" - "\t-r|--raw Show raw cpuid data\n" - "\t-s|--subleaf=3Dsub Specify the subleaf you want to check\n" + warnx("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" + "\t-a|--all Show both bit flags and complex bit fields = info\n" + "\t-b|--bitflags Show boolean flags only\n" + "\t-d|--detail Show details of the flag/fields (default)\n" + "\t-f|--flags Specify the cpuid csv file\n" + "\t-h|--help Show usage info\n" + "\t-l|--leaf=3Dindex Specify the leaf you want to check\n" + "\t-r|--raw Show raw cpuid data\n" + "\t-s|--subleaf=3Dsub Specify the subleaf you want to check" ); } =20 @@ -652,7 +651,7 @@ static int parse_options(int argc, char *argv[]) user_sub =3D strtoul(optarg, NULL, 0); break; default: - printf("%s: Invalid option '%c'\n", argv[0], optopt); + warnx("Invalid option '%c'", optopt); return -1; } =20 --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 96C51207DED for ; Thu, 6 Mar 2025 20:50:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294229; cv=none; b=BORk3QWgObI5sVR8urNIEuRqL0Zx8MgOxykkvmakaPVziHTZMm9FAXIqQqRj+73S93D3BJ6p7aHxxplvxYo34E18UUTZIsVTMoBWFgTOYIfuwVfMgmPTN/pizkr3NrIP9NUJVm41q0iJbP03lFFO4zW9KVxz8wza/1q1B4oWMyE= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; 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Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741294225; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lwVtck4Unu5sM6JeYtaPoha2zMPYGqqNVUo58AiBHJk=; b=KRZI9nZpx97ZwvF+V/AwxSLCv5eRtaF1o2o3OYqRjErxo1D7FCMuOd/JPWPoYqqJ39gXF2 fALQ5Y56xV4CRZdWB7TNHsVT+BqZCIFZ5yzXZU+hanma56C7QyALn4cuJ+/T22qR55Oq4y sNHUba/CwTOwCv7fXoGD+X/mwmrU6I82tKxZ0rd3wnWGtC764SJk8oDgxiW8leGPa0HOvp UEJGNdR0W3ATB2qN4Me/FJU/qPQ+zJZspXCn1KURMYOLico4FbdIQwAeUAzmCwnWzsEARQ KgF+c9a2dSuRgJIW2R1S1h79xt6vGqg9DMGmjRFhTcIPu5EINvKIHKfM2/kdHQ== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741294225; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=lwVtck4Unu5sM6JeYtaPoha2zMPYGqqNVUo58AiBHJk=; b=NQt5d+D9SrmvSpLtQC14+WKrdBWrzwjC3BvNY7UPquwg1ZnB5yI1GdOI7TVQxToFJwX6JU yJFRouxFg6YdEzCg== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 02/12] tools/x86/kcpuid: Remove unused local variable Date: Thu, 6 Mar 2025 21:49:50 +0100 Message-ID: <20250306205000.227399-3-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The local variable "index" is not used anywhere. Remove it. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 4 ---- 1 file changed, 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index abfeecce5aa8..1159204b9902 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -180,10 +180,6 @@ static void raw_dump_range(struct cpuid_range *range) =20 for (f =3D 0; (int)f < range->nr; f++) { struct cpuid_func *func =3D &range->funcs[f]; - u32 index =3D f; - - if (range->is_ext) - index +=3D 0x80000000; =20 /* Skip leaf without valid items */ if (!func->nr) --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BBF37270EBF for ; Thu, 6 Mar 2025 20:50:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294232; cv=none; b=db3DlUI0LSlc4ZR9teKgjIooQMoMt9/hyT7PFKbsIyrJh6Ol1scj9JLMWbxRfHvelACusuUyNGA+uY/8I43RsUCv7P9ijHX5q4iPdNtcDzQzZfCaIqrVxC95znmERwgk94r5iYtcowyAvTAH2o+eq0Lb/9NyRd4KP7vwkmbcua4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294232; c=relaxed/simple; bh=etYCWwZuY6WBwGV1mwSClKPJGtnqn08gMHsF1t0ivMY=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=lJWAOg0Z+HjvXFHsNLqV9A94rvX8bnrcNQ4PfqK+wjR+0EucwFUJ57SZ9Lgiu0Hwi7MXzVQGtVfPvtDBg+mjX5Z0EEpsli/u2EcC3Ya37cDAOB7d0y/ICDv7h7pXJl8WCHGrVD1Pt4OL9Nqb9OTt+87KMn3gS/f1mRgZkisQcNU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=BKZwTppk; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=Q58QeEmV; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="BKZwTppk"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="Q58QeEmV" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 03/12] tools/x86/kcpuid: Remove unused global variable Date: Thu, 6 Mar 2025 21:49:51 +0100 Message-ID: <20250306205000.227399-4-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The global variable "is_amd" is not used anywhere. Remove it. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 1159204b9902..ceed560cd8a3 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -78,7 +78,6 @@ struct cpuid_range { */ struct cpuid_range *leafs_basic, *leafs_ext; =20 -static bool is_amd; static bool show_details; static bool show_raw; static bool show_flags_only =3D true; @@ -571,16 +570,6 @@ static void show_info(void) =20 static void setup_platform_cpuid(void) { - u32 eax, ebx, ecx, edx; - - /* Check vendor */ - eax =3D ebx =3D ecx =3D edx =3D 0; - cpuid(&eax, &ebx, &ecx, &edx); - - /* "htuA" */ - if (ebx =3D=3D 0x68747541) - is_amd =3D true; - /* Setup leafs for the basic and extended range */ leafs_basic =3D setup_cpuid_range(0x0); leafs_ext =3D setup_cpuid_range(0x80000000); --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 963EC2777FD for ; Thu, 6 Mar 2025 20:50:33 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294235; cv=none; b=QGy5NfN37JjMGjor/sWmqlO60onXkTitTdDPzmNN+DgidBLYk/H7j7r99CgnSqK+SD2CMJVkGfrGig7J23wgboufOBIeC48enRZCaPGo2l46GGryxGgGZbSK7/fKvhPqrHOeYjNeQGZJ/pNKIqqpgs/TyGBPvLczzDLZFx7oYos= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294235; c=relaxed/simple; bh=48MXf2D3f+m/CXIPCWPp+NC0YZqPpT13wi5sfchvN9w=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Gl9mXo5DvvyGH3qAl2SRHhHONoNVgZWr/GgturjnzHCoMkwYmQLjdMn87OciMH2W8w2oh+pgTLoc9ubs2xh871V1qUEoZ7GWf6ekeh2G9gfrW944n8z/xwnYucyyuZivho0L9TfYO+vDtqlcjvhjXZnoYY2wgSDXiXBHKM2rG+E= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=HUJhaMeJ; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=ljn5aK4R; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="HUJhaMeJ"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="ljn5aK4R" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 04/12] tools/x86/kcpuid: Simplify usage() handling Date: Thu, 6 Mar 2025 21:49:52 +0100 Message-ID: <20250306205000.227399-5-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Refactor usage() to accept an exit code parameter and exit the program after usage printing. This streamlines its callers' code paths. Remove the "Invalid option" error message since getopt_long(3) already emits a similar message by default. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 37 +++++++++++++++------------------- 1 file changed, 16 insertions(+), 21 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index ceed560cd8a3..c5e18a397e07 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -10,6 +10,7 @@ =20 #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) #define min(a, b) (((a) < (b)) ? (a) : (b)) +#define __noreturn __attribute__((__noreturn__)) =20 typedef unsigned int u32; typedef unsigned long long u64; @@ -575,17 +576,17 @@ static void setup_platform_cpuid(void) leafs_ext =3D setup_cpuid_range(0x80000000); } =20 -static void usage(void) +static void __noreturn usage(int exit_code) { - warnx("kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" - "\t-a|--all Show both bit flags and complex bit fields = info\n" - "\t-b|--bitflags Show boolean flags only\n" - "\t-d|--detail Show details of the flag/fields (default)\n" - "\t-f|--flags Specify the cpuid csv file\n" - "\t-h|--help Show usage info\n" - "\t-l|--leaf=3Dindex Specify the leaf you want to check\n" - "\t-r|--raw Show raw cpuid data\n" - "\t-s|--subleaf=3Dsub Specify the subleaf you want to check" + err(exit_code, "kcpuid [-abdfhr] [-l leaf] [-s subleaf]\n" + "\t-a|--all Show both bit flags and complex bit fields in= fo\n" + "\t-b|--bitflags Show boolean flags only\n" + "\t-d|--detail Show details of the flag/fields (default)\n" + "\t-f|--flags Specify the cpuid csv file\n" + "\t-h|--help Show usage info\n" + "\t-l|--leaf=3Dindex Specify the leaf you want to check\n" + "\t-r|--raw Show raw cpuid data\n" + "\t-s|--subleaf=3Dsub Specify the subleaf you want to check" ); } =20 @@ -601,7 +602,7 @@ static struct option opts[] =3D { { NULL, 0, NULL, 0 } }; =20 -static int parse_options(int argc, char *argv[]) +static void parse_options(int argc, char *argv[]) { int c; =20 @@ -621,9 +622,7 @@ static int parse_options(int argc, char *argv[]) user_csv =3D optarg; break; case 'h': - usage(); - exit(1); - break; + usage(EXIT_SUCCESS); case 'l': /* main leaf */ user_index =3D strtoul(optarg, NULL, 0); @@ -636,11 +635,8 @@ static int parse_options(int argc, char *argv[]) user_sub =3D strtoul(optarg, NULL, 0); break; default: - warnx("Invalid option '%c'", optopt); - return -1; - } - - return 0; + usage(EXIT_FAILURE); + } } =20 /* @@ -653,8 +649,7 @@ static int parse_options(int argc, char *argv[]) */ int main(int argc, char *argv[]) { - if (parse_options(argc, argv)) - return -1; + parse_options(argc, argv); =20 /* Setup the cpuid leafs of current platform */ setup_platform_cpuid(); --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5C6D2066F9 for ; Thu, 6 Mar 2025 20:50:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294238; cv=none; b=KCjoIhVaQIzMHwJFfjSG2O5BeY4yRzy75A8gLa8zL18gD6f9mz6R74GGWiTMnJwF4nU6IkeWZzdC5WKRB7q5NsiSWu4dKM1wzBqgNgHfiC64PJck7oAVJWqrme+E6JM+VA0eaKlvZGorpS0WwLmUWc0XNa6ZaTSRURpVLuFwOYc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294238; c=relaxed/simple; bh=JRqnuXcyiL3IN3+bfXeEvZVUd2YugMhoG/bz8wK0OO8=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=GZIpwra6k4qQsr4+XRbRC69si47h7lXk9g14nnegJDFkng1jU0DeiKcZXhZ5jid4s94rE7nMaoaEWVYA0xClQc6hFMv59m3XT0dsDKfYJbT2k7ZHjlZZwV44rSCEClvD+oDiQ/JvBm8jqm3/9Hd+D4awJQA06YM8qeaGnvfZRxc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=rXg8tFuY; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=dn+gMbYw; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="rXg8tFuY"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="dn+gMbYw" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 05/12] tools/x86/kcpuid: Refactor CPUID range handling for future expansion Date: Thu, 6 Mar 2025 21:49:53 +0100 Message-ID: <20250306205000.227399-6-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kcpuid code assumes only two CPUID index ranges, standard (0x0...) and extended (0x80000000...). Since additional CPUID index ranges will be added in further commits, replace the "is_ext" boolean with enumeration-based range classification. Collect all CPUID ranges in a structured array and introduce helper macros to iterate over it. Use such helpers throughout the code. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 103 ++++++++++++++++++++------------- 1 file changed, 62 insertions(+), 41 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index c5e18a397e07..6f6a394486af 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -65,19 +65,52 @@ struct cpuid_func { int nr; }; =20 +enum range_index { + RANGE_STD =3D 0, /* Standard */ + RANGE_EXT =3D 0x80000000, /* Extended */ +}; + +#define CPUID_INDEX_MASK 0x80000000 +#define CPUID_FUNCTION_MASK (~CPUID_INDEX_MASK) + struct cpuid_range { /* array of main leafs */ struct cpuid_func *funcs; /* number of valid leafs */ int nr; - bool is_ext; + enum range_index index; }; =20 -/* - * basic: basic functions range: [0... ] - * ext: extended functions range: [0x80000000... ] - */ -struct cpuid_range *leafs_basic, *leafs_ext; +static struct cpuid_range ranges[] =3D { + { .index =3D RANGE_STD, }, + { .index =3D RANGE_EXT, }, +}; + +static char *range_to_str(struct cpuid_range *range) +{ + switch (range->index) { + case RANGE_STD: return "Standard"; + case RANGE_EXT: return "Extended"; + default: return NULL; + } +} + +#define for_each_cpuid_range(range) \ + for (unsigned int i =3D 0; \ + i < ARRAY_SIZE(ranges) && ((range) =3D &ranges[i]); \ + i++) + +struct cpuid_range *index_to_cpuid_range(u32 index) +{ + struct cpuid_range *range; + + for_each_cpuid_range(range) { + if (range->index =3D=3D (index & CPUID_INDEX_MASK)) + return range; + } + + return NULL; +} =20 static bool show_details; static bool show_raw; @@ -175,7 +208,7 @@ static void raw_dump_range(struct cpuid_range *range) u32 f; int i; =20 - printf("%s Leafs :\n", range->is_ext ? "Extended" : "Basic"); + printf("%s Leafs :\n", range_to_str(range)); printf("=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n"); =20 for (f =3D 0; (int)f < range->nr; f++) { @@ -192,29 +225,19 @@ static void raw_dump_range(struct cpuid_range *range) } =20 #define MAX_SUBLEAF_NUM 64 -struct cpuid_range *setup_cpuid_range(u32 input_eax) +void setup_cpuid_range(struct cpuid_range *range) { u32 max_func, idx_func, subleaf, max_subleaf; - u32 eax, ebx, ecx, edx, f =3D input_eax; - struct cpuid_range *range; + u32 eax, ebx, ecx, edx, f; bool allzero; =20 - eax =3D input_eax; + eax =3D f =3D range->index; ebx =3D ecx =3D edx =3D 0; =20 cpuid(&eax, &ebx, &ecx, &edx); max_func =3D eax; idx_func =3D (max_func & 0xffff) + 1; =20 - range =3D malloc(sizeof(struct cpuid_range)); - if (!range) - err(EXIT_FAILURE, NULL); - - if (input_eax & 0x80000000) - range->is_ext =3D true; - else - range->is_ext =3D false; - range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) err(EXIT_FAILURE, NULL); @@ -265,8 +288,6 @@ struct cpuid_range *setup_cpuid_range(u32 input_eax) } =20 } - - return range; } =20 /* @@ -325,13 +346,13 @@ static int parse_line(char *line) /* index/main-leaf */ index =3D strtoull(tokens[0], NULL, 0); =20 - if (index & 0x80000000) - range =3D leafs_ext; - else - range =3D leafs_basic; + /* Skip line parsing if it's not covered by known ranges */ + range =3D index_to_cpuid_range(index); + if (!range) + return -1; =20 - index &=3D 0x7FFFFFFF; /* Skip line parsing for non-existing indexes */ + index &=3D CPUID_FUNCTION_MASK; if ((int)index >=3D range->nr) return -1; =20 @@ -521,24 +542,28 @@ static inline struct cpuid_func *index_to_func(u32 in= dex) struct cpuid_range *range; u32 func_idx; =20 - range =3D (index & 0x80000000) ? leafs_ext : leafs_basic; - func_idx =3D index & 0xffff; + range =3D index_to_cpuid_range(index); + if (!range) + return NULL; =20 + func_idx =3D index & 0xffff; if ((func_idx + 1) > (u32)range->nr) { warnx("Invalid input index (0x%x)", index); return NULL; } + return &range->funcs[func_idx]; } =20 static void show_info(void) { + struct cpuid_range *range; struct cpuid_func *func; =20 if (show_raw) { /* Show all of the raw output of 'cpuid' instr */ - raw_dump_range(leafs_basic); - raw_dump_range(leafs_ext); + for_each_cpuid_range(range) + raw_dump_range(range); return; } =20 @@ -565,15 +590,8 @@ static void show_info(void) } =20 printf("CPU features:\n=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D\n\n"); - show_range(leafs_basic); - show_range(leafs_ext); -} - -static void setup_platform_cpuid(void) -{ - /* Setup leafs for the basic and extended range */ - leafs_basic =3D setup_cpuid_range(0x0); - leafs_ext =3D setup_cpuid_range(0x80000000); + for_each_cpuid_range(range) + show_range(range); } =20 static void __noreturn usage(int exit_code) @@ -649,10 +667,13 @@ static void parse_options(int argc, char *argv[]) */ int main(int argc, char *argv[]) { + struct cpuid_range *range; + parse_options(argc, argv); =20 /* Setup the cpuid leafs of current platform */ - setup_platform_cpuid(); + for_each_cpuid_range(range) + setup_cpuid_range(range); =20 /* Read and parse the 'cpuid.csv' */ parse_text(); --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 59EF7278150 for ; Thu, 6 Mar 2025 20:50:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294242; cv=none; b=cek6Od59I+FlUx+MmltvnSO3v2hRDNQ5dHfbflzjSIqwb3QApPi8fIKF9opMxSbUw6h3xLghCqjBTuhvOtSVN6c8bRE3DmeYXwEfZZrpLOOq1Ilve7CGpwIEdl37vnRTzY0f6GYwIEY6SXay70AGrSWZr7erZSa57u/EZFRKdr4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294242; c=relaxed/simple; bh=nPB/Nn8SelnBvMhQSnTJZZlN5sI/ygflWttSB0phHTA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=bryPW+PRQsYPvvleRaCCPOszfmVi7ArTL115N98bNBFAKgX70BYDmmUaUYvOAToArW5+T6xOH69a29Zhis4PwVFXzulSL3LwvBdaRe1XpyLvh9e/Qi5OfVB4/TQuENoB9+9f1sUqgp8rE1INf+Jvus3059wBlJMHjUhYk7tqZhc= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=DKiHUj6R; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=e5oBf0l3; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="DKiHUj6R"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="e5oBf0l3" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 06/12] tools/x86/kcpuid: Extend CPUID index mask macro Date: Thu, 6 Mar 2025 21:49:54 +0100 Message-ID: <20250306205000.227399-7-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Extend the CPUID index mask macro from 0x80000000 to 0xffff0000. This accommodates the Centaur-specific indices (0x80860000+) which will be later added. Note that this also automatically sets CPUID_FUNCTION_MASK to 0x0000ffff, which is the actual correct value. Use it instead of the 0xffff literal where appropriate. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 6f6a394486af..6a4c845bc1de 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -70,7 +70,7 @@ enum range_index { RANGE_EXT =3D 0x80000000, /* Extended */ }; =20 -#define CPUID_INDEX_MASK 0x80000000 +#define CPUID_INDEX_MASK 0xffff0000 #define CPUID_FUNCTION_MASK (~CPUID_INDEX_MASK) =20 struct cpuid_range { @@ -174,7 +174,7 @@ static bool cpuid_store(struct cpuid_range *range, u32 = f, int subleaf, * Cut off vendor-prefix from CPUID function as we're using it as an * index into ->funcs. */ - func =3D &range->funcs[f & 0xffff]; + func =3D &range->funcs[f & CPUID_FUNCTION_MASK]; =20 if (!func->leafs) { func->leafs =3D malloc(sizeof(struct subleaf)); @@ -236,7 +236,7 @@ void setup_cpuid_range(struct cpuid_range *range) =20 cpuid(&eax, &ebx, &ecx, &edx); max_func =3D eax; - idx_func =3D (max_func & 0xffff) + 1; + idx_func =3D (max_func & CPUID_FUNCTION_MASK) + 1; =20 range->funcs =3D malloc(sizeof(struct cpuid_func) * idx_func); if (!range->funcs) @@ -546,7 +546,7 @@ static inline struct cpuid_func *index_to_func(u32 inde= x) if (!range) return NULL; =20 - func_idx =3D index & 0xffff; + func_idx =3D index & CPUID_FUNCTION_MASK; if ((func_idx + 1) > (u32)range->nr) { warnx("Invalid input index (0x%x)", index); return NULL; --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B782206F22 for ; Thu, 6 Mar 2025 20:50:42 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294244; cv=none; b=LI0AH74YWk0j/1SZMUT5LkX+vdhAaBQle9YXC/0C8JHBfVEY9MLx7Gj+9Sijmzh3OR5anxv/URJDFAaTx9uiX77inLkh3wIHMzK7FWrpmhftoEVYg7vWH7685hFulW7nUuOdMq/yLqXhGw9PIkv1n6ku1Vit/HdoAX4DZVwmUtc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294244; c=relaxed/simple; bh=bC9MJfynTdb206YBE832HbVqruIbRmYVUbYmc43PQaA=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=piUyRvOZq1I843owHv5kbsSMIX8Fc1FamsVFfRFAqSlVOmlte/TSsGW2HVr75oQZgI/taze0XV4wSGdI580Li8K0u0PHbD06xy71yN4nqkFYnS6CuX2fhSH6e3mbj3NRAK+ZVvjrJbEzO6v/jD5odzssNxnmua+A3gDa+6xPoQQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=h0pCzjjG; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=U6APigC/; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="h0pCzjjG"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="U6APigC/" From: "Ahmed S. Darwish" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020; t=1741294241; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qT46OHAQ0Id4t8iEJKmnosKGJmcnq/7L9c0wFS85XMA=; b=h0pCzjjGvniSaHlidsaRSOIn9vcrbiVPENRpnWSlMZNjOoHUhPmV90g+qac9/bw25ZG7d5 BGUL9H6BaWmnaUrzkEJgmUjSspwLJdFl0TsdPdZGXe/nqrEwhcEhuMi/whpI1yI3KaUKOS zGfEgOCvOdWYUaIaKEY+wVN1E2q58+7IV0Mw8x1/VGtwyK3c0E4bzQYdX0Ldlsb4fck115 NM+Vw82LdEOn/7BSX2eWOAEhyI0VAvY80FHzCjOQPdj1nrlS2MGY4sCohbO9Xmzj8Inofm LKWmHXEdsFs1WA0Ncm36pgp+e2pNg4lo0ZGuzamn+sNPbQCsgdmGqJlTtK1ohA== DKIM-Signature: v=1; a=ed25519-sha256; c=relaxed/relaxed; d=linutronix.de; s=2020e; t=1741294241; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=qT46OHAQ0Id4t8iEJKmnosKGJmcnq/7L9c0wFS85XMA=; b=U6APigC/I3tPK+CmE/o/H2UMex64pzAtd8oGMzeiKEZk5oti1eV+LQCUOZSOy4f9LhKM6/ ZU+HbAVWHdwGwMCA== To: Borislav Petkov , Ingo Molnar , Dave Hansen Cc: Thomas Gleixner , Andrew Cooper , "H. Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 07/12] tools/x86/kcpuid: Add rudimentary CPU vendor detection Date: Thu, 6 Mar 2025 21:49:55 +0100 Message-ID: <20250306205000.227399-8-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The kcpuid CSV file will soon be updated with CPUID indices that are only valid for certain CPU vendors, such as Centaur or Transmeta. Thus, introduce rudimentary x86 vendor detection to kcpuid. Associate each known CPUID index range with a bitmask indicating its compatible CPU vendors. Define CPU vendor markers for Intel, AMD, Centaur, and Transmeta. Since fine-grained vendor detection is not needed, classify Hygon CPUs under AMD and Zhaoxin CPUs under Centaur. Mark standard (0x0) and extended (0x80000000) CPUID index ranges as valid for all vendors, including unknown ones. This ensures that kcpuid still works in case of an x86 vendor detection failure. Save the result of CPU vendor detection at a "this_cpu_vendor" global, which will be utilized in next commits. Note, to avoid needlessly complicating the kcpuid code, implement vendor detection only in terms of leaf 0x0's EDX register. Complete x86 vendor detection can be later added if needed. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 65 +++++++++++++++++++++++++++++++--- 1 file changed, 61 insertions(+), 4 deletions(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 6a4c845bc1de..36efcb753b77 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -8,12 +8,16 @@ #include #include =20 +typedef unsigned int u32; +typedef unsigned long long u64; + #define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0])) +#define BIT(x) (1UL << (x)) #define min(a, b) (((a) < (b)) ? (a) : (b)) #define __noreturn __attribute__((__noreturn__)) =20 -typedef unsigned int u32; -typedef unsigned long long u64; +#define fourcc(a, b, c, d) \ + ((u32)(a) | ((u32)(b) << 8) | ((u32)(c) << 16) | ((u32)(d) << 24)) =20 char *def_csv =3D "/usr/share/misc/cpuid.csv"; char *user_csv; @@ -65,6 +69,17 @@ struct cpuid_func { int nr; }; =20 +enum cpu_vendor { + VENDOR_INTEL =3D BIT(0), + VENDOR_AMD =3D BIT(1), /* includes Hygon */ + VENDOR_CENTAUR =3D BIT(2), /* includes Zhaoxin */ + VENDOR_TRANSMETA =3D BIT(3), + VENDOR_UNKNOWN =3D BIT(15), + VENDOR_ALL =3D ~0UL, +}; + +static enum cpu_vendor this_cpu_vendor; + enum range_index { RANGE_STD =3D 0, /* Standard */ RANGE_EXT =3D 0x80000000, /* Extended */ @@ -79,11 +94,17 @@ struct cpuid_range { /* number of valid leafs */ int nr; enum range_index index; + /* compatible cpu vendors */ + enum cpu_vendor vendors; }; =20 static struct cpuid_range ranges[] =3D { - { .index =3D RANGE_STD, }, - { .index =3D RANGE_EXT, }, + { .index =3D RANGE_STD, + .vendors =3D VENDOR_ALL, + }, + { .index =3D RANGE_EXT, + .vendors =3D VENDOR_ALL, + }, }; =20 static char *range_to_str(struct cpuid_range *range) @@ -145,6 +166,40 @@ static inline bool has_subleafs(u32 f) return false; } =20 +/* + * Leaf 0x0 EDX output, CPU vendor ID string bytes 4 - 7. + */ +enum { + EDX_INTEL =3D fourcc('i', 'n', 'e', 'I'), /* Genu_ineI_ntel */ + EDX_AMD =3D fourcc('e', 'n', 't', 'i'), /* Auth_enti_cAMD */ + EDX_HYGON =3D fourcc('n', 'G', 'e', 'n'), /* Hygo_nGen_uine */ + EDX_TRANSMETA =3D fourcc('i', 'n', 'e', 'T'), /* Genu_ineT_Mx86 */ + EDX_CENTAUR =3D fourcc('a', 'u', 'r', 'H'), /* Cent_aurH_auls */ + EDX_ZHAOXIN =3D fourcc('a', 'n', 'g', 'h'), /* Sh_angh_ai */ +}; + +static enum cpu_vendor identify_cpu_vendor(void) +{ + u32 eax =3D 0, ebx, ecx =3D 0, edx; + + cpuid(&eax, &ebx, &ecx, &edx); + + switch (edx) { + case EDX_INTEL: + return VENDOR_INTEL; + case EDX_AMD: + case EDX_HYGON: + return VENDOR_AMD; + case EDX_TRANSMETA: + return VENDOR_TRANSMETA; + case EDX_CENTAUR: + case EDX_ZHAOXIN: + return VENDOR_CENTAUR; + default: + return VENDOR_UNKNOWN; + } +} + static void leaf_print_raw(struct subleaf *leaf) { if (has_subleafs(leaf->index)) { @@ -671,6 +726,8 @@ int main(int argc, char *argv[]) =20 parse_options(argc, argv); =20 + this_cpu_vendor =3D identify_cpu_vendor(); + /* Setup the cpuid leafs of current platform */ for_each_cpuid_range(range) setup_cpuid_range(range); --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6720927BF75 for ; Thu, 6 Mar 2025 20:50:45 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294246; cv=none; b=thF0Bh4AMfHgyV1FtosHiSHG0mgLKlwTh0rTRMzK9OjDYITHhjPWDsoVolprt1vx03HeWs02SMTpEiqxvpeziQs0K3cPOwsGOZfFXuEr6BPwarn+NjyXnaeCCgXC6bFshxsD13dpYIQlviZSCjKLFp4gZp/h+LtRXh5uRM+fXug= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294246; c=relaxed/simple; bh=3dyKvFwIOoPeXrZ1fE8S9QLS4SSkGAFsSLgxF9LTb58=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=XbUUHlqGKd1EyQl7FBuH1lfOW16f3yvr3lgLO2+iSUZZ4M+zlf1Sdz2EAOFcCT5IiPs7YOFfxOeq0JqHghQoe3eHE13sRxT01VyCPg3G8idwi076TlY5eedgM+6hSheNgPTgtJt7C9Vf5KWRWZWOsmqHUKOsSnrHbj4a7OP90pQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nWGv10sr; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=60mIn93+; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nWGv10sr"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="60mIn93+" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 08/12] tools/x86/kcpuid: Restrict CPUID scanning to valid vendor ranges Date: Thu, 6 Mar 2025 21:49:56 +0100 Message-ID: <20250306205000.227399-9-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" kcpuid works in two runs: one run for invoking the CPUID instructions and saving all their output in memory, and another for parsing that raw in-memory output using the CSV file specification. In both runs, kcpuid should only process CPUID ranges that are valid for the current CPU vendor. Restrict for_each_cpuid_range() to only iterate over CPUID ranges that are known to be valid for this CPU vendor. Doing it at the iterator level avoids sprinkling ugly CPU-vendor CPUID range validity conditionals throughout the code. Overall, this allows adding vendor-specific CPUID rages to the CSV file at later commits. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 36efcb753b77..3153c8eba0c4 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -118,7 +118,9 @@ static char *range_to_str(struct cpuid_range *range) =20 #define for_each_cpuid_range(range) \ for (unsigned int i =3D 0; \ - i < ARRAY_SIZE(ranges) && ((range) =3D &ranges[i]); \ + i < ARRAY_SIZE(ranges) && \ + ((range) =3D &ranges[i]) && \ + (range->vendors & this_cpu_vendor); \ i++) =20 struct cpuid_range *index_to_cpuid_range(u32 index) --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6B39027C142 for ; Thu, 6 Mar 2025 20:50:48 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294249; cv=none; b=o2VzVdyErIBm4au63r0ta8x18gbbCcwmY1GoR8/MJXS4iY2ZCxQ0Dz5T0h+LMbb+oSF7jrIcB8us1GIrTyjZvbrp3a47drB88bbiggUobre99962BrnQck0ZdLbp9+B6VtrdAw3Y/snBBONgFH68MNTcXUHgS9WmbSnn7Zq7sHg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294249; c=relaxed/simple; bh=V1xKLv7fGjTGyGSTuQoHum7FUR9cS3g9ZcWAgCPS5BM=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Yjk+xVFbyYmf+4ufsSlWzIlePh+WDT0WpW43C3s8yHQadSUZxZ+3enWGjNXG15GmMdz3MGqsAINrBSmLnsUtc7aPxOFPq6P6ncHqBoLxV+F9qBKefOezUsJvldwgp6dhyZamvXHRn34+yBLcUR3H04y/0ldtZ8PC+tjI0dTZDKU= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=QnJn8V6C; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=YGrG9CEI; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="QnJn8V6C"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="YGrG9CEI" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 09/12] tools/x86/kcpuid: Define Transmeta and Centaur index ranges Date: Thu, 6 Mar 2025 21:49:57 +0100 Message-ID: <20250306205000.227399-10-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Explicitly define the CPUID index ranges for Transmeta (0x80860000) and Centaur/Zhaoxin (0xc0000000). Without these explicit definitions, their respective CPUID indices would be skipped during CSV bitfield parsing. Signed-off-by: Ahmed S. Darwish --- tools/arch/x86/kcpuid/kcpuid.c | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/tools/arch/x86/kcpuid/kcpuid.c b/tools/arch/x86/kcpuid/kcpuid.c index 3153c8eba0c4..823226fbf089 100644 --- a/tools/arch/x86/kcpuid/kcpuid.c +++ b/tools/arch/x86/kcpuid/kcpuid.c @@ -83,6 +83,8 @@ static enum cpu_vendor this_cpu_vendor; enum range_index { RANGE_STD =3D 0, /* Standard */ RANGE_EXT =3D 0x80000000, /* Extended */ + RANGE_TSM =3D 0x80860000, /* Transmeta */ + RANGE_CTR =3D 0xc0000000, /* Centaur/Zhaoxin */ }; =20 #define CPUID_INDEX_MASK 0xffff0000 @@ -105,6 +107,12 @@ static struct cpuid_range ranges[] =3D { { .index =3D RANGE_EXT, .vendors =3D VENDOR_ALL, }, + { .index =3D RANGE_TSM, + .vendors =3D VENDOR_TRANSMETA, + }, + { .index =3D RANGE_CTR, + .vendors =3D VENDOR_CENTAUR, + }, }; =20 static char *range_to_str(struct cpuid_range *range) @@ -112,6 +120,8 @@ static char *range_to_str(struct cpuid_range *range) switch (range->index) { case RANGE_STD: return "Standard"; case RANGE_EXT: return "Extended"; + case RANGE_TSM: return "Transmeta"; + case RANGE_CTR: return "Centaur"; default: return NULL; } } --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 90BA627C15F for ; Thu, 6 Mar 2025 20:50:51 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294255; cv=none; b=OLPWe0xku3mWGUZyoPmgGAdcCV6HK+rBK4NSFub27tovzuFx62dks5+D34q3Da5MyVxgM+gjfr/Iu6RsZWaUl3jaDXXsKoTs+E0jygdtO9FVnd76auHCz8p2Wf1ZdvsQwGiDuNiuOd51T9y2rVxTeMoKxDdU7QLss3H3L/uBMuY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294255; c=relaxed/simple; bh=CDk77YhcDwHD7SxLsPTArhvw0AVPf0GzG24guE0WIkU=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=P3xGjc2GdoOlu5dMHUsSrtaHQBZsQJtPBCNsMPEBE92lcYog0huiDQxeZxEyYSKYnxwRNanmEkdeWgWlCzp0TSzWalDNLuMYdo4wLSGgYK3W66zjMe726i3jRHVi5WiIbGQYv7w9KTTZBZyVZTJ47+vk0m3sTxYoopKk+IJ8nus= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de; spf=pass smtp.mailfrom=linutronix.de; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=nyDKOZ/R; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b=A1qcp3Y1; arc=none smtp.client-ip=193.142.43.55 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linutronix.de Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="nyDKOZ/R"; dkim=permerror (0-bit key) header.d=linutronix.de header.i=@linutronix.de header.b="A1qcp3Y1" From: "Ahmed S. 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 10/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.0 Date: Thu, 6 Mar 2025 21:49:58 +0100 Message-ID: <20250306205000.227399-11-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV file to version v2.0, as generated by the x86-cpuid-db project. Summary of the v2.0 changes: - Introduce the leaves: - Leaf 0x00000003, Transmeta Processor serial number - Leaf 0x80860000, Transmeta max leaf number + CPU vendor ID - Leaf 0x80860001, Transmeta extended CPU information - Leaf 0x80860002, Transmeta Code Morphing Software (CMS) enumeration - Leaf 0x80860003 =3D> 0x80860006, Transmeta CPU information string - Leaf 0x80860007, Transmeta "live" CPU information - Leaf 0xc0000000, Centaur/Zhaoxin's max leaf number - Leaf 0xc0000001, Centaur/Zhaoxin's extended CPU features - Add a 0x prefix for leaves 0x0 to 0x9. This maintains consistency with the rest of the CSV entries. - Add new bitfields: - Leaf 0x7: nmi_src, NMI-source reporting with FRED event data - Leaf 0x80000001: e_base_type and e_mmx (Transmeta) - Update the section headers for leaves 0x80000000 and 0x80000005 to indicate that they are also valid for Transmeta CPUs. Signed-off-by: Ahmed S. Darwish Link: https://lkml.kernel.org/r/ZwU0HtmCTj2rF2T8@lx-t490 --- tools/arch/x86/kcpuid/cpuid.csv | 648 +++++++++++++++++++------------- 1 file changed, 382 insertions(+), 266 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index d751eb8585d0..d0f7159f99ba 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v1.0 +# Generator: x86-cpuid-db v2.0 =20 # # Auto-generated file. @@ -12,297 +12,306 @@ # Leaf 0H # Maximum standard leaf number + CPU vendor string =20 - 0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported - 0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 - 0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 - 0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 + 0x0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported + 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 + 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 + 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 =20 # Leaf 1H # CPU FMS (Family/Model/Stepping) + standard feature flags =20 - 1, 0, eax, 3:0, stepping , Stepping= ID - 1, 0, eax, 7:4, base_model , Base CPU= model ID - 1, 0, eax, 11:8, base_family_id , Base CPU= family ID - 1, 0, eax, 13:12, cpu_type , CPU type - 1, 0, eax, 19:16, ext_model , Extended= CPU model ID - 1, 0, eax, 27:20, ext_family , Extended= CPU family ID - 1, 0, ebx, 7:0, brand_id , Brand in= dex - 1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size - 1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count - 1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID - 1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) - 1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support - 1, 0, ecx, 2, dtes64 , 64-bit D= S save area - 1, 0, ecx, 3, monitor , MONITOR/= MWAIT support - 1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store - 1, 0, ecx, 5, vmx , Virtual = Machine Extensions - 1, 0, ecx, 6, smx , Safer Mo= de Extensions - 1, 0, ecx, 7, est , Enhanced= Intel SpeedStep - 1, 0, ecx, 8, tm2 , Thermal = Monitor 2 - 1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 - 1, 0, ecx, 10, cid , L1 Conte= xt ID - 1, 0, ecx, 11, sdbg , Sillicon= Debug - 1, 0, ecx, 12, fma , FMA exte= nsions using YMM state - 1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support - 1, 0, ecx, 14, xtpr , xTPR Upd= ate Control - 1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability - 1, 0, ecx, 17, pcid , Process-= context identifiers - 1, 0, ecx, 18, dca , Direct C= ache Access - 1, 0, ecx, 19, sse4_1 , SSE4.1 - 1, 0, ecx, 20, sse4_2 , SSE4.2 - 1, 0, ecx, 21, x2apic , X2APIC s= upport - 1, 0, ecx, 22, movbe , MOVBE in= struction support - 1, 0, ecx, 23, popcnt , POPCNT i= nstruction support - 1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation - 1, 0, ecx, 25, aes , AES inst= ructions - 1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support - 1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS - 1, 0, ecx, 28, avx , AVX inst= ructions support - 1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support - 1, 0, ecx, 30, rdrand , RDRAND i= nstruction support - 1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system - 1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) - 1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions - 1, 0, edx, 2, de , Debuggin= g Extensions - 1, 0, edx, 3, pse , Page Siz= e Extension - 1, 0, edx, 4, tsc , Time Sta= mp Counter - 1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) - 1, 0, edx, 6, pae , Physical= Address Extensions - 1, 0, edx, 7, mce , Machine = Check Exception - 1, 0, edx, 8, cx8 , CMPXCHG8= B instruction - 1, 0, edx, 9, apic , APIC on-= chip - 1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs - 1, 0, edx, 12, mtrr , Memory T= ype Range Registers - 1, 0, edx, 13, pge , Page Glo= bal Extensions - 1, 0, edx, 14, mca , Machine = Check Architecture - 1, 0, edx, 15, cmov , Conditio= nal Move Instruction - 1, 0, edx, 16, pat , Page Att= ribute Table - 1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) - 1, 0, edx, 18, pn , Processo= r Serial Number - 1, 0, edx, 19, clflush , CLFLUSH = instruction - 1, 0, edx, 21, dts , Debug St= ore - 1, 0, edx, 22, acpi , Thermal = monitor and clock control - 1, 0, edx, 23, mmx , MMX inst= ructions - 1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions - 1, 0, edx, 25, sse , SSE inst= ructions - 1, 0, edx, 26, sse2 , SSE2 ins= tructions - 1, 0, edx, 27, ss , Self Sno= op - 1, 0, edx, 28, ht , Hyper-th= reading - 1, 0, edx, 29, tm , Thermal = Monitor - 1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved - 1, 0, edx, 31, pbe , Pending = Break Enable + 0x1, 0, eax, 3:0, stepping , Stepping= ID + 0x1, 0, eax, 7:4, base_model , Base CPU= model ID + 0x1, 0, eax, 11:8, base_family_id , Base CPU= family ID + 0x1, 0, eax, 13:12, cpu_type , CPU type + 0x1, 0, eax, 19:16, ext_model , Extended= CPU model ID + 0x1, 0, eax, 27:20, ext_family , Extended= CPU family ID + 0x1, 0, ebx, 7:0, brand_id , Brand in= dex + 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size + 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count + 0x1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID + 0x1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) + 0x1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support + 0x1, 0, ecx, 2, dtes64 , 64-bit D= S save area + 0x1, 0, ecx, 3, monitor , MONITOR/= MWAIT support + 0x1, 0, ecx, 4, ds_cpl , CPL Qual= ified Debug Store + 0x1, 0, ecx, 5, vmx , Virtual = Machine Extensions + 0x1, 0, ecx, 6, smx , Safer Mo= de Extensions + 0x1, 0, ecx, 7, est , Enhanced= Intel SpeedStep + 0x1, 0, ecx, 8, tm2 , Thermal = Monitor 2 + 0x1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 + 0x1, 0, ecx, 10, cid , L1 Conte= xt ID + 0x1, 0, ecx, 11, sdbg , Sillicon= Debug + 0x1, 0, ecx, 12, fma , FMA exte= nsions using YMM state + 0x1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support + 0x1, 0, ecx, 14, xtpr , xTPR Upd= ate Control + 0x1, 0, ecx, 15, pdcm , Perfmon = and Debug Capability + 0x1, 0, ecx, 17, pcid , Process-= context identifiers + 0x1, 0, ecx, 18, dca , Direct C= ache Access + 0x1, 0, ecx, 19, sse4_1 , SSE4.1 + 0x1, 0, ecx, 20, sse4_2 , SSE4.2 + 0x1, 0, ecx, 21, x2apic , X2APIC s= upport + 0x1, 0, ecx, 22, movbe , MOVBE in= struction support + 0x1, 0, ecx, 23, popcnt , POPCNT i= nstruction support + 0x1, 0, ecx, 24, tsc_deadline_timer , APIC tim= er one-shot operation + 0x1, 0, ecx, 25, aes , AES inst= ructions + 0x1, 0, ecx, 26, xsave , XSAVE (a= nd related instructions) support + 0x1, 0, ecx, 27, osxsave , XSAVE (a= nd related instructions) are enabled by OS + 0x1, 0, ecx, 28, avx , AVX inst= ructions support + 0x1, 0, ecx, 29, f16c , Half-pre= cision floating-point conversion support + 0x1, 0, ecx, 30, rdrand , RDRAND i= nstruction support + 0x1, 0, ecx, 31, guest_status , System i= s running as guest; (para-)virtualized system + 0x1, 0, edx, 0, fpu , Floating= -Point Unit on-chip (x87) + 0x1, 0, edx, 1, vme , Virtual-= 8086 Mode Extensions + 0x1, 0, edx, 2, de , Debuggin= g Extensions + 0x1, 0, edx, 3, pse , Page Siz= e Extension + 0x1, 0, edx, 4, tsc , Time Sta= mp Counter + 0x1, 0, edx, 5, msr , Model-Sp= ecific Registers (RDMSR and WRMSR support) + 0x1, 0, edx, 6, pae , Physical= Address Extensions + 0x1, 0, edx, 7, mce , Machine = Check Exception + 0x1, 0, edx, 8, cx8 , CMPXCHG8= B instruction + 0x1, 0, edx, 9, apic , APIC on-= chip + 0x1, 0, edx, 11, sep , SYSENTER= , SYSEXIT, and associated MSRs + 0x1, 0, edx, 12, mtrr , Memory T= ype Range Registers + 0x1, 0, edx, 13, pge , Page Glo= bal Extensions + 0x1, 0, edx, 14, mca , Machine = Check Architecture + 0x1, 0, edx, 15, cmov , Conditio= nal Move Instruction + 0x1, 0, edx, 16, pat , Page Att= ribute Table + 0x1, 0, edx, 17, pse36 , Page Siz= e Extension (36-bit) + 0x1, 0, edx, 18, pn , Processo= r Serial Number + 0x1, 0, edx, 19, clflush , CLFLUSH = instruction + 0x1, 0, edx, 21, dts , Debug St= ore + 0x1, 0, edx, 22, acpi , Thermal = monitor and clock control + 0x1, 0, edx, 23, mmx , MMX inst= ructions + 0x1, 0, edx, 24, fxsr , FXSAVE a= nd FXRSTOR instructions + 0x1, 0, edx, 25, sse , SSE inst= ructions + 0x1, 0, edx, 26, sse2 , SSE2 ins= tructions + 0x1, 0, edx, 27, ss , Self Sno= op + 0x1, 0, edx, 28, ht , Hyper-th= reading + 0x1, 0, edx, 29, tm , Thermal = Monitor + 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved + 0x1, 0, edx, 31, pbe , Pending = Break Enable =20 # Leaf 2H # Intel cache and TLB information one-byte descriptors =20 - 2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried - 2, 0, eax, 15:8, desc1 , Descript= or #1 - 2, 0, eax, 23:16, desc2 , Descript= or #2 - 2, 0, eax, 30:24, desc3 , Descript= or #3 - 2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set - 2, 0, ebx, 7:0, desc4 , Descript= or #4 - 2, 0, ebx, 15:8, desc5 , Descript= or #5 - 2, 0, ebx, 23:16, desc6 , Descript= or #6 - 2, 0, ebx, 30:24, desc7 , Descript= or #7 - 2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set - 2, 0, ecx, 7:0, desc8 , Descript= or #8 - 2, 0, ecx, 15:8, desc9 , Descript= or #9 - 2, 0, ecx, 23:16, desc10 , Descript= or #10 - 2, 0, ecx, 30:24, desc11 , Descript= or #11 - 2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set - 2, 0, edx, 7:0, desc12 , Descript= or #12 - 2, 0, edx, 15:8, desc13 , Descript= or #13 - 2, 0, edx, 23:16, desc14 , Descript= or #14 - 2, 0, edx, 30:24, desc15 , Descript= or #15 - 2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + 0x2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried + 0x2, 0, eax, 15:8, desc1 , Descript= or #1 + 0x2, 0, eax, 23:16, desc2 , Descript= or #2 + 0x2, 0, eax, 30:24, desc3 , Descript= or #3 + 0x2, 0, eax, 31, eax_invalid , Descript= ors 1-3 are invalid if set + 0x2, 0, ebx, 7:0, desc4 , Descript= or #4 + 0x2, 0, ebx, 15:8, desc5 , Descript= or #5 + 0x2, 0, ebx, 23:16, desc6 , Descript= or #6 + 0x2, 0, ebx, 30:24, desc7 , Descript= or #7 + 0x2, 0, ebx, 31, ebx_invalid , Descript= ors 4-7 are invalid if set + 0x2, 0, ecx, 7:0, desc8 , Descript= or #8 + 0x2, 0, ecx, 15:8, desc9 , Descript= or #9 + 0x2, 0, ecx, 23:16, desc10 , Descript= or #10 + 0x2, 0, ecx, 30:24, desc11 , Descript= or #11 + 0x2, 0, ecx, 31, ecx_invalid , Descript= ors 8-11 are invalid if set + 0x2, 0, edx, 7:0, desc12 , Descript= or #12 + 0x2, 0, edx, 15:8, desc13 , Descript= or #13 + 0x2, 0, edx, 23:16, desc14 , Descript= or #14 + 0x2, 0, edx, 30:24, desc15 , Descript= or #15 + 0x2, 0, edx, 31, edx_invalid , Descript= ors 12-15 are invalid if set + +# Leaf 3H +# Transmeta Processor Serial Number (PSN) + + 0x3, 0, eax, 31:0, cpu_psn_0 , Processo= r Serial Number bytes 0 - 3 + 0x3, 0, ebx, 31:0, cpu_psn_1 , Processo= r Serial Number bytes 4 - 7 + 0x3, 0, ecx, 31:0, cpu_psn_2 , Processo= r Serial Number bytes 8 - 11 + 0x3, 0, edx, 31:0, cpu_psn_3 , Processo= r Serial Number bytes 12 - 15 =20 # Leaf 4H # Intel deterministic cache parameters =20 - 4, 31:0, eax, 4:0, cache_type , Cache ty= pe field - 4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) - 4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level - 4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache - 4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache - 4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package - 4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) - 4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) - 4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) - 4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) - 4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches - 4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches - 4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) + 0x4, 31:0, eax, 4:0, cache_type , Cache ty= pe field + 0x4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) + 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level + 0x4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache + 0x4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache + 0x4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package + 0x4, 31:0, ebx, 11:0, cache_linesize , System c= oherency line size (0-based) + 0x4, 31:0, ebx, 21:12, cache_npartitions , Physical= line partitions (0-based) + 0x4, 31:0, ebx, 31:22, cache_nways , Ways of = associativity (0-based) + 0x4, 31:0, ecx, 30:0, cache_nsets , Cache nu= mber of sets (0-based) + 0x4, 31:0, edx, 0, wbinvd_rll_no_guarantee, WBINVD/I= NVD not guaranteed for Remote Lower-Level caches + 0x4, 31:0, edx, 1, ll_inclusive , Cache is= inclusive of Lower-Level caches + 0x4, 31:0, edx, 2, complex_indexing , Not a di= rect-mapped cache (complex function) =20 # Leaf 5H # MONITOR/MWAIT instructions enumeration =20 - 5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes - 5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes - 5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported - 5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported - 5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT - 5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT - 5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT - 5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT - 5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT - 5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT - 5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT - 5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT + 0x5, 0, eax, 15:0, min_mon_size , Smallest= monitor-line size, in bytes + 0x5, 0, ebx, 15:0, max_mon_size , Largest = monitor-line size, in bytes + 0x5, 0, ecx, 0, mwait_ext , Enumerat= ion of MONITOR/MWAIT extensions is supported + 0x5, 0, ecx, 1, mwait_irq_break , Interrup= ts as a break-event for MWAIT is supported + 0x5, 0, edx, 3:0, n_c0_substates , Number o= f C0 sub C-states supported using MWAIT + 0x5, 0, edx, 7:4, n_c1_substates , Number o= f C1 sub C-states supported using MWAIT + 0x5, 0, edx, 11:8, n_c2_substates , Number o= f C2 sub C-states supported using MWAIT + 0x5, 0, edx, 15:12, n_c3_substates , Number o= f C3 sub C-states supported using MWAIT + 0x5, 0, edx, 19:16, n_c4_substates , Number o= f C4 sub C-states supported using MWAIT + 0x5, 0, edx, 23:20, n_c5_substates , Number o= f C5 sub C-states supported using MWAIT + 0x5, 0, edx, 27:24, n_c6_substates , Number o= f C6 sub C-states supported using MWAIT + 0x5, 0, edx, 31:28, n_c7_substates , Number o= f C7 sub C-states supported using MWAIT =20 # Leaf 6H # Thermal and Power Management enumeration =20 - 6, 0, eax, 0, dtherm , Digital = temprature sensor - 6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost - 6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) - 6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event - 6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension - 6, 0, eax, 6, pts , Package = thermal management - 6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported - 6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) - 6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported - 6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference - 6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request - 6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported - 6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 - 6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change - 6, 0, eax, 16, hwp_peci_override , HWP PECI= override - 6, 0, eax, 17, hwp_flexible , Flexible= HWP - 6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode - 6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported - 6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported - 6, 0, eax, 23, thread_director , Intel th= read director support - 6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported - 6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds - 6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) - 6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support - 6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director - 6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting - 6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting - 6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages - 6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based + 0x6, 0, eax, 0, dtherm , Digital = temprature sensor + 0x6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost + 0x6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) + 0x6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event + 0x6, 0, eax, 5, ecmd , Clock mo= dulation duty cycle extension + 0x6, 0, eax, 6, pts , Package = thermal management + 0x6, 0, eax, 7, hwp , HWP (Har= dware P-states) base registers are supported + 0x6, 0, eax, 8, hwp_notify , HWP noti= fication (IA32_HWP_INTERRUPT MSR) + 0x6, 0, eax, 9, hwp_act_window , HWP acti= vity window (IA32_HWP_REQUEST[bits 41:32]) supported + 0x6, 0, eax, 10, hwp_epp , HWP Ener= gy Performance Preference + 0x6, 0, eax, 11, hwp_pkg_req , HWP Pack= age Level Request + 0x6, 0, eax, 13, hdc_base_regs , HDC base= registers are supported + 0x6, 0, eax, 14, turbo_boost_3_0 , Intel Tu= rbo Boost Max 3.0 + 0x6, 0, eax, 15, hwp_capabilities , HWP High= est Performance change + 0x6, 0, eax, 16, hwp_peci_override , HWP PECI= override + 0x6, 0, eax, 17, hwp_flexible , Flexible= HWP + 0x6, 0, eax, 18, hwp_fast , IA32_HWP= _REQUEST MSR fast access mode + 0x6, 0, eax, 19, hfi , HW_FEEDB= ACK MSRs supported + 0x6, 0, eax, 20, hwp_ignore_idle , Ignoring= idle logical CPU HWP req is supported + 0x6, 0, eax, 23, thread_director , Intel th= read director support + 0x6, 0, eax, 24, therm_interrupt_bit25 , IA32_THE= RM_INTERRUPT MSR bit 25 is supported + 0x6, 0, ebx, 3:0, n_therm_thresholds , Digital = thermometer thresholds + 0x6, 0, ecx, 0, aperfmperf , MPERF/AP= ERF MSRs (effective frequency interface) + 0x6, 0, ecx, 3, epb , IA32_ENE= RGY_PERF_BIAS MSR support + 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director + 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting + 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting + 0x6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages + 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based =20 # Leaf 7H # Extended CPU features enumeration =20 - 7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves - 7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support - 7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported - 7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) - 7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 - 7, 0, ebx, 4, hle , Hardware= Lock Elision - 7, 0, ebx, 5, avx2 , AVX2 ins= truction set - 7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions - 7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection - 7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 - 7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB - 7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) - 7, 0, ebx, 11, rtm , Intel re= stricted transactional memory - 7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring - 7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) - 7, 0, ebx, 14, mpx , Intel me= mory protection extensions - 7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent - 7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions - 7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions - 7, 0, ebx, 18, rdseed , RDSEED i= nstruction - 7, 0, ebx, 19, adx , ADCX/ADO= X instructions - 7, 0, ebx, 20, smap , Supervis= or mode access prevention - 7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add - 7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction - 7, 0, ebx, 24, clwb , CLWB ins= truction - 7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace - 7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions - 7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs - 7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs - 7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions - 7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions - 7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions - 7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) - 7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs - 7, 0, ecx, 2, umip , User mod= e instruction protection - 7, 0, ecx, 3, pku , Protecti= on keys for user-space - 7, 0, ecx, 4, ospke , OS prote= ction keys enable - 7, 0, ecx, 5, waitpkg , WAITPKG = instructions - 7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 - 7, 0, ecx, 7, cet_ss , CET shad= ow stack features - 7, 0, ecx, 8, gfni , Galois f= ield new instructions - 7, 0, ecx, 9, vaes , Vector A= ES instrs - 7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support - 7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions - 7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle - 7, 0, ecx, 13, tme , Intel to= tal memory encryption - 7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW - 7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) - 7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode - 7, 0, ecx, 22, rdpid , RDPID in= struction - 7, 0, ecx, 23, key_locker , Intel ke= y locker support - 7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection - 7, 0, ecx, 25, cldemote , CLDEMOTE= instruction - 7, 0, ecx, 27, movdiri , MOVDIRI = instruction - 7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction - 7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) - 7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration - 7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages - 7, 0, edx, 1, sgx_keys , Intel SG= X attestation services - 7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions - 7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision - 7, 0, edx, 4, fsrm , Fast sho= rt REP MOV - 7, 0, edx, 5, uintr , CPU supp= orts user interrupts - 7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions - 7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available - 7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support - 7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts - 7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported - 7, 0, edx, 14, serialize , SERIALIZ= E instruction - 7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' - 7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking - 7, 0, edx, 18, pconfig , PCONFIG = instruction - 7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs - 7, 0, edx, 20, ibt , CET indi= rect branch tracking - 7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support - 7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions - 7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support - 7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support - 7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) - 7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors - 7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR - 7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR - 7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR - 7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable - 7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions - 7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions - 7, 1, eax, 6, lass , Linear a= ddress space separation - 7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions - 7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported - 7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB - 7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB - 7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB - 7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions - 7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS - 7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) - 7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations - 7, 1, eax, 22, hreset , History = reset support - 7, 1, eax, 23, avx_ifma , Integer = fused multiply add - 7, 1, eax, 26, lam , Linear a= ddress masking - 7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions - 7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) - 7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions - 7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions - 7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) - 7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions - 7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use - 7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable - 7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} - 7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} - 7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U - 7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S - 7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed - 7, 2, edx, 6, uclock_disable , UC-lock = disable is supported + 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves + 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support + 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported + 0x7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) + 0x7, 0, ebx, 3, bmi1 , Bit mani= pulation extensions group 1 + 0x7, 0, ebx, 4, hle , Hardware= Lock Elision + 0x7, 0, ebx, 5, avx2 , AVX2 ins= truction set + 0x7, 0, ebx, 6, fdp_excptn_only , FPU Data= Pointer updated only on x87 exceptions + 0x7, 0, ebx, 7, smep , Supervis= or Mode Execution Protection + 0x7, 0, ebx, 8, bmi2 , Bit mani= pulation extensions group 2 + 0x7, 0, ebx, 9, erms , Enhanced= REP MOVSB/STOSB + 0x7, 0, ebx, 10, invpcid , INVPCID = instruction (Invalidate Processor Context ID) + 0x7, 0, ebx, 11, rtm , Intel re= stricted transactional memory + 0x7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring + 0x7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) + 0x7, 0, ebx, 14, mpx , Intel me= mory protection extensions + 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent + 0x7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions + 0x7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions + 0x7, 0, ebx, 18, rdseed , RDSEED i= nstruction + 0x7, 0, ebx, 19, adx , ADCX/ADO= X instructions + 0x7, 0, ebx, 20, smap , Supervis= or mode access prevention + 0x7, 0, ebx, 21, avx512ifma , AVX-512 = integer fused multiply add + 0x7, 0, ebx, 23, clflushopt , CLFLUSHO= PT instruction + 0x7, 0, ebx, 24, clwb , CLWB ins= truction + 0x7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace + 0x7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions + 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs + 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs + 0x7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions + 0x7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions + 0x7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions + 0x7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) + 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs + 0x7, 0, ecx, 2, umip , User mod= e instruction protection + 0x7, 0, ecx, 3, pku , Protecti= on keys for user-space + 0x7, 0, ecx, 4, ospke , OS prote= ction keys enable + 0x7, 0, ecx, 5, waitpkg , WAITPKG = instructions + 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 + 0x7, 0, ecx, 7, cet_ss , CET shad= ow stack features + 0x7, 0, ecx, 8, gfni , Galois f= ield new instructions + 0x7, 0, ecx, 9, vaes , Vector A= ES instrs + 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support + 0x7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions + 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle + 0x7, 0, ecx, 13, tme , Intel to= tal memory encryption + 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW + 0x7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) + 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode + 0x7, 0, ecx, 22, rdpid , RDPID in= struction + 0x7, 0, ecx, 23, key_locker , Intel ke= y locker support + 0x7, 0, ecx, 24, bus_lock_detect , OS bus-l= ock detection + 0x7, 0, ecx, 25, cldemote , CLDEMOTE= instruction + 0x7, 0, ecx, 27, movdiri , MOVDIRI = instruction + 0x7, 0, ecx, 28, movdir64b , MOVDIR64= B instruction + 0x7, 0, ecx, 29, enqcmd , Enqueue = stores supported (ENQCMD{,S}) + 0x7, 0, ecx, 30, sgx_lc , Intel SG= X launch configuration + 0x7, 0, ecx, 31, pks , Protecti= on keys for supervisor-mode pages + 0x7, 0, edx, 1, sgx_keys , Intel SG= X attestation services + 0x7, 0, edx, 2, avx512_4vnniw , AVX-512 = neural network instructions + 0x7, 0, edx, 3, avx512_4fmaps , AVX-512 = multiply accumulation single precision + 0x7, 0, edx, 4, fsrm , Fast sho= rt REP MOV + 0x7, 0, edx, 5, uintr , CPU supp= orts user interrupts + 0x7, 0, edx, 8, avx512_vp2intersect , VP2INTER= SECT{D,Q} instructions + 0x7, 0, edx, 9, srdbs_ctrl , SRBDS mi= tigation MSR available + 0x7, 0, edx, 10, md_clear , VERW MD_= CLEAR microcode support + 0x7, 0, edx, 11, rtm_always_abort , XBEGIN (= RTM transaction) always aborts + 0x7, 0, edx, 13, tsx_force_abort , MSR TSX_= FORCE_ABORT, RTM_ABORT bit, supported + 0x7, 0, edx, 14, serialize , SERIALIZ= E instruction + 0x7, 0, edx, 15, hybrid_cpu , The CPU = is identified as a 'hybrid part' + 0x7, 0, edx, 16, tsxldtrk , TSX susp= end/resume load address tracking + 0x7, 0, edx, 18, pconfig , PCONFIG = instruction + 0x7, 0, edx, 19, arch_lbr , Intel ar= chitectural LBRs + 0x7, 0, edx, 20, ibt , CET indi= rect branch tracking + 0x7, 0, edx, 22, amx_bf16 , AMX-BF16= : tile bfloat16 support + 0x7, 0, edx, 23, avx512_fp16 , AVX-512 = FP16 instructions + 0x7, 0, edx, 24, amx_tile , AMX-TILE= : tile architecture support + 0x7, 0, edx, 25, amx_int8 , AMX-INT8= : tile 8-bit integer support + 0x7, 0, edx, 26, spec_ctrl , Speculat= ion Control (IBRS/IBPB: indirect branch restrictions) + 0x7, 0, edx, 27, intel_stibp , Single t= hread indirect branch predictors + 0x7, 0, edx, 28, flush_l1d , FLUSH L1= D cache: IA32_FLUSH_CMD MSR + 0x7, 0, edx, 29, arch_capabilities , Intel IA= 32_ARCH_CAPABILITIES MSR + 0x7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR + 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable + 0x7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions + 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions + 0x7, 1, eax, 6, lass , Linear a= ddress space separation + 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported + 0x7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB + 0x7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB + 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB + 0x7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions + 0x7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS + 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) + 0x7, 1, eax, 20, nmi_src , NMI-sour= ce reporting with FRED event data + 0x7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations + 0x7, 1, eax, 22, hreset , History = reset support + 0x7, 1, eax, 23, avx_ifma , Integer = fused multiply add + 0x7, 1, eax, 26, lam , Linear a= ddress masking + 0x7, 1, eax, 27, rd_wr_msrlist , RDMSRLIS= T/WRMSRLIST instructions + 0x7, 1, ebx, 0, intel_ppin , Protecte= d processor inventory number (PPIN{,_CTL} MSRs) + 0x7, 1, edx, 4, avx_vnni_int8 , AVX-VNNI= -INT8 instructions + 0x7, 1, edx, 5, avx_ne_convert , AVX-NE-C= ONVERT instructions + 0x7, 1, edx, 8, amx_complex , AMX-COMP= LEX instructions (starting from Granite Rapids) + 0x7, 1, edx, 14, prefetchit_0_1 , PREFETCH= IT0/1 instructions + 0x7, 1, edx, 18, cet_sss , CET supe= rvisor shadow stacks safe to use + 0x7, 2, edx, 0, intel_psfd , Intel pr= edictive store forward disable + 0x7, 2, edx, 1, ipred_ctrl , MSR bits= IA32_SPEC_CTRL.IPRED_DIS_{U,S} + 0x7, 2, edx, 2, rrsba_ctrl , MSR bits= IA32_SPEC_CTRL.RRSBA_DIS_{U,S} + 0x7, 2, edx, 3, ddp_ctrl , MSR bit = IA32_SPEC_CTRL.DDPD_U + 0x7, 2, edx, 4, bhi_ctrl , MSR bit = IA32_SPEC_CTRL.BHI_DIS_S + 0x7, 2, edx, 5, mcdt_no , MCDT mit= igation not needed + 0x7, 2, edx, 6, uclock_disable , UC-lock = disable is supported =20 # Leaf 9H # Intel DCA (Direct Cache Access) enumeration =20 - 9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS + 0x9, 0, eax, 0, dca_enabled_in_bios , DCA is e= nabled in BIOS =20 # Leaf AH # Intel PMU (Performance Monitoring Unit) enumeration @@ -623,7 +632,7 @@ 0x40000000, 0, edx, 31:0, hypervisor_id_2 , Hypervis= or ID string bytes 8 - 11 =20 # Leaf 80000000H -# Maximum extended leaf number + CPU vendor string (AMD) +# Maximum extended leaf number + AMD/Transmeta CPU vendor string =20 0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended cpuid leaf supported 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 @@ -636,6 +645,7 @@ 0x80000001, 0, eax, 3:0, e_stepping_id , Stepping= ID 0x80000001, 0, eax, 7:4, e_base_model , Base pro= cessor model 0x80000001, 0, eax, 11:8, e_base_family , Base pro= cessor family +0x80000001, 0, eax, 13:12, e_base_type , Base pro= cessor type (Transmeta) 0x80000001, 0, eax, 19:16, e_ext_model , Extended= processor model 0x80000001, 0, eax, 27:20, e_ext_family , Extended= processor family 0x80000001, 0, ebx, 15:0, brand_id , Brand ID @@ -687,6 +697,7 @@ 0x80000001, 0, edx, 19, mp , Out-of-s= pec AMD Multiprocessing bit 0x80000001, 0, edx, 20, nx , No-execu= te page protection 0x80000001, 0, edx, 22, mmxext , AMD MMX = extensions +0x80000001, 0, edx, 23, e_mmx , MMX inst= ructions (Transmeta) 0x80000001, 0, edx, 24, e_fxsr , FXSAVE a= nd FXRSTOR instructions 0x80000001, 0, edx, 25, fxsr_opt , FXSAVE a= nd FXRSTOR optimizations 0x80000001, 0, edx, 26, pdpe1gb , 1-GB lar= ge page support @@ -720,7 +731,7 @@ 0x80000004, 0, edx, 31:0, cpu_brandid_11 , CPU bran= d ID string, bytes 44 - 47 =20 # Leaf 80000005H -# AMD L1 cache and L1 TLB enumeration +# AMD/Transmeta L1 cache and L1 TLB enumeration =20 0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entires, 2M and 4M pages 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages @@ -1051,3 +1062,108 @@ 0x80000026, 3:0, ecx, 7:0, domain_level , This dom= ain level (subleaf ID) 0x80000026, 3:0, ecx, 15:8, domain_type , This dom= ain type 0x80000026, 3:0, edx, 31:0, x2apic_id , x2APIC I= D of current logical CPU + +# Leaf 80860000H +# Maximum Transmeta leaf number + CPU vendor ID string + +0x80860000, 0, eax, 31:0, max_tra_leaf , Maximum = supported Transmeta leaf number +0x80860000, 0, ebx, 31:0, cpu_vendorid_0 , Transmet= a Vendor ID string bytes 0 - 3 +0x80860000, 0, ecx, 31:0, cpu_vendorid_2 , Transmet= a Vendor ID string bytes 8 - 11 +0x80860000, 0, edx, 31:0, cpu_vendorid_1 , Transmet= a Vendor ID string bytes 4 - 7 + +# Leaf 80860001H +# Transmeta extended CPU information + +0x80860001, 0, eax, 3:0, stepping , Stepping= ID +0x80860001, 0, eax, 7:4, base_model , Base CPU= model ID +0x80860001, 0, eax, 11:8, base_family_id , Base CPU= family ID +0x80860001, 0, eax, 13:12, cpu_type , CPU type +0x80860001, 0, ebx, 7:0, cpu_rev_mask_minor , CPU revi= sion ID, mask minor +0x80860001, 0, ebx, 15:8, cpu_rev_mask_major , CPU revi= sion ID, mask major +0x80860001, 0, ebx, 23:16, cpu_rev_minor , CPU revi= sion ID, minor +0x80860001, 0, ebx, 31:24, cpu_rev_major , CPU revi= sion ID, major +0x80860001, 0, ecx, 31:0, cpu_base_mhz , CPU nomi= nal frequency, in MHz +0x80860001, 0, edx, 0, recovery , Recovery= CMS is active (after bad flush) +0x80860001, 0, edx, 1, longrun , LongRun = power management capabilities +0x80860001, 0, edx, 3, lrti , LongRun = Table Interface + +# Leaf 80860002H +# Transmeta Code Morphing Software (CMS) enumeration + +0x80860002, 0, eax, 31:0, cpu_rev_id , CPU revi= sion ID +0x80860002, 0, ebx, 7:0, cms_rev_mask_2 , CMS revi= sion ID, mask component 2 +0x80860002, 0, ebx, 15:8, cms_rev_mask_1 , CMS revi= sion ID, mask component 1 +0x80860002, 0, ebx, 23:16, cms_rev_minor , CMS revi= sion ID, minor +0x80860002, 0, ebx, 31:24, cms_rev_major , CMS revi= sion ID, major +0x80860002, 0, ecx, 31:0, cms_rev_mask_3 , CMS revi= sion ID, mask component 3 + +# Leaf 80860003H +# Transmeta CPU information string, bytes 0 - 15 + +0x80860003, 0, eax, 31:0, cpu_info_0 , CPU info= string bytes 0 - 3 +0x80860003, 0, ebx, 31:0, cpu_info_1 , CPU info= string bytes 4 - 7 +0x80860003, 0, ecx, 31:0, cpu_info_2 , CPU info= string bytes 8 - 11 +0x80860003, 0, edx, 31:0, cpu_info_3 , CPU info= string bytes 12 - 15 + +# Leaf 80860004H +# Transmeta CPU information string, bytes 16 - 31 + +0x80860004, 0, eax, 31:0, cpu_info_4 , CPU info= string bytes 16 - 19 +0x80860004, 0, ebx, 31:0, cpu_info_5 , CPU info= string bytes 20 - 23 +0x80860004, 0, ecx, 31:0, cpu_info_6 , CPU info= string bytes 24 - 27 +0x80860004, 0, edx, 31:0, cpu_info_7 , CPU info= string bytes 28 - 31 + +# Leaf 80860005H +# Transmeta CPU information string, bytes 32 - 47 + +0x80860005, 0, eax, 31:0, cpu_info_8 , CPU info= string bytes 32 - 35 +0x80860005, 0, ebx, 31:0, cpu_info_9 , CPU info= string bytes 36 - 39 +0x80860005, 0, ecx, 31:0, cpu_info_10 , CPU info= string bytes 40 - 43 +0x80860005, 0, edx, 31:0, cpu_info_11 , CPU info= string bytes 44 - 47 + +# Leaf 80860006H +# Transmeta CPU information string, bytes 48 - 63 + +0x80860006, 0, eax, 31:0, cpu_info_12 , CPU info= string bytes 48 - 51 +0x80860006, 0, ebx, 31:0, cpu_info_13 , CPU info= string bytes 52 - 55 +0x80860006, 0, ecx, 31:0, cpu_info_14 , CPU info= string bytes 56 - 59 +0x80860006, 0, edx, 31:0, cpu_info_15 , CPU info= string bytes 60 - 63 + +# Leaf 80860007H +# Transmeta live CPU information + +0x80860007, 0, eax, 31:0, cpu_cur_mhz , Current = CPU frequency, in MHz +0x80860007, 0, ebx, 31:0, cpu_cur_voltage , Current = CPU voltage, in millivolts +0x80860007, 0, ecx, 31:0, cpu_cur_perf_pctg , Current = CPU performance percentage, 0 - 100d +0x80860007, 0, edx, 31:0, cpu_cur_gate_delay , Current = CPU gate delay, in femtoseconds + +# Leaf C0000000H +# Maximum Centaur/Zhaoxin leaf number + +0xc0000000, 0, eax, 31:0, max_cntr_leaf , Maximum = Centaur/Zhaoxin leaf number + +# Leaf C0000001H +# Centaur/Zhaoxin extended CPU features + +0xc0000001, 0, edx, 0, ccs_sm2 , CCS SM2 = instructions +0xc0000001, 0, edx, 1, ccs_sm2_en , CCS SM2 = enabled +0xc0000001, 0, edx, 2, xstore , Random N= umber Generator +0xc0000001, 0, edx, 3, xstore_en , RNG enab= led +0xc0000001, 0, edx, 4, ccs_sm3_sm4 , CCS SM3 = and SM4 instructions +0xc0000001, 0, edx, 5, ccs_sm3_sm4_en , CCS SM3/= SM4 enabled +0xc0000001, 0, edx, 6, ace , Advanced= Cryptography Engine +0xc0000001, 0, edx, 7, ace_en , ACE enab= led +0xc0000001, 0, edx, 8, ace2 , Advanced= Cryptography Engine v2 +0xc0000001, 0, edx, 9, ace2_en , ACE v2 e= nabled +0xc0000001, 0, edx, 10, phe , PadLock = Hash Engine +0xc0000001, 0, edx, 11, phe_en , PHE enab= led +0xc0000001, 0, edx, 12, pmm , PadLock = Montgomery Multiplier +0xc0000001, 0, edx, 13, pmm_en , PMM enab= led +0xc0000001, 0, edx, 16, parallax , Parallax= auto adjust processor voltage +0xc0000001, 0, edx, 17, parallax_en , Parallax= enabled +0xc0000001, 0, edx, 20, tm3 , Thermal = Monitor v3 +0xc0000001, 0, edx, 21, tm3_en , TM v3 en= abled +0xc0000001, 0, edx, 25, phe2 , PadLock = Hash Engine v2 (SHA384/SHA512) +0xc0000001, 0, edx, 26, phe2_en , PHE v2 e= nabled +0xc0000001, 0, edx, 27, rsa , RSA inst= ructions (XMODEXP/MONTMUL2) +0xc0000001, 0, edx, 28, rsa_en , RSA inst= ructions enabled --=20 2.48.1 From nobody Sun Feb 8 09:17:04 2026 Received: from galois.linutronix.de (Galois.linutronix.de [193.142.43.55]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C0B5A1FECA7 for ; Thu, 6 Mar 2025 20:50:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=193.142.43.55 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741294257; cv=none; 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 11/12] tools/x86/kcpuid: Update bitfields to x86-cpuid-db v2.2 Date: Thu, 6 Mar 2025 21:49:59 +0100 Message-ID: <20250306205000.227399-12-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Update kcpuid's CSV file from v2.0 to v2.2, as generated by the x86-cpuid-db project. * v2.1 changes summary: - Use a standardized style for all x86 trademarks, registers, opcodes, byte units, hexadecimal digits, and x86 technical terms. This was enforced by a number of x86-specfic hunspell(5) dictionary and affix files at the x86-cpuid-db project's CI pipeline. - Expand abbreviated terms that might be OK in code but not in official listings (e.g., "addr", "instr", "reg", "virt", etc.) - Add new Zen5 SoC bits to leaf 0x80000020 and leaf 0x80000021. * v2.2 changes summary: - Per Ingo Molnar's feedback on a related Linux kernel patch queue, it is desired to always use CPUID in its capitalized form. That quick v2.2 release fixed all instances of small case "cpuid" at the XML database, and thus the generated kcpuid CSV file. Signed-off-by: Ahmed S. Darwish Link: https://lkml.kernel.org/r/Z8hJhgGVduJWFqRE@lx-t490 Link: https://lkml.kernel.org/r/Z8bHK391zKE4gUEW@gmail.com --- Notes: No ANNOUNCE link for v2.2, as it was a very minor release and I didn't want to spam people inboxes. tools/arch/x86/kcpuid/cpuid.csv | 189 +++++++++++++++++--------------- 1 file changed, 100 insertions(+), 89 deletions(-) diff --git a/tools/arch/x86/kcpuid/cpuid.csv b/tools/arch/x86/kcpuid/cpuid.= csv index d0f7159f99ba..9613e09cbfb3 100644 --- a/tools/arch/x86/kcpuid/cpuid.csv +++ b/tools/arch/x86/kcpuid/cpuid.csv @@ -1,5 +1,5 @@ # SPDX-License-Identifier: CC0-1.0 -# Generator: x86-cpuid-db v2.0 +# Generator: x86-cpuid-db v2.2 =20 # # Auto-generated file. @@ -12,7 +12,7 @@ # Leaf 0H # Maximum standard leaf number + CPU vendor string =20 - 0x0, 0, eax, 31:0, max_std_leaf , Highest = cpuid standard leaf supported + 0x0, 0, eax, 31:0, max_std_leaf , Highest = standard CPUID leaf supported 0x0, 0, ebx, 31:0, cpu_vendorid_0 , CPU vend= or ID string bytes 0 - 3 0x0, 0, ecx, 31:0, cpu_vendorid_2 , CPU vend= or ID string bytes 8 - 11 0x0, 0, edx, 31:0, cpu_vendorid_1 , CPU vend= or ID string bytes 4 - 7 @@ -28,7 +28,7 @@ 0x1, 0, eax, 27:20, ext_family , Extended= CPU family ID 0x1, 0, ebx, 7:0, brand_id , Brand in= dex 0x1, 0, ebx, 15:8, clflush_size , CLFLUSH = instruction cache line size - 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU (HW threads) count + 0x1, 0, ebx, 23:16, n_logical_cpu , Logical = CPU count 0x1, 0, ebx, 31:24, local_apic_id , Initial = local APIC physical ID 0x1, 0, ecx, 0, pni , Streamin= g SIMD Extensions 3 (SSE3) 0x1, 0, ecx, 1, pclmulqdq , PCLMULQD= Q instruction support @@ -41,7 +41,7 @@ 0x1, 0, ecx, 8, tm2 , Thermal = Monitor 2 0x1, 0, ecx, 9, ssse3 , Suppleme= ntal SSE3 0x1, 0, ecx, 10, cid , L1 Conte= xt ID - 0x1, 0, ecx, 11, sdbg , Sillicon= Debug + 0x1, 0, ecx, 11, sdbg , Silicon = Debug 0x1, 0, ecx, 12, fma , FMA exte= nsions using YMM state 0x1, 0, ecx, 13, cx16 , CMPXCHG1= 6B instruction support 0x1, 0, ecx, 14, xtpr , xTPR Upd= ate Control @@ -89,13 +89,13 @@ 0x1, 0, edx, 27, ss , Self Sno= op 0x1, 0, edx, 28, ht , Hyper-th= reading 0x1, 0, edx, 29, tm , Thermal = Monitor - 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now resreved + 0x1, 0, edx, 30, ia64 , Legacy I= A-64 (Itanium) support bit, now reserved 0x1, 0, edx, 31, pbe , Pending = Break Enable =20 # Leaf 2H # Intel cache and TLB information one-byte descriptors =20 - 0x2, 0, eax, 7:0, iteration_count , Number o= f times this CPUD leaf must be queried + 0x2, 0, eax, 7:0, iteration_count , Number o= f times this leaf must be queried 0x2, 0, eax, 15:8, desc1 , Descript= or #1 0x2, 0, eax, 23:16, desc2 , Descript= or #2 0x2, 0, eax, 30:24, desc3 , Descript= or #3 @@ -129,7 +129,7 @@ =20 0x4, 31:0, eax, 4:0, cache_type , Cache ty= pe field 0x4, 31:0, eax, 7:5, cache_level , Cache le= vel (1-based) - 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tialializing cache level + 0x4, 31:0, eax, 8, cache_self_init , Self-ini= tializing cache level 0x4, 31:0, eax, 9, fully_associative , Fully-as= sociative cache 0x4, 31:0, eax, 25:14, num_threads_sharing , Number l= ogical CPUs sharing this cache 0x4, 31:0, eax, 31:26, num_cores_on_die , Number o= f cores in the physical package @@ -160,7 +160,7 @@ # Leaf 6H # Thermal and Power Management enumeration =20 - 0x6, 0, eax, 0, dtherm , Digital = temprature sensor + 0x6, 0, eax, 0, dtherm , Digital = temperature sensor 0x6, 0, eax, 1, turbo_boost , Intel Tu= rbo Boost 0x6, 0, eax, 2, arat , Always-R= unning APIC Timer (not affected by p-state) 0x6, 0, eax, 4, pln , Power Li= mit Notification (PLN) event @@ -187,13 +187,13 @@ 0x6, 0, ecx, 15:8, thrd_director_nclasses , Number o= f classes, Intel thread director 0x6, 0, edx, 0, perfcap_reporting , Performa= nce capability reporting 0x6, 0, edx, 1, encap_reporting , Energy e= fficiency capability reporting - 0x6, 0, edx, 11:8, feedback_sz , HW feedb= ack interface struct size, in 4K pages - 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU index @ HW feedback struct, 0-based + 0x6, 0, edx, 11:8, feedback_sz , Feedback= interface structure size, in 4K pages + 0x6, 0, edx, 31:16, this_lcpu_hwfdbk_idx , This log= ical CPU hardware feedback interface index =20 # Leaf 7H # Extended CPU features enumeration =20 - 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f cpuid 0x7 subleaves + 0x7, 0, eax, 31:0, leaf7_n_subleaves , Number o= f leaf 0x7 subleaves 0x7, 0, ebx, 0, fsgsbase , FSBASE/G= SBASE read/write support 0x7, 0, ebx, 1, tsc_adjust , IA32_TSC= _ADJUST MSR supported 0x7, 0, ebx, 2, sgx , Intel SG= X (Software Guard Extensions) @@ -209,7 +209,7 @@ 0x7, 0, ebx, 12, cqm , Intel RD= T-CMT / AMD Platform-QoS cache monitoring 0x7, 0, ebx, 13, zero_fcs_fds , Deprecat= ed FPU CS/DS (stored as zero) 0x7, 0, ebx, 14, mpx , Intel me= mory protection extensions - 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcemeent + 0x7, 0, ebx, 15, rdt_a , Intel RD= T / AMD Platform-QoS Enforcement 0x7, 0, ebx, 16, avx512f , AVX-512 = foundation instructions 0x7, 0, ebx, 17, avx512dq , AVX-512 = double/quadword instructions 0x7, 0, ebx, 18, rdseed , RDSEED i= nstruction @@ -220,27 +220,27 @@ 0x7, 0, ebx, 24, clwb , CLWB ins= truction 0x7, 0, ebx, 25, intel_pt , Intel pr= ocessor trace 0x7, 0, ebx, 26, avx512pf , AVX-512 = prefetch instructions - 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instrs - 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instrs + 0x7, 0, ebx, 27, avx512er , AVX-512 = exponent/reciprocal instructions + 0x7, 0, ebx, 28, avx512cd , AVX-512 = conflict detection instructions 0x7, 0, ebx, 29, sha_ni , SHA/SHA2= 56 instructions - 0x7, 0, ebx, 30, avx512bw , AVX-512 = BW (byte/word granular) instructions + 0x7, 0, ebx, 30, avx512bw , AVX-512 = byte/word instructions 0x7, 0, ebx, 31, avx512vl , AVX-512 = VL (128/256 vector length) extensions 0x7, 0, ecx, 0, prefetchwt1 , PREFETCH= WT1 (Intel Xeon Phi only) - 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instrs + 0x7, 0, ecx, 1, avx512vbmi , AVX-512 = Vector byte manipulation instructions 0x7, 0, ecx, 2, umip , User mod= e instruction protection 0x7, 0, ecx, 3, pku , Protecti= on keys for user-space 0x7, 0, ecx, 4, ospke , OS prote= ction keys enable 0x7, 0, ecx, 5, waitpkg , WAITPKG = instructions - 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instrs group 2 + 0x7, 0, ecx, 6, avx512_vbmi2 , AVX-512 = vector byte manipulation instructions group 2 0x7, 0, ecx, 7, cet_ss , CET shad= ow stack features 0x7, 0, ecx, 8, gfni , Galois f= ield new instructions - 0x7, 0, ecx, 9, vaes , Vector A= ES instrs + 0x7, 0, ecx, 9, vaes , Vector A= ES instructions 0x7, 0, ecx, 10, vpclmulqdq , VPCLMULQ= DQ 256-bit instruction support 0x7, 0, ecx, 11, avx512_vnni , Vector n= eural network instructions - 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bit count/shiffle + 0x7, 0, ecx, 12, avx512_bitalg , AVX-512 = bitwise algorithms 0x7, 0, ecx, 13, tme , Intel to= tal memory encryption - 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DW/QW - 0x7, 0, ecx, 16, la57 , 57-bit l= inear addreses (five-level paging) + 0x7, 0, ecx, 14, avx512_vpopcntdq , AVX-512:= POPCNT for vectors of DWORD/QWORD + 0x7, 0, ecx, 16, la57 , 57-bit l= inear addresses (five-level paging) 0x7, 0, ecx, 21:17, mawau_val_lm , BNDLDX/B= NDSTX MAWAU value in 64-bit mode 0x7, 0, ecx, 22, rdpid , RDPID in= struction 0x7, 0, ecx, 23, key_locker , Intel ke= y locker support @@ -278,16 +278,16 @@ 0x7, 0, edx, 30, core_capabilities , IA32_COR= E_CAPABILITIES MSR 0x7, 0, edx, 31, spec_ctrl_ssbd , Speculat= ive store bypass disable 0x7, 1, eax, 4, avx_vnni , AVX-VNNI= instructions - 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bFloat16 instructions + 0x7, 1, eax, 5, avx512_bf16 , AVX-512 = bfloat16 instructions 0x7, 1, eax, 6, lass , Linear a= ddress space separation 0x7, 1, eax, 7, cmpccxadd , CMPccXAD= D instructions - 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: CPUID leaf 0x23 is supported + 0x7, 1, eax, 8, arch_perfmon_ext , ArchPerf= monExt: leaf 0x23 is supported 0x7, 1, eax, 10, fzrm , Fast zer= o-length REP MOVSB 0x7, 1, eax, 11, fsrs , Fast sho= rt REP STOSB 0x7, 1, eax, 12, fsrc , Fast Sho= rt REP CMPSB/SCASB 0x7, 1, eax, 17, fred , FRED: Fl= exible return and event delivery transitions 0x7, 1, eax, 18, lkgs , LKGS: Lo= ad 'kernel' (userspace) GS - 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instr (WRMSR-non-serializing) + 0x7, 1, eax, 19, wrmsrns , WRMSRNS = instruction (WRMSR-non-serializing) 0x7, 1, eax, 20, nmi_src , NMI-sour= ce reporting with FRED event data 0x7, 1, eax, 21, amx_fp16 , AMX-FP16= : FP16 tile operations 0x7, 1, eax, 22, hreset , History = reset support @@ -319,7 +319,7 @@ 0xa, 0, eax, 7:0, pmu_version , Performa= nce monitoring unit version ID 0xa, 0, eax, 15:8, pmu_n_gcounters , Number o= f general PMU counters per logical CPU 0xa, 0, eax, 23:16, pmu_gcounters_nbits , Bitwidth= of PMU general counters - 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length o= f cpuid leaf 0xa EBX bit vector + 0xa, 0, eax, 31:24, pmu_cpuid_ebx_bits , Length o= f leaf 0xa EBX bit vector 0xa, 0, ebx, 0, no_core_cycle_evt , Core cyc= le event not available 0xa, 0, ebx, 1, no_insn_retired_evt , Instruct= ion retired event not available 0xa, 0, ebx, 2, no_refcycle_evt , Referenc= e cycles event not available @@ -348,18 +348,18 @@ 0xd, 0, eax, 0, xcr0_x87 , XCR0.X87= (bit 0) supported 0xd, 0, eax, 1, xcr0_sse , XCR0.SEE= (bit 1) supported 0xd, 0, eax, 2, xcr0_avx , XCR0.AVX= (bit 2) supported - 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS (bit 3) supported (MPX BND0-BND3 regs) - 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) - 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK (bit 5) supported (AVX-512 k0-k7 regs) - 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) - 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) - 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U (bit 9) supported (XSAVE PKRU reg) - 0xd, 0, eax, 11, xcr0_cet_u , AMD XCR0= .CET_U (bit 11) supported (CET supervisor state) - 0xd, 0, eax, 12, xcr0_cet_s , AMD XCR0= .CET_S (bit 12) support (CET user state) + 0xd, 0, eax, 3, xcr0_mpx_bndregs , XCR0.BND= REGS (bit 3) supported (MPX BND0-BND3 registers) + 0xd, 0, eax, 4, xcr0_mpx_bndcsr , XCR0.BND= CSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) + 0xd, 0, eax, 5, xcr0_avx512_opmask , XCR0.OPM= ASK (bit 5) supported (AVX-512 k0-k7 registers) + 0xd, 0, eax, 6, xcr0_avx512_zmm_hi256 , XCR0.ZMM= _Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) + 0xd, 0, eax, 7, xcr0_avx512_hi16_zmm , XCR0.HI1= 6_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) + 0xd, 0, eax, 9, xcr0_pkru , XCR0.PKR= U (bit 9) supported (XSAVE PKRU registers) + 0xd, 0, eax, 11, xcr0_cet_u , XCR0.CET= _U (bit 11) supported (CET user state) + 0xd, 0, eax, 12, xcr0_cet_s , XCR0.CET= _S (bit 12) supported (CET supervisor state) 0xd, 0, eax, 17, xcr0_tileconfig , XCR0.TIL= ECONFIG (bit 17) supported (AMX can manage TILECONFIG) 0xd, 0, eax, 18, xcr0_tiledata , XCR0.TIL= EDATA (bit 18) supported (AMX can manage TILEDATA) - 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XR= STR area byte size, for XCR0 enabled features - 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XR= STR area max byte size, all CPU features + 0xd, 0, ebx, 31:0, xsave_sz_xcr0_enabled , XSAVE/XR= STOR area byte size, for XCR0 enabled features + 0xd, 0, ecx, 31:0, xsave_sz_max , XSAVE/XR= STOR area max byte size, all CPU features 0xd, 0, edx, 30, xcr0_lwp , AMD XCR0= .LWP (bit 62) supported (Light-weight Profiling) 0xd, 1, eax, 0, xsaveopt , XSAVEOPT= instruction 0xd, 1, eax, 1, xsavec , XSAVEC i= nstruction @@ -378,7 +378,7 @@ 0xd, 63:2, eax, 31:0, xsave_sz , Size of = save area for subleaf-N feature, in bytes 0xd, 63:2, ebx, 31:0, xsave_offset , Offset o= f save area for subleaf-N feature, in bytes 0xd, 63:2, ecx, 0, is_xss_bit , Subleaf = N describes an XSS bit, otherwise XCR0 bit - 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N feature xsave area is 64-byte aligned + 0xd, 63:2, ecx, 1, compacted_xsave_64byte_aligned, W= hen compacted, subleaf-N feature XSAVE area is 64-byte aligned =20 # Leaf FH # Intel RDT / AMD PQoS resource monitoring @@ -435,17 +435,17 @@ 0x12, 1, ecx, 0, xfrm_x87 , Enclave = XFRM.X87 (bit 0) supported 0x12, 1, ecx, 1, xfrm_sse , Enclave = XFRM.SEE (bit 1) supported 0x12, 1, ecx, 2, xfrm_avx , Enclave = XFRM.AVX (bit 2) supported - 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 regs) - 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS regs) - 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 regs) - 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 regs) - 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 regs) - 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (bit 9) supported (XSAVE PKRU reg) + 0x12, 1, ecx, 3, xfrm_mpx_bndregs , Enclave = XFRM.BNDREGS (bit 3) supported (MPX BND0-BND3 registers) + 0x12, 1, ecx, 4, xfrm_mpx_bndcsr , Enclave = XFRM.BNDCSR (bit 4) supported (MPX BNDCFGU/BNDSTATUS registers) + 0x12, 1, ecx, 5, xfrm_avx512_opmask , Enclave = XFRM.OPMASK (bit 5) supported (AVX-512 k0-k7 registers) + 0x12, 1, ecx, 6, xfrm_avx512_zmm_hi256 , Enclave = XFRM.ZMM_Hi256 (bit 6) supported (AVX-512 ZMM0->ZMM7/15 registers) + 0x12, 1, ecx, 7, xfrm_avx512_hi16_zmm , Enclave = XFRM.HI16_ZMM (bit 7) supported (AVX-512 ZMM16->ZMM31 registers) + 0x12, 1, ecx, 9, xfrm_pkru , Enclave = XFRM.PKRU (bit 9) supported (XSAVE PKRU registers) 0x12, 1, ecx, 17, xfrm_tileconfig , Enclave = XFRM.TILECONFIG (bit 17) supported (AMX can manage TILECONFIG) 0x12, 1, ecx, 18, xfrm_tiledata , Enclave = XFRM.TILEDATA (bit 18) supported (AMX can manage TILEDATA) 0x12, 31:2, eax, 3:0, subleaf_type , Subleaf = type (dictates output layout) - 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sect= ion base addr, bits[12:31] - 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sect= ion base addr, bits[32:51] + 0x12, 31:2, eax, 31:12, epc_sec_base_addr_0 , EPC sect= ion base address, bits[12:31] + 0x12, 31:2, ebx, 19:0, epc_sec_base_addr_1 , EPC sect= ion base address, bits[32:51] 0x12, 31:2, ecx, 3:0, epc_sec_type , EPC sect= ion type / property encoding 0x12, 31:2, ecx, 31:12, epc_sec_size_0 , EPC sect= ion size, bits[12:31] 0x12, 31:2, edx, 19:0, epc_sec_size_1 , EPC sect= ion size, bits[32:51] @@ -453,7 +453,7 @@ # Leaf 14H # Intel Processor Trace enumeration =20 - 0x14, 0, eax, 31:0, pt_max_subleaf , Max cpui= d 0x14 subleaf + 0x14, 0, eax, 31:0, pt_max_subleaf , Maximum = leaf 0x14 subleaf 0x14, 0, ebx, 0, cr3_filtering , IA32_RTI= T_CR3_MATCH is accessible 0x14, 0, ebx, 1, psb_cyc , Configur= able PSB and cycle-accurate mode 0x14, 0, ebx, 2, ip_filtering , IP/Trace= Stop filtering; Warm-reset PT MSRs preservation @@ -481,7 +481,7 @@ 0x15, 0, ecx, 31:0, cpu_crystal_hz , Core cry= stal clock nominal frequency, in Hz =20 # Leaf 16H -# Intel processor fequency enumeration +# Intel processor frequency enumeration =20 0x16, 0, eax, 15:0, cpu_base_mhz , Processo= r base frequency, in MHz 0x16, 0, ebx, 15:0, cpu_max_mhz , Processo= r max frequency, in MHz @@ -490,9 +490,9 @@ # Leaf 17H # Intel SoC vendor attributes enumeration =20 - 0x17, 0, eax, 31:0, soc_max_subleaf , Max cpui= d leaf 0x17 subleaf + 0x17, 0, eax, 31:0, soc_max_subleaf , Maximum = leaf 0x17 subleaf 0x17, 0, ebx, 15:0, soc_vendor_id , SoC vend= or ID - 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumaeratoion scheme (not Intel) + 0x17, 0, ebx, 16, is_vendor_scheme , Assigned= by industry enumeration scheme (not Intel) 0x17, 0, ecx, 31:0, soc_proj_id , SoC proj= ect ID, assigned by vendor 0x17, 0, edx, 31:0, soc_stepping_id , Soc proj= ect stepping ID, assigned by vendor 0x17, 3:1, eax, 31:0, vendor_brand_a , Vendor B= rand ID string, bytes subleaf_nr * (0 -> 3) @@ -503,18 +503,18 @@ # Leaf 18H # Intel determenestic address translation (TLB) parameters =20 - 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Max cpui= d 0x18 subleaf + 0x18, 31:0, eax, 31:0, tlb_max_subleaf , Maximum = leaf 0x18 subleaf 0x18, 31:0, ebx, 0, tlb_4k_page , TLB 4KB-= page entries supported 0x18, 31:0, ebx, 1, tlb_2m_page , TLB 2MB-= page entries supported 0x18, 31:0, ebx, 2, tlb_4m_page , TLB 4MB-= page entries supported 0x18, 31:0, ebx, 3, tlb_1g_page , TLB 1GB-= page entries supported - 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/So= ft) partitioning between logical CPUs sharing this struct + 0x18, 31:0, ebx, 10:8, hard_partitioning , (Hard/So= ft) partitioning between logical CPUs sharing this structure 0x18, 31:0, ebx, 31:16, n_way_associative , Ways of = associativity 0x18, 31:0, ecx, 31:0, n_sets , Number o= f sets 0x18, 31:0, edx, 4:0, tlb_type , Translat= ion cache type (TLB type) 0x18, 31:0, edx, 7:5, tlb_cache_level , Translat= ion cache level (1-based) 0x18, 31:0, edx, 8, is_fully_associative , Fully-as= sociative structure - 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max num = of addressible IDs for logical CPUs sharing this TLB - 1 + 0x18, 31:0, edx, 25:14, tlb_max_addressible_ids, Max numb= er of addressable IDs for logical CPUs sharing this TLB - 1 =20 # Leaf 19H # Intel Key Locker enumeration @@ -577,7 +577,7 @@ # Intel AMX, TMUL (Tile-matrix MULtiply) accelerator unit enumeration =20 0x1e, 0, ebx, 7:0, tmul_maxk , TMUL uni= t maximum height, K (rows or columns) - 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL uni= t maxiumum SIMD dimension, N (column bytes) + 0x1e, 0, ebx, 23:8, tmul_maxn , TMUL uni= t maximum SIMD dimension, N (column bytes) =20 # Leaf 1FH # Intel extended topology enumeration v2 @@ -634,7 +634,7 @@ # Leaf 80000000H # Maximum extended leaf number + AMD/Transmeta CPU vendor string =20 -0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended cpuid leaf supported +0x80000000, 0, eax, 31:0, max_ext_leaf , Maximum = extended CPUID leaf supported 0x80000000, 0, ebx, 31:0, cpu_vendorid_0 , Vendor I= D string bytes 0 - 3 0x80000000, 0, ecx, 31:0, cpu_vendorid_2 , Vendor I= D string bytes 8 - 11 0x80000000, 0, edx, 31:0, cpu_vendorid_1 , Vendor I= D string bytes 4 - 7 @@ -669,7 +669,7 @@ 0x80000001, 0, ecx, 17, tce , Translat= ion cache extension 0x80000001, 0, ecx, 19, nodeid_msr , NodeId M= SR (0xc001100c) 0x80000001, 0, ecx, 21, tbm , Trailing= bit manipulations -0x80000001, 0, ecx, 22, topoext , Topology= Extensions (cpuid leaf 0x8000001d) +0x80000001, 0, ecx, 22, topoext , Topology= Extensions (leaf 0x8000001d) 0x80000001, 0, ecx, 23, perfctr_core , Core per= formance counter extensions 0x80000001, 0, ecx, 24, perfctr_nb , NB/DF pe= rformance counter extensions 0x80000001, 0, ecx, 26, bpext , Data acc= ess breakpoint extension @@ -733,9 +733,9 @@ # Leaf 80000005H # AMD/Transmeta L1 cache and L1 TLB enumeration =20 -0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entires, 2M and 4M pages +0x80000005, 0, eax, 7:0, l1_itlb_2m_4m_nentries , L1 ITLB = #entries, 2M and 4M pages 0x80000005, 0, eax, 15:8, l1_itlb_2m_4m_assoc , L1 ITLB = associativity, 2M and 4M pages -0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB = #entires, 2M and 4M pages +0x80000005, 0, eax, 23:16, l1_dtlb_2m_4m_nentries , L1 DTLB = #entries, 2M and 4M pages 0x80000005, 0, eax, 31:24, l1_dtlb_2m_4m_assoc , L1 DTLB = associativity, 2M and 4M pages 0x80000005, 0, ebx, 7:0, l1_itlb_4k_nentries , L1 ITLB = #entries, 4K pages 0x80000005, 0, ebx, 15:8, l1_itlb_4k_assoc , L1 ITLB = associativity, 4K pages @@ -774,11 +774,11 @@ # CPU power management (mostly AMD) and AMD RAS enumeration =20 0x80000007, 0, ebx, 0, overflow_recov , MCA over= flow conditions not fatal -0x80000007, 0, ebx, 1, succor , Software= containment of UnCORRectable errors +0x80000007, 0, ebx, 1, succor , Software= containment of uncorrectable errors 0x80000007, 0, ebx, 2, hw_assert , Hardware= assert MSRs 0x80000007, 0, ebx, 3, smca , Scalable= MCA (MCAX MSRs) 0x80000007, 0, ecx, 31:0, cpu_pwr_sample_ratio , CPU powe= r sample time ratio -0x80000007, 0, edx, 0, digital_temp , Digital = temprature sensor +0x80000007, 0, edx, 0, digital_temp , Digital = temperature sensor 0x80000007, 0, edx, 1, powernow_freq_id , PowerNOW= ! frequency scaling 0x80000007, 0, edx, 2, powernow_volt_id , PowerNOW= ! voltage scaling 0x80000007, 0, edx, 3, thermal_trip , THERMTRI= P (Thermal Trip) @@ -821,7 +821,7 @@ 0x80000008, 0, ebx, 23, amd_ppin , Protecte= d Processor Inventory Number 0x80000008, 0, ebx, 24, amd_ssbd , Speculat= ive Store Bypass Disable 0x80000008, 0, ebx, 25, virt_ssbd , virtuali= zed SSBD (Speculative Store Bypass Disable) -0x80000008, 0, ebx, 26, amd_ssb_no , SSBD not= needed (fixed in HW) +0x80000008, 0, ebx, 26, amd_ssb_no , SSBD is = not needed (fixed in hardware) 0x80000008, 0, ebx, 27, cppc , Collabor= ative Processor Performance Control 0x80000008, 0, ebx, 28, amd_psfd , Predicti= ve Store Forward Disable 0x80000008, 0, ebx, 29, btc_no , CPU not = affected by Branch Type Confusion @@ -849,7 +849,7 @@ 0x8000000a, 0, edx, 10, pausefilter , Pause in= tercept filter 0x8000000a, 0, edx, 12, pfthreshold , Pause fi= lter threshold 0x8000000a, 0, edx, 13, avic , Advanced= virtual interrupt controller -0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual = VMSAVE/VMLOAD (nested virt) +0x8000000a, 0, edx, 15, v_vmsave_vmload , Virtual = VMSAVE/VMLOAD (nested virtualization) 0x8000000a, 0, edx, 16, vgif , Virtuali= ze the Global Interrupt Flag 0x8000000a, 0, edx, 17, gmet , Guest mo= de execution trap 0x8000000a, 0, edx, 18, x2avic , Virtual = x2APIC @@ -861,7 +861,7 @@ 0x8000000a, 0, edx, 25, vnmi , NMI virt= ualization 0x8000000a, 0, edx, 26, ibs_virt , IBS Virt= ualization 0x8000000a, 0, edx, 27, ext_lvt_off_chg , Extended= LVT offset fault change -0x8000000a, 0, edx, 28, svme_addr_chk , Guest SV= ME addr check +0x8000000a, 0, edx, 28, svme_addr_chk , Guest SV= ME address check =20 # Leaf 80000019H # AMD TLB 1G-pages enumeration @@ -902,20 +902,20 @@ # AMD LWP (Lightweight Profiling) =20 0x8000001c, 0, eax, 0, os_lwp_avail , LWP is a= vailable to application programs (supported by OS) -0x8000001c, 0, eax, 1, os_lpwval , LWPVAL i= nstruction (EventId=3D1) is supported by OS -0x8000001c, 0, eax, 2, os_lwp_ire , Instruct= ions Retired Event (EventId=3D2) is supported by OS -0x8000001c, 0, eax, 3, os_lwp_bre , Branch R= etired Event (EventId=3D3) is supported by OS -0x8000001c, 0, eax, 4, os_lwp_dme , DCache M= iss Event (EventId=3D4) is supported by OS -0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Cloc= ks Not Halted event (EventId=3D5) is supported by OS -0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refe= rence clocks Not Halted event (EventId=3D6) is supported by OS +0x8000001c, 0, eax, 1, os_lpwval , LWPVAL i= nstruction is supported by OS +0x8000001c, 0, eax, 2, os_lwp_ire , Instruct= ions Retired Event is supported by OS +0x8000001c, 0, eax, 3, os_lwp_bre , Branch R= etired Event is supported by OS +0x8000001c, 0, eax, 4, os_lwp_dme , Dcache M= iss Event is supported by OS +0x8000001c, 0, eax, 5, os_lwp_cnh , CPU Cloc= ks Not Halted event is supported by OS +0x8000001c, 0, eax, 6, os_lwp_rnh , CPU Refe= rence clocks Not Halted event is supported by OS 0x8000001c, 0, eax, 29, os_lwp_cont , LWP samp= ling in continuous mode is supported by OS 0x8000001c, 0, eax, 30, os_lwp_ptsc , Performa= nce Time Stamp Counter in event records is supported by OS 0x8000001c, 0, eax, 31, os_lwp_int , Interrup= t on threshold overflow is supported by OS 0x8000001c, 0, ebx, 7:0, lwp_lwpcb_sz , LWP Cont= rol Block size, in quadwords 0x8000001c, 0, ebx, 15:8, lwp_event_sz , LWP even= t record size, in bytes -0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max = supported EventId value (EventID 255 not included) +0x8000001c, 0, ebx, 23:16, lwp_max_events , LWP max = supported EventID value (EventID 255 not included) 0x8000001c, 0, ebx, 31:24, lwp_event_offset , LWP even= ts area offset in the LWP Control Block -0x8000001c, 0, ecx, 4:0, lwp_latency_max , Num of b= its in cache latency counters (10 to 31) +0x8000001c, 0, ecx, 4:0, lwp_latency_max , Number o= f bits in cache latency counters (10 to 31) 0x8000001c, 0, ecx, 5, lwp_data_adddr , Cache mi= ss events report the data address of the reference 0x8000001c, 0, ecx, 8:6, lwp_latency_rnd , Amount b= y which cache latency is rounded 0x8000001c, 0, ecx, 15:9, lwp_version , LWP impl= ementation version @@ -924,16 +924,16 @@ 0x8000001c, 0, ecx, 29, lwp_ip_filtering , IP filte= ring (IPI, IPF, BaseIP, and LimitIP @ LWPCP) supported 0x8000001c, 0, ecx, 30, lwp_cache_levels , Cache-re= lated events can be filtered by cache level 0x8000001c, 0, ecx, 31, lwp_cache_latency , Cache-re= lated events can be filtered by latency -0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is a= vailable in Hardware -0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL i= nstruction (EventId=3D1) is available in HW -0x8000001c, 0, edx, 2, hw_lwp_ire , Instruct= ions Retired Event (EventId=3D2) is available in HW -0x8000001c, 0, edx, 3, hw_lwp_bre , Branch R= etired Event (EventId=3D3) is available in HW -0x8000001c, 0, edx, 4, hw_lwp_dme , DCache M= iss Event (EventId=3D4) is available in HW -0x8000001c, 0, edx, 5, hw_lwp_cnh , CPU Cloc= ks Not Halted event (EventId=3D5) is available in HW -0x8000001c, 0, edx, 6, hw_lwp_rnh , CPU Refe= rence clocks Not Halted event (EventId=3D6) is available in HW -0x8000001c, 0, edx, 29, hw_lwp_cont , LWP samp= ling in continuous mode is available in HW -0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performa= nce Time Stamp Counter in event records is available in HW -0x8000001c, 0, edx, 31, hw_lwp_int , Interrup= t on threshold overflow is available in HW +0x8000001c, 0, edx, 0, hw_lwp_avail , LWP is a= vailable in hardware +0x8000001c, 0, edx, 1, hw_lpwval , LWPVAL i= nstruction is available in hardware +0x8000001c, 0, edx, 2, hw_lwp_ire , Instruct= ions Retired Event is available in hardware +0x8000001c, 0, edx, 3, hw_lwp_bre , Branch R= etired Event is available in hardware +0x8000001c, 0, edx, 4, hw_lwp_dme , Dcache M= iss Event is available in hardware +0x8000001c, 0, edx, 5, hw_lwp_cnh , Clocks N= ot Halted event is available in hardware +0x8000001c, 0, edx, 6, hw_lwp_rnh , Referenc= e clocks Not Halted event is available in hardware +0x8000001c, 0, edx, 29, hw_lwp_cont , LWP samp= ling in continuous mode is available in hardware +0x8000001c, 0, edx, 30, hw_lwp_ptsc , Performa= nce Time Stamp Counter in event records is available in hardware +0x8000001c, 0, edx, 31, hw_lwp_int , Interrup= t on threshold overflow is available in hardware =20 # Leaf 8000001DH # AMD deterministic cache parameters @@ -969,10 +969,10 @@ 0x8000001f, 0, eax, 4, sev_nested_paging , SEV secu= re nested paging supported 0x8000001f, 0, eax, 5, vm_permission_levels , VMPL sup= ported 0x8000001f, 0, eax, 6, rpmquery , RPMQUERY= instruction supported -0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadwo stack supported +0x8000001f, 0, eax, 7, vmpl_sss , VMPL sup= ervisor shadow stack supported 0x8000001f, 0, eax, 8, secure_tsc , Secure T= SC supported 0x8000001f, 0, eax, 9, v_tsc_aux , Hardware= virtualizes TSC_AUX -0x8000001f, 0, eax, 10, sme_coherent , HW enfor= ces cache coherency across encryption domains +0x8000001f, 0, eax, 10, sme_coherent , Cache co= herency is enforced across encryption domains 0x8000001f, 0, eax, 11, req_64bit_hypervisor , SEV gues= t mandates 64-bit hypervisor 0x8000001f, 0, eax, 12, restricted_injection , Restrict= ed Injection supported 0x8000001f, 0, eax, 13, alternate_injection , Alternat= e Injection supported @@ -984,13 +984,13 @@ 0x8000001f, 0, eax, 19, virt_ibs , IBS stat= e virtualization is supported for SEV-ES guests 0x8000001f, 0, eax, 24, vmsa_reg_protection , VMSA reg= ister protection is supported 0x8000001f, 0, eax, 25, smt_protection , SMT prot= ection is supported -0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR (0xc001f000h) is supported +0x8000001f, 0, eax, 28, svsm_page_msr , SVSM com= munication page MSR (0xc001f000) is supported 0x8000001f, 0, eax, 29, nested_virt_snp_msr , VIRT_RMP= UPDATE/VIRT_PSMASH MSRs are supported 0x8000001f, 0, ebx, 5:0, pte_cbit_pos , PTE bit = number used to enable memory encryption 0x8000001f, 0, ebx, 11:6, phys_addr_reduction_nbits, Reduct= ion of phys address space when encryption is enabled, in bits 0x8000001f, 0, ebx, 15:12, vmpl_count , Number o= f VM permission levels (VMPL) supported 0x8000001f, 0, ecx, 31:0, enc_guests_max , Max supp= orted number of simultaneous encrypted guests -0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Mininum = ASID for SEV-enabled SEV-ES-disabled guest +0x8000001f, 0, edx, 31:0, min_sev_asid_no_sev_es , Minimum = ASID for SEV-enabled SEV-ES-disabled guest =20 # Leaf 80000020H # AMD Platform QoS extended feature IDs @@ -999,6 +999,8 @@ 0x80000020, 0, ebx, 2, smba , Slow Mem= ory Bandwidth Allocation support 0x80000020, 0, ebx, 3, bmec , Bandwidt= h Monitoring Event Configuration support 0x80000020, 0, ebx, 4, l3rr , L3 Range= Reservation support +0x80000020, 0, ebx, 5, abmc , Assignab= le Bandwidth Monitoring Counters +0x80000020, 0, ebx, 6, sdciae , Smart Da= ta Cache Injection (SDCI) Allocation Enforcement 0x80000020, 1, eax, 31:0, mba_limit_len , MBA enfo= rcement limit size 0x80000020, 1, edx, 31:0, mba_cos_max , MBA max = Class of Service number (zero-based) 0x80000020, 2, eax, 31:0, smba_limit_len , SMBA enf= orcement limit size @@ -1023,12 +1025,21 @@ 0x80000021, 0, eax, 7, upper_addr_ignore , EFER MSR= Upper Address Ignore Enable bit supported 0x80000021, 0, eax, 8, autoibrs , EFER MSR= Automatic IBRS enable bit supported 0x80000021, 0, eax, 9, no_smm_ctl_msr , SMM_CTL = MSR (0xc0010116) is not present -0x80000021, 0, eax, 10, fsrs_supported , Fast Sho= rt Rep Stosb (FSRS) is supported -0x80000021, 0, eax, 11, fsrc_supported , Fast Sho= rt Repe Cmpsb (FSRC) is supported +0x80000021, 0, eax, 10, fsrs_supported , Fast Sho= rt Rep STOSB (FSRS) is supported +0x80000021, 0, eax, 11, fsrc_supported , Fast Sho= rt Rep CMPSB (FSRC) is supported 0x80000021, 0, eax, 13, prefetch_ctl_msr , Prefetch= control MSR is supported +0x80000021, 0, eax, 16, opcode_reclaim , Reserves= opcode space 0x80000021, 0, eax, 17, user_cpuid_disable , #GP when= executing CPUID at CPL > 0 is supported 0x80000021, 0, eax, 18, epsf_supported , Enhanced= Predictive Store Forwarding (EPSF) is supported -0x80000021, 0, ebx, 11:0, microcode_patch_size , Size of = microcode patch, in 16-byte units +0x80000021, 0, eax, 22, wl_feedback , Workload= -based heuristic feedback to OS +0x80000021, 0, eax, 24, eraps_support , Enhanced= Return Address Predictor Security +0x80000021, 0, eax, 27, sbpb , Support = for the Selective Branch Predictor Barrier +0x80000021, 0, eax, 28, ibpb_brtype , Branch p= redictions flushed from CPU branch predictor +0x80000021, 0, eax, 29, srso_no , CPU is n= ot subject to the SRSO vulnerability +0x80000021, 0, eax, 30, srso_uk_no , CPU is n= ot vulnerable to SRSO at user-kernel boundary +0x80000021, 0, eax, 31, srso_msr_fix , Software= may use MSR BP_CFG[BpSpecReduce] to mitigate SRSO +0x80000021, 0, ebx, 15:0, microcode_patch_size , Size of = microcode patch, in 16-byte units +0x80000021, 0, ebx, 23:16, rap_size , Return A= ddress Predictor size =20 # Leaf 80000022H # AMD Performance Monitoring v2 enumeration @@ -1036,7 +1047,7 @@ 0x80000022, 0, eax, 0, perfmon_v2 , Performa= nce monitoring v2 supported 0x80000022, 0, eax, 1, lbr_v2 , Last Bra= nch Record v2 extensions (LBR Stack) 0x80000022, 0, eax, 2, lbr_pmc_freeze , Freezing= core performance counters / LBR Stack supported -0x80000022, 0, ebx, 3:0, n_pmc_core , Number o= f core perfomance counters +0x80000022, 0, ebx, 3:0, n_pmc_core , Number o= f core performance counters 0x80000022, 0, ebx, 9:4, lbr_v2_stack_size , Number o= f available LBR stack entries 0x80000022, 0, ebx, 15:10, n_pmc_northbridge , Number o= f available northbridge (data fabric) performance counters 0x80000022, 0, ebx, 21:16, n_pmc_umc , Number o= f available UMC performance counters @@ -1046,7 +1057,7 @@ # AMD Secure Multi-key Encryption enumeration =20 0x80000023, 0, eax, 0, mem_hmk_mode , MEM-HMK = encryption mode is supported -0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK = mode: total num of available encryption keys +0x80000023, 0, ebx, 15:0, mem_hmk_avail_keys , MEM-HMK = mode: total number of available encryption keys =20 # Leaf 80000026H # AMD extended topology enumeration v2 @@ -1134,7 +1145,7 @@ =20 0x80860007, 0, eax, 31:0, cpu_cur_mhz , Current = CPU frequency, in MHz 0x80860007, 0, ebx, 31:0, cpu_cur_voltage , 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Peter Anvin" , x86@kernel.org, John Ogness , x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 12/12] MAINTAINERS: Include kcpuid under X86 CPUID DATABASE Date: Thu, 6 Mar 2025 21:50:00 +0100 Message-ID: <20250306205000.227399-13-darwi@linutronix.de> In-Reply-To: <20250306205000.227399-1-darwi@linutronix.de> References: <20250306205000.227399-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" kcpuid's CSV file is covered by the "x86 CPUID database" MAINTAINERS entry. Recent patches have shown that changes to this CSV file may require updates to the kcpuid code. Include the whole of kcpuid under the same entry where its CSV file resides. This also ensures that myself and the x86-cpuid mailing list are CCed on all future kcpuid patches. Signed-off-by: Ahmed S. Darwish --- MAINTAINERS | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/MAINTAINERS b/MAINTAINERS index 8e0736dc2ee0..d52702451b82 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -25695,7 +25695,7 @@ R: Ahmed S. Darwish L: x86-cpuid@lists.linux.dev S: Maintained W: https://x86-cpuid.org -F: tools/arch/x86/kcpuid/cpuid.csv +F: tools/arch/x86/kcpuid/ =20 X86 ENTRY CODE M: Andy Lutomirski --=20 2.48.1