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Wed, 05 Mar 2025 23:54:48 -0800 (PST) From: Stanley Chu X-Google-Original-From: Stanley Chu To: frank.li@nxp.com, miquel.raynal@bootlin.com, alexandre.belloni@bootlin.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-i3c@lists.infradead.org Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, tomer.maimon@nuvoton.com, kwliu@nuvoton.com, yschu@nuvoton.com Subject: [PATCH v7 4/5] i3c: master: svc: Fix npcm845 invalid slvstart event Date: Thu, 6 Mar 2025 15:54:28 +0800 Message-Id: <20250306075429.2265183-5-yschu@nuvoton.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250306075429.2265183-1-yschu@nuvoton.com> References: <20250306075429.2265183-1-yschu@nuvoton.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stanley Chu I3C HW may generate an invalid SlvStart event when emitting a STOP. If it is a true SlvStart, the MSTATUS state is SLVREQ. Check the MSTATUS state to ignore the false event. Reviewed-by: Frank Li Signed-off-by: Stanley Chu --- drivers/i3c/master/svc-i3c-master.c | 15 ++++++++++++++- 1 file changed, 14 insertions(+), 1 deletion(-) diff --git a/drivers/i3c/master/svc-i3c-master.c b/drivers/i3c/master/svc-i= 3c-master.c index cba89a685e13..1cab5b8594de 100644 --- a/drivers/i3c/master/svc-i3c-master.c +++ b/drivers/i3c/master/svc-i3c-master.c @@ -58,6 +58,7 @@ #define SVC_I3C_MSTATUS 0x088 #define SVC_I3C_MSTATUS_STATE(x) FIELD_GET(GENMASK(2, 0), (x)) #define SVC_I3C_MSTATUS_STATE_DAA(x) (SVC_I3C_MSTATUS_STATE(x) =3D=3D 5) +#define SVC_I3C_MSTATUS_STATE_SLVREQ(x) (SVC_I3C_MSTATUS_STATE(x) =3D=3D= 1) #define SVC_I3C_MSTATUS_STATE_IDLE(x) (SVC_I3C_MSTATUS_STATE(x) =3D=3D 0) #define SVC_I3C_MSTATUS_BETWEEN(x) FIELD_GET(BIT(4), (x)) #define SVC_I3C_MSTATUS_NACKED(x) FIELD_GET(BIT(5), (x)) @@ -143,6 +144,12 @@ * Fill the FIFO in advance to prevent FIFO from becoming empty. */ #define SVC_I3C_QUIRK_FIFO_EMPTY BIT(0) +/* + * SVC_I3C_QUIRK_FLASE_SLVSTART: + * I3C HW may generate an invalid SlvStart event when emitting a STOP. + * If it is a true SlvStart, the MSTATUS state is SLVREQ. + */ +#define SVC_I3C_QUIRK_FALSE_SLVSTART BIT(1) =20 struct svc_i3c_cmd { u8 addr; @@ -586,6 +593,11 @@ static irqreturn_t svc_i3c_master_irq_handler(int irq,= void *dev_id) /* Clear the interrupt status */ writel(SVC_I3C_MINT_SLVSTART, master->regs + SVC_I3C_MSTATUS); =20 + /* Ignore the false event */ + if (svc_has_quirk(master, SVC_I3C_QUIRK_FALSE_SLVSTART) && + !SVC_I3C_MSTATUS_STATE_SLVREQ(active)) + return IRQ_HANDLED; + svc_i3c_master_disable_interrupts(master); =20 /* Handle the interrupt in a non atomic context */ @@ -2018,7 +2030,8 @@ static const struct dev_pm_ops svc_i3c_pm_ops =3D { }; =20 static const struct svc_i3c_drvdata npcm845_drvdata =3D { - .quirks =3D SVC_I3C_QUIRK_FIFO_EMPTY, + .quirks =3D SVC_I3C_QUIRK_FIFO_EMPTY | + SVC_I3C_QUIRK_FALSE_SLVSTART, }; =20 static const struct svc_i3c_drvdata svc_default_drvdata =3D {}; --=20 2.34.1