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Thu, 06 Mar 2025 12:43:05 -0800 (PST) From: Peter Griffin Date: Thu, 06 Mar 2025 20:42:36 +0000 Subject: [PATCH v3 2/4] pinctrl: samsung: add dedicated SoC eint suspend/resume callbacks Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250306-pinctrl-fltcon-suspend-v3-2-f9ab4ff6a24e@linaro.org> References: <20250306-pinctrl-fltcon-suspend-v3-0-f9ab4ff6a24e@linaro.org> In-Reply-To: <20250306-pinctrl-fltcon-suspend-v3-0-f9ab4ff6a24e@linaro.org> To: Krzysztof Kozlowski , Sylwester Nawrocki , Alim Akhtar , Linus Walleij Cc: linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, andre.draszik@linaro.org, tudor.ambarus@linaro.org, willmcvicker@google.com, semen.protsenko@linaro.org, kernel-team@android.com, jaewon02.kim@samsung.com, Peter Griffin X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=0EFC8E6F5578750D56B549FCCEE8B8D6023472BA gs101 needs it's own suspend/resume callbacks to use the newly added eint_fltcon_offset for saving & restoring fltcon0 & fltcon1 registers. It also differs to previous SoCs in that fltcon1 register doesn't always exist for each bank. exynosautov920 also has dedicated logic for using eint_con_offset and eint_mask_offset for saving & restoring it's registers. Refactor the existing platform specific suspend/resume callback so that each SoC variant has their own callback containing the SoC specific logic. Additionally we now call drvdata->suspend() & drvdata->resume() from within the loop that iterates the banks in samsung_pinctrl_suspend() and samsung_pinctrl_resume(). This simplifies the logic, and allows us to remove the clk_enable() and clk_disable() from the callbacks. Signed-off-by: Peter Griffin Reviewed-by: Andr=C3=A9 Draszik --- Changes since v2: * Remove useless init (Andre) * make it clear set_wakeup is conditional on bank->eint_type (Andre) Changes since v1: * Split code refactor & gs101 parts into separate patches (Andre) --- drivers/pinctrl/samsung/pinctrl-exynos-arm64.c | 28 ++-- drivers/pinctrl/samsung/pinctrl-exynos.c | 201 ++++++++++-----------= ---- drivers/pinctrl/samsung/pinctrl-exynos.h | 6 +- drivers/pinctrl/samsung/pinctrl-samsung.c | 11 +- drivers/pinctrl/samsung/pinctrl-samsung.h | 8 +- 5 files changed, 109 insertions(+), 145 deletions(-) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c b/drivers/pinct= rl/samsung/pinctrl-exynos-arm64.c index e28fe81776466b693417c66bb15752d609b79eb1..57c98d2451b54b00d50e0e948e2= 72ed53d386c34 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos-arm64.c @@ -1112,8 +1112,8 @@ static const struct samsung_pin_ctrl exynosautov920_p= in_ctrl[] =3D { .pin_banks =3D exynosautov920_pin_banks0, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks0), .eint_wkup_init =3D exynos_eint_wkup_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, .retention_data =3D &exynosautov920_retention_data, }, { /* pin-controller instance 1 AUD data */ @@ -1124,43 +1124,43 @@ static const struct samsung_pin_ctrl exynosautov920= _pin_ctrl[] =3D { .pin_banks =3D exynosautov920_pin_banks2, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks2), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 3 HSI1 data */ .pin_banks =3D exynosautov920_pin_banks3, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks3), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 4 HSI2 data */ .pin_banks =3D exynosautov920_pin_banks4, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks4), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 5 HSI2UFS data */ .pin_banks =3D exynosautov920_pin_banks5, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks5), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 6 PERIC0 data */ .pin_banks =3D exynosautov920_pin_banks6, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks6), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, { /* pin-controller instance 7 PERIC1 data */ .pin_banks =3D exynosautov920_pin_banks7, .nr_banks =3D ARRAY_SIZE(exynosautov920_pin_banks7), .eint_gpio_init =3D exynos_eint_gpio_init, - .suspend =3D exynos_pinctrl_suspend, - .resume =3D exynos_pinctrl_resume, + .suspend =3D exynosautov920_pinctrl_suspend, + .resume =3D exynosautov920_pinctrl_resume, }, }; =20 diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.c b/drivers/pinctrl/sam= sung/pinctrl-exynos.c index ac6dc22b37c98ed5b7fca3335764f19abb2f71cc..f10ff09c1af01c11ff9229aaef7= 7df32eb057b7b 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.c +++ b/drivers/pinctrl/samsung/pinctrl-exynos.c @@ -761,153 +761,114 @@ __init int exynos_eint_wkup_init(struct samsung_pin= ctrl_drv_data *d) return 0; } =20 -static void exynos_pinctrl_suspend_bank( - struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) +static void exynos_set_wakeup(struct samsung_pin_bank *bank) { - struct exynos_eint_gpio_save *save =3D bank->soc_priv; - const void __iomem *regs =3D bank->eint_base; + struct exynos_irq_chip *irq_chip; =20 - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for saving state\n"); - return; + if (bank->irq_chip) { + irq_chip =3D bank->irq_chip; + irq_chip->set_eint_wakeup_mask(bank->drvdata, irq_chip); } - - save->eint_con =3D readl(regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset); - save->eint_fltcon0 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset); - save->eint_fltcon1 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4); - save->eint_mask =3D readl(regs + bank->irq_chip->eint_mask - + bank->eint_offset); - - clk_disable(bank->drvdata->pclk); - - pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); - pr_debug("%s: save fltcon0 %#010x\n", bank->name, save->eint_fltcon0); - pr_debug("%s: save fltcon1 %#010x\n", bank->name, save->eint_fltcon1); - pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); } =20 -static void exynosauto_pinctrl_suspend_bank(struct samsung_pinctrl_drv_dat= a *drvdata, - struct samsung_pin_bank *bank) +void exynos_pinctrl_suspend(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; const void __iomem *regs =3D bank->eint_base; =20 - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for saving state\n"); - return; - } - - save->eint_con =3D readl(regs + bank->pctl_offset + bank->eint_con_offset= ); - save->eint_mask =3D readl(regs + bank->pctl_offset + bank->eint_mask_offs= et); - - clk_disable(bank->drvdata->pclk); - - pr_debug("%s: save con %#010x\n", bank->name, save->eint_con); - pr_debug("%s: save mask %#010x\n", bank->name, save->eint_mask); + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + save->eint_con =3D readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + save->eint_fltcon0 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + save->eint_fltcon1 =3D readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + save->eint_mask =3D readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset); + + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save fltcon0 %#010x\n", + bank->name, save->eint_fltcon0); + pr_debug("%s: save fltcon1 %#010x\n", + bank->name, save->eint_fltcon1); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) + exynos_set_wakeup(bank); } =20 -void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata) +void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank) { - struct samsung_pin_bank *bank =3D drvdata->pin_banks; - struct exynos_irq_chip *irq_chip =3D NULL; - int i; + struct exynos_eint_gpio_save *save =3D bank->soc_priv; + const void __iomem *regs =3D bank->eint_base; =20 - for (i =3D 0; i < drvdata->nr_banks; ++i, ++bank) { - if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { - if (bank->eint_con_offset) - exynosauto_pinctrl_suspend_bank(drvdata, bank); - else - exynos_pinctrl_suspend_bank(drvdata, bank); - } - else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) { - if (!irq_chip) { - irq_chip =3D bank->irq_chip; - irq_chip->set_eint_wakeup_mask(drvdata, - irq_chip); - } - } - } + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + save->eint_con =3D readl(regs + bank->pctl_offset + + bank->eint_con_offset); + save->eint_mask =3D readl(regs + bank->pctl_offset + + bank->eint_mask_offset); + pr_debug("%s: save con %#010x\n", + bank->name, save->eint_con); + pr_debug("%s: save mask %#010x\n", + bank->name, save->eint_mask); + } else if (bank->eint_type =3D=3D EINT_TYPE_WKUP) + exynos_set_wakeup(bank); } =20 -static void exynos_pinctrl_resume_bank( - struct samsung_pinctrl_drv_data *drvdata, - struct samsung_pin_bank *bank) +void exynos_pinctrl_resume(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; void __iomem *regs =3D bank->eint_base; =20 - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for restoring state\n"); - return; + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset), save->eint_con); + pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset), save->eint_fltcon0); + pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, + readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4), + save->eint_fltcon1); + pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, + readl(regs + bank->irq_chip->eint_mask + + bank->eint_offset), save->eint_mask); + + writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET + + bank->eint_offset); + writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset); + writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET + + 2 * bank->eint_offset + 4); + writel(save->eint_mask, regs + bank->irq_chip->eint_mask + + bank->eint_offset); } - - pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset), save->eint_con); - pr_debug("%s: fltcon0 %#010x =3D> %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset), save->eint_fltcon0); - pr_debug("%s: fltcon1 %#010x =3D> %#010x\n", bank->name, - readl(regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4), save->eint_fltcon1); - pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, - readl(regs + bank->irq_chip->eint_mask - + bank->eint_offset), save->eint_mask); - - writel(save->eint_con, regs + EXYNOS_GPIO_ECON_OFFSET - + bank->eint_offset); - writel(save->eint_fltcon0, regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset); - writel(save->eint_fltcon1, regs + EXYNOS_GPIO_EFLTCON_OFFSET - + 2 * bank->eint_offset + 4); - writel(save->eint_mask, regs + bank->irq_chip->eint_mask - + bank->eint_offset); - - clk_disable(bank->drvdata->pclk); } =20 -static void exynosauto_pinctrl_resume_bank(struct samsung_pinctrl_drv_data= *drvdata, - struct samsung_pin_bank *bank) +void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank) { struct exynos_eint_gpio_save *save =3D bank->soc_priv; void __iomem *regs =3D bank->eint_base; =20 - if (clk_enable(bank->drvdata->pclk)) { - dev_err(bank->gpio_chip.parent, - "unable to enable clock for restoring state\n"); - return; + if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { + /* exynosautov920 has eint_con_offset for all but one bank */ + if (!bank->eint_con_offset) + exynos_pinctrl_resume(bank); + + pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, + readl(regs + bank->pctl_offset + bank->eint_con_offset), + save->eint_con); + pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, + readl(regs + bank->pctl_offset + + bank->eint_mask_offset), save->eint_mask); + + writel(save->eint_con, + regs + bank->pctl_offset + bank->eint_con_offset); + writel(save->eint_mask, + regs + bank->pctl_offset + bank->eint_mask_offset); } - - pr_debug("%s: con %#010x =3D> %#010x\n", bank->name, - readl(regs + bank->pctl_offset + bank->eint_con_offset), save->eint_con= ); - pr_debug("%s: mask %#010x =3D> %#010x\n", bank->name, - readl(regs + bank->pctl_offset + bank->eint_mask_offset), save->eint_ma= sk); - - writel(save->eint_con, regs + bank->pctl_offset + bank->eint_con_offset); - writel(save->eint_mask, regs + bank->pctl_offset + bank->eint_mask_offset= ); - - clk_disable(bank->drvdata->pclk); -} - -void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata) -{ - struct samsung_pin_bank *bank =3D drvdata->pin_banks; - int i; - - for (i =3D 0; i < drvdata->nr_banks; ++i, ++bank) - if (bank->eint_type =3D=3D EINT_TYPE_GPIO) { - if (bank->eint_con_offset) - exynosauto_pinctrl_resume_bank(drvdata, bank); - else - exynos_pinctrl_resume_bank(drvdata, bank); - } } =20 static void exynos_retention_enable(struct samsung_pinctrl_drv_data *drvda= ta) diff --git a/drivers/pinctrl/samsung/pinctrl-exynos.h b/drivers/pinctrl/sam= sung/pinctrl-exynos.h index 33df21d5c9d61e852834031570d4a0ac0e51f6a4..35c2bc4ea488bda600ebfbda149= 2f5f49dbd9849 100644 --- a/drivers/pinctrl/samsung/pinctrl-exynos.h +++ b/drivers/pinctrl/samsung/pinctrl-exynos.h @@ -221,8 +221,10 @@ struct exynos_muxed_weint_data { =20 int exynos_eint_gpio_init(struct samsung_pinctrl_drv_data *d); int exynos_eint_wkup_init(struct samsung_pinctrl_drv_data *d); -void exynos_pinctrl_suspend(struct samsung_pinctrl_drv_data *drvdata); -void exynos_pinctrl_resume(struct samsung_pinctrl_drv_data *drvdata); +void exynosautov920_pinctrl_resume(struct samsung_pin_bank *bank); +void exynosautov920_pinctrl_suspend(struct samsung_pin_bank *bank); +void exynos_pinctrl_suspend(struct samsung_pin_bank *bank); +void exynos_pinctrl_resume(struct samsung_pin_bank *bank); struct samsung_retention_ctrl * exynos_retention_init(struct samsung_pinctrl_drv_data *drvdata, const struct samsung_retention_data *data); diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.c b/drivers/pinctrl/sa= msung/pinctrl-samsung.c index 963060920301ec90affb2ee6d758d3d602ffb4a9..375634d8cc79d6533603e3eed56= 2452181e2ee25 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.c +++ b/drivers/pinctrl/samsung/pinctrl-samsung.c @@ -1349,6 +1349,9 @@ static int __maybe_unused samsung_pinctrl_suspend(str= uct device *dev) const u8 *widths =3D bank->type->fld_width; enum pincfg_type type; =20 + if (drvdata->suspend) + drvdata->suspend(bank); + /* Registers without a powerdown config aren't lost */ if (!widths[PINCFG_TYPE_CON_PDN]) continue; @@ -1373,8 +1376,6 @@ static int __maybe_unused samsung_pinctrl_suspend(str= uct device *dev) =20 clk_disable(drvdata->pclk); =20 - if (drvdata->suspend) - drvdata->suspend(drvdata); if (drvdata->retention_ctrl && drvdata->retention_ctrl->enable) drvdata->retention_ctrl->enable(drvdata); =20 @@ -1406,9 +1407,6 @@ static int __maybe_unused samsung_pinctrl_resume(stru= ct device *dev) return ret; } =20 - if (drvdata->resume) - drvdata->resume(drvdata); - for (i =3D 0; i < drvdata->nr_banks; i++) { struct samsung_pin_bank *bank =3D &drvdata->pin_banks[i]; void __iomem *reg =3D bank->pctl_base + bank->pctl_offset; @@ -1416,6 +1414,9 @@ static int __maybe_unused samsung_pinctrl_resume(stru= ct device *dev) const u8 *widths =3D bank->type->fld_width; enum pincfg_type type; =20 + if (drvdata->resume) + drvdata->resume(bank); + /* Registers without a powerdown config aren't lost */ if (!widths[PINCFG_TYPE_CON_PDN]) continue; diff --git a/drivers/pinctrl/samsung/pinctrl-samsung.h b/drivers/pinctrl/sa= msung/pinctrl-samsung.h index 371e4f02bbfb375964b7833beb9bbc098a51f4a3..e939e5bb0347458ae4a9014fd96= 57fc59c5c3994 100644 --- a/drivers/pinctrl/samsung/pinctrl-samsung.h +++ b/drivers/pinctrl/samsung/pinctrl-samsung.h @@ -285,8 +285,8 @@ struct samsung_pin_ctrl { int (*eint_gpio_init)(struct samsung_pinctrl_drv_data *); int (*eint_wkup_init)(struct samsung_pinctrl_drv_data *); void (*pud_value_init)(struct samsung_pinctrl_drv_data *drvdata); - void (*suspend)(struct samsung_pinctrl_drv_data *); - void (*resume)(struct samsung_pinctrl_drv_data *); + void (*suspend)(struct samsung_pin_bank *bank); + void (*resume)(struct samsung_pin_bank *bank); }; =20 /** @@ -335,8 +335,8 @@ struct samsung_pinctrl_drv_data { =20 struct samsung_retention_ctrl *retention_ctrl; =20 - void (*suspend)(struct samsung_pinctrl_drv_data *); - void (*resume)(struct samsung_pinctrl_drv_data *); + void (*suspend)(struct samsung_pin_bank *bank); + void (*resume)(struct samsung_pin_bank *bank); }; =20 /** --=20 2.49.0.rc0.332.g42c0ae87b1-goog