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[34.91.171.30]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e5c74a6af7sm708972a12.33.2025.03.06.02.14.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 06 Mar 2025 02:14:49 -0800 (PST) From: =?utf-8?q?Andr=C3=A9_Draszik?= Date: Thu, 06 Mar 2025 10:14:47 +0000 Subject: [PATCH 2/3] arm64: dts: exynos: gs101-pixel-common: add the MAX77759 PMIC Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250306-b4-max77759-mfd-dts-v1-2-9fe8b0eb8123@linaro.org> References: <20250306-b4-max77759-mfd-dts-v1-0-9fe8b0eb8123@linaro.org> In-Reply-To: <20250306-b4-max77759-mfd-dts-v1-0-9fe8b0eb8123@linaro.org> To: Catalin Marinas , Will Deacon , Peter Griffin , Tudor Ambarus , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Alim Akhtar Cc: Will McVicker , kernel-team@android.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-samsung-soc@vger.kernel.org, devicetree@vger.kernel.org, =?utf-8?q?Andr=C3=A9_Draszik?= X-Mailer: b4 0.14.2 Also add the subnodes for the GPIO expander and NVMEM, and define the NVMEM layout. The NVMEM layout is declared such that it matches downstream's open-coded configuration [1]. The pinctrl nodes are kept sorted by the 'samsung,pins' property rather than node name, as I think that makes it easier to look at and to add new nodes unambiguously in the future. Link: https://android.googlesource.com/kernel/google-modules/bms/+/96e729a8= 3817/max77759_maxq.c#67 [1] Signed-off-by: Andr=C3=A9 Draszik --- .../boot/dts/exynos/google/gs101-pixel-common.dtsi | 61 ++++++++++++++++++= ++++ 1 file changed, 61 insertions(+) diff --git a/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi b/ar= ch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi index b25230495c64dce60916b7cd5dcb9a7cce5d0e4e..f67fa1e84d994de4d40f29a2d43= 7ab6401ac133d 100644 --- a/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi +++ b/arch/arm64/boot/dts/exynos/google/gs101-pixel-common.dtsi @@ -188,6 +188,60 @@ usbc0_role_sw: endpoint { }; }; }; + + pmic@66 { + compatible =3D "maxim,max77759"; + reg =3D <0x66>; + + pinctrl-0 =3D <&if_pmic_int>; + pinctrl-names =3D "default"; + interrupts-extended =3D <&gpa8 3 IRQ_TYPE_LEVEL_LOW>; + + interrupt-controller; + #interrupt-cells =3D <2>; + + gpio { + compatible =3D "maxim,max77759-gpio"; + + gpio-controller; + #gpio-cells =3D <2>; + /* + * "Human-readable name [SIGNAL_LABEL]" where the + * latter comes from the schematic + */ + gpio-line-names =3D "OTG boost [OTG_BOOST_EN]", + "max20339 IRQ [MW_OVP_INT_L]"; + + interrupt-controller; + #interrupt-cells =3D <2>; + }; + + nvmem-0 { + compatible =3D "maxim,max77759-nvmem"; + + nvmem-layout { + compatible =3D "fixed-layout"; + #address-cells =3D <1>; + #size-cells =3D <1>; + + reboot-mode@0 { + reg =3D <0x0 0x4>; + }; + + boot-reason@4 { + reg =3D <0x4 0x4>; + }; + + shutdown-user-flag@8 { + reg =3D <0x8 0x1>; + }; + + rsoc@a { + reg =3D <0xa 0x2>; + }; + }; + }; + }; }; =20 &pinctrl_far_alive { @@ -211,6 +265,13 @@ typec_int: typec-int-pins { samsung,pin-pud =3D ; samsung,pin-drv =3D ; }; + + if_pmic_int: if-pmic-int-pins { + samsung,pins =3D "gpa8-3"; + samsung,pin-function =3D ; + samsung,pin-pud =3D ; + samsung,pin-drv =3D ; + }; }; =20 &pinctrl_gpio_alive { --=20 2.49.0.rc0.332.g42c0ae87b1-goog