From nobody Sun Feb 8 04:11:16 2026 Received: from out-186.mta1.migadu.com (out-186.mta1.migadu.com [95.215.58.186]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BCBD32566F3 for ; Wed, 5 Mar 2025 20:27:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=95.215.58.186 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741206424; cv=none; b=IcvRzyav2NIZvRg9Pcf7fAUZnmDvz8qkIvq13qZaAmvhGWSxOD5u23aqyaLWwG/fYRdmK+RWRvbQDyiScjJVoVRM/eR4F87Cqg15QrGaAh9dxcRgDtGNYyuJ36y8rJmFYmDTN3wFLkCOg9Rsxbr3SA4jaJahmZs6lkPYVEqx5kc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741206424; c=relaxed/simple; bh=82pQFF5TJWTGnuUtsQ9t/PIiYpetCGBPDoLe7JOXPO8=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=DucIfF0h/oqjO9AGpUIfS3j1svbRw8BMhXuwUkrfGLJ9J5IQUiF1I18UTNncY5pDRyD1SaDsUFiH3AYIDFm9lrdUDqt+4MwAm3RE9pK+HWOHxIDEQ0SR7YCw/6JNyaDtSjCFKSmFu7qAlN/xcU/pSlrn212J2MBD5nDAonrTodI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev; spf=pass smtp.mailfrom=linux.dev; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b=BBrLbbi5; arc=none smtp.client-ip=95.215.58.186 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.dev Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linux.dev Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=linux.dev header.i=@linux.dev header.b="BBrLbbi5" X-Report-Abuse: Please report any abuse attempt to abuse@migadu.com and include these headers. DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linux.dev; s=key1; t=1741206419; h=from:from:reply-to:subject:subject:date:date:message-id:message-id: to:to:cc:cc:mime-version:mime-version: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=+69dsXa194Lbj7OuVGODh/C+nXkT1DCOFxIShuli7hw=; b=BBrLbbi5SmryGjedtHNKZjPmGNHNieIuBF/e4ufYwqwbc13QlAWi9ygpumye6NRbjVycaQ rZe/1pO1JG7el8o+nDW0nq2sEU6hPXKdYo38vEOdX9u8zqtaDGAOLsP2wmrInX0lhqb8ha 2eehc4M5SRjonnP61pNgHWVH2gkJFdg= From: Oliver Upton To: kvmarm@lists.linux.dev Cc: Marc Zyngier , Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Janne Grunau , Oliver Upton Subject: [PATCH v3 02/14] drivers/perf: apple_m1: Support host/guest event filtering Date: Wed, 5 Mar 2025 12:26:29 -0800 Message-Id: <20250305202641.428114-3-oliver.upton@linux.dev> In-Reply-To: <20250305202641.428114-1-oliver.upton@linux.dev> References: <20250305202641.428114-1-oliver.upton@linux.dev> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Migadu-Flow: FLOW_OUT Content-Type: text/plain; charset="utf-8" The PMU appears to have a separate register for filtering 'guest' exception levels (i.e. EL1 and !ELIsInHost(EL0)) which has the same layout as PMCR1_EL1. Conveniently, there exists a VHE register alias (PMCR1_EL12) that can be used to configure it. Support guest events by programming the EL12 register with the intended guest kernel/userspace filters. Limit support for guest events to VHE (i.e. kernel running at EL2), as it avoids involving KVM to context switch PMU registers. VHE is the only supported mode on M* parts anyway, so this isn't an actual feature limitation. Tested-by: Janne Grunau Signed-off-by: Oliver Upton --- arch/arm64/include/asm/apple_m1_pmu.h | 1 + drivers/perf/apple_m1_cpu_pmu.c | 20 ++++++++++++++++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/arch/arm64/include/asm/apple_m1_pmu.h b/arch/arm64/include/asm= /apple_m1_pmu.h index 99483b19b99f..02e05d05851f 100644 --- a/arch/arm64/include/asm/apple_m1_pmu.h +++ b/arch/arm64/include/asm/apple_m1_pmu.h @@ -37,6 +37,7 @@ #define PMCR0_PMI_ENABLE_8_9 GENMASK(45, 44) =20 #define SYS_IMP_APL_PMCR1_EL1 sys_reg(3, 1, 15, 1, 0) +#define SYS_IMP_APL_PMCR1_EL12 sys_reg(3, 1, 15, 7, 2) #define PMCR1_COUNT_A64_EL0_0_7 GENMASK(15, 8) #define PMCR1_COUNT_A64_EL1_0_7 GENMASK(23, 16) #define PMCR1_COUNT_A64_EL0_8_9 GENMASK(41, 40) diff --git a/drivers/perf/apple_m1_cpu_pmu.c b/drivers/perf/apple_m1_cpu_pm= u.c index cea80afd1253..d6d4ff6da862 100644 --- a/drivers/perf/apple_m1_cpu_pmu.c +++ b/drivers/perf/apple_m1_cpu_pmu.c @@ -120,6 +120,8 @@ enum m1_pmu_events { */ M1_PMU_CFG_COUNT_USER =3D BIT(8), M1_PMU_CFG_COUNT_KERNEL =3D BIT(9), + M1_PMU_CFG_COUNT_HOST =3D BIT(10), + M1_PMU_CFG_COUNT_GUEST =3D BIT(11), }; =20 /* @@ -328,7 +330,7 @@ static void m1_pmu_disable_counter_interrupt(unsigned i= nt index) } =20 static void __m1_pmu_configure_event_filter(unsigned int index, bool user, - bool kernel) + bool kernel, bool host) { u64 clear, set, user_bit, kernel_bit; =20 @@ -356,7 +358,10 @@ static void __m1_pmu_configure_event_filter(unsigned i= nt index, bool user, else clear |=3D kernel_bit; =20 - sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL1, clear, set); + if (host) + sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL1, clear, set); + else if (is_kernel_in_hyp_mode()) + sysreg_clear_set_s(SYS_IMP_APL_PMCR1_EL12, clear, set); } =20 static void __m1_pmu_configure_eventsel(unsigned int index, u8 event) @@ -391,10 +396,13 @@ static void __m1_pmu_configure_eventsel(unsigned int = index, u8 event) static void m1_pmu_configure_counter(unsigned int index, unsigned long con= fig_base) { bool kernel =3D config_base & M1_PMU_CFG_COUNT_KERNEL; + bool guest =3D config_base & M1_PMU_CFG_COUNT_GUEST; + bool host =3D config_base & M1_PMU_CFG_COUNT_HOST; bool user =3D config_base & M1_PMU_CFG_COUNT_USER; u8 evt =3D config_base & M1_PMU_CFG_EVENT; =20 - __m1_pmu_configure_event_filter(index, user, kernel); + __m1_pmu_configure_event_filter(index, user && host, kernel && host, true= ); + __m1_pmu_configure_event_filter(index, user && guest, kernel && guest, fa= lse); __m1_pmu_configure_eventsel(index, evt); } =20 @@ -570,7 +578,7 @@ static int m1_pmu_set_event_filter(struct hw_perf_event= *event, { unsigned long config_base =3D 0; =20 - if (!attr->exclude_guest) { + if (!attr->exclude_guest && !is_kernel_in_hyp_mode()) { pr_debug("ARM performance counters do not support mode exclusion\n"); return -EOPNOTSUPP; } @@ -578,6 +586,10 @@ static int m1_pmu_set_event_filter(struct hw_perf_even= t *event, config_base |=3D M1_PMU_CFG_COUNT_KERNEL; if (!attr->exclude_user) config_base |=3D M1_PMU_CFG_COUNT_USER; + if (!attr->exclude_host) + config_base |=3D M1_PMU_CFG_COUNT_HOST; + if (!attr->exclude_guest) + config_base |=3D M1_PMU_CFG_COUNT_GUEST; =20 event->config_base =3D config_base; =20 --=20 2.39.5