From nobody Thu Dec 18 01:35:38 2025 Received: from metis.whiteo.stw.pengutronix.de (metis.whiteo.stw.pengutronix.de [185.203.201.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B1D324BC05 for ; Wed, 5 Mar 2025 13:14:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.203.201.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741180486; cv=none; b=AFr1fZb7iUC5jjPzp/q/xj4IQ0wnX1C7mx21Kl6nlSoHY4GJg5dai80hYy5saFJAdv7Bhnk3UXGmsMdRZUg3atrevOCGFDfjG6t2UyUQ/GgdAw6BYJHeKjCiv1MxS6KFevja2zZdjsi3znqr+faozXh7pGkuGWnnVQe7Z33aCnY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741180486; c=relaxed/simple; bh=BbTAWagfnSyWjzM+4l1VuDEtviOwLQ71Y89ec1iIv/I=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=VUH4gS1mg0h9z4aPAlT+VAMZGr1IKUpqlAROXY+Y0+JDAyJwTxp7N6vAurSpufmZv66o2b4TOLQ4jwQQj2U88wf9GIk5/eUGwcbP6zPolDNhdOlhdUZrmjBUrFbpgcI9KCaW5SwacKy74FugozI2xuCjTxTOFtlKm4wzn16L4cs= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de; spf=pass smtp.mailfrom=pengutronix.de; arc=none smtp.client-ip=185.203.201.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=pengutronix.de Received: from drehscheibe.grey.stw.pengutronix.de ([2a0a:edc0:0:c01:1d::a2]) by metis.whiteo.stw.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1tpoZw-0000xd-A1; Wed, 05 Mar 2025 14:14:28 +0100 Received: from dude04.red.stw.pengutronix.de ([2a0a:edc0:0:1101:1d::ac]) by drehscheibe.grey.stw.pengutronix.de with esmtps (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.96) (envelope-from ) id 1tpoZv-0049PA-1e; Wed, 05 Mar 2025 14:14:27 +0100 Received: from ore by dude04.red.stw.pengutronix.de with local (Exim 4.96) (envelope-from ) id 1tpoZv-006G5t-1O; Wed, 05 Mar 2025 14:14:27 +0100 From: Oleksij Rempel To: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Maxime Coquelin , Alexandre Torgue , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Woojung Huh , Andrew Lunn Cc: Oleksij Rempel , kernel@pengutronix.de, linux-kernel@vger.kernel.org, netdev@vger.kernel.org, devicetree@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com Subject: [PATCH v5 3/4] ARM: dts: stm32: Add pinmux groups for Plymovent AQM board Date: Wed, 5 Mar 2025 14:14:24 +0100 Message-Id: <20250305131425.1491769-4-o.rempel@pengutronix.de> X-Mailer: git-send-email 2.39.5 In-Reply-To: <20250305131425.1491769-1-o.rempel@pengutronix.de> References: <20250305131425.1491769-1-o.rempel@pengutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 2a0a:edc0:0:c01:1d::a2 X-SA-Exim-Mail-From: ore@pengutronix.de X-SA-Exim-Scanned: No (on metis.whiteo.stw.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-kernel@vger.kernel.org Content-Type: text/plain; charset="utf-8" Add pinmux groups required for the Plymovent AQM board. Signed-off-by: Oleksij Rempel --- arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi | 292 ++++++++++++++++++++ 1 file changed, 292 insertions(+) diff --git a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi b/arch/arm/boot/dt= s/st/stm32mp15-pinctrl.dtsi index 95fafc51a1c8..40605ea85ee1 100644 --- a/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi +++ b/arch/arm/boot/dts/st/stm32mp15-pinctrl.dtsi @@ -25,6 +25,13 @@ pins { }; }; =20 + /omit-if-no-ref/ + adc1_in10_pins_a: adc1-in10-0 { + pins { + pinmux =3D ; + }; + }; + /omit-if-no-ref/ adc12_ain_pins_a: adc12-ain-0 { pins { @@ -584,6 +591,43 @@ pins1 { }; }; =20 + /omit-if-no-ref/ + ethernet0_rmii_pins_d: rmii-3 { + pins1 { + pinmux =3D , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_RMII_REF_CLK */ + , /* ETH1_MDIO */ + ; /* ETH1_MDC */ + bias-disable; + drive-push-pull; + slew-rate =3D <2>; + }; + + pins2 { + pinmux =3D , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + ; /* ETH1_RMII_CRS_DV */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + ethernet0_rmii_sleep_pins_d: rmii-sleep-3 { + pins1 { + pinmux =3D , /* ETH1_RMII_TXD0 */ + , /* ETH1_RMII_TXD1 */ + , /* ETH1_RMII_TX_EN */ + , /* ETH1_MDIO */ + , /* ETH1_MDC */ + , /* ETH1_RMII_RXD0 */ + , /* ETH1_RMII_RXD1 */ + , /* ETH1_RMII_REF_CLK */ + ; /* ETH1_RMII_CRS_DV */ + }; + }; + /omit-if-no-ref/ fmc_pins_a: fmc-0 { pins1 { @@ -725,6 +769,25 @@ pins { }; }; =20 + /omit-if-no-ref/ + i2c1_pins_c: i2c1-2 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + bias-disable; + drive-open-drain; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + i2c1_sleep_pins_c: i2c1-sleep-2 { + pins { + pinmux =3D , /* I2C1_SCL */ + ; /* I2C1_SDA */ + }; + }; + /omit-if-no-ref/ i2c2_pins_a: i2c2-0 { pins { @@ -819,6 +882,27 @@ pins { }; }; =20 + /omit-if-no-ref/ + i2s1_pins_a: i2s1-0 { + pins { + pinmux =3D , /* I2S2_SDI */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + slew-rate =3D <0>; + drive-push-pull; + bias-disable; + }; + }; + + /omit-if-no-ref/ + i2s1_sleep_pins_a: i2s1-sleep-0 { + pins { + pinmux =3D , /* I2S2_SDI */ + , /* I2S2_WS */ + ; /* I2S2_CK */ + }; + }; + /omit-if-no-ref/ i2s2_pins_a: i2s2-0 { pins { @@ -1418,6 +1502,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + pwm1_pins_d: pwm1-3 { + pins { + pinmux =3D ; /* TIM5_CH1 */ + bias-pull-down; + drive-push-pull; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + pwm1_sleep_pins_d: pwm1-sleep-3 { + pins { + pinmux =3D ; + }; + }; + /omit-if-no-ref/ pwm2_pins_a: pwm2-0 { pins { @@ -2160,6 +2261,66 @@ pins3 { }; }; =20 + /omit-if-no-ref/ + sdmmc2_b4_pins_c: sdmmc2-b4-2 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_od_pins_c: sdmmc2-b4-od-2 { + pins1 { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + ; /* SDMMC2_D3 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux =3D ; /* SDMMC2_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux =3D ; /* SDMMC2_CMD */ + slew-rate =3D <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc2_b4_sleep_pins_c: sdmmc2-b4-sleep-2 { + pins { + pinmux =3D , /* SDMMC2_D0 */ + , /* SDMMC2_D1 */ + , /* SDMMC2_D2 */ + , /* SDMMC2_D3 */ + , /* SDMMC2_CK */ + ; /* SDMMC2_CMD */ + }; + }; + /omit-if-no-ref/ sdmmc2_d47_pins_a: sdmmc2-d47-0 { pins { @@ -2389,6 +2550,66 @@ pins { }; }; =20 + /omit-if-no-ref/ + sdmmc3_b4_pins_c: sdmmc3-b4-2 { + pins1 { + pinmux =3D , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + ; /* SDMMC3_CMD */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux =3D ; /* SDMMC3_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_od_pins_c: sdmmc3-b4-od-2 { + pins1 { + pinmux =3D , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + ; /* SDMMC3_D3 */ + slew-rate =3D <1>; + drive-push-pull; + bias-pull-up; + }; + + pins2 { + pinmux =3D ; /* SDMMC3_CK */ + slew-rate =3D <2>; + drive-push-pull; + bias-pull-up; + }; + + pins3 { + pinmux =3D ; /* SDMMC3_CMD */ + slew-rate =3D <1>; + drive-open-drain; + bias-pull-up; + }; + }; + + /omit-if-no-ref/ + sdmmc3_b4_sleep_pins_c: sdmmc3-b4-sleep-2 { + pins { + pinmux =3D , /* SDMMC3_D0 */ + , /* SDMMC3_D1 */ + , /* SDMMC3_D2 */ + , /* SDMMC3_D3 */ + , /* SDMMC3_CK */ + ; /* SDMMC3_CMD */ + }; + }; + /omit-if-no-ref/ spdifrx_pins_a: spdifrx-0 { pins { @@ -2600,6 +2821,41 @@ pins { }; }; =20 + /omit-if-no-ref/ + uart4_pins_e: uart4-4 { + pins1 { + pinmux =3D ; /* UART4_TX */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + + pins2 { + pinmux =3D ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_idle_pins_e: uart4-idle-4 { + pins1 { + pinmux =3D ; /* UART4_TX */ + }; + + pins2 { + pinmux =3D ; /* UART4_RX */ + bias-disable; + }; + }; + + /omit-if-no-ref/ + uart4_sleep_pins_e: uart4-sleep-4 { + pins { + pinmux =3D , /* UART4_TX */ + ; /* UART4_RX */ + }; + }; + /omit-if-no-ref/ uart5_pins_a: uart5-0 { pins1 { @@ -2677,6 +2933,23 @@ pins { }; }; =20 + /omit-if-no-ref/ + uart7_pins_d: uart7-3 { + pins1 { + pinmux =3D , /* UART7_TX */ + ; /* UART7_RTS */ + bias-disable; + drive-push-pull; + slew-rate =3D <0>; + }; + + pins2 { + pinmux =3D , /* UART7_RX */ + ; /* UART7_CTS */ + bias-disable; + }; + }; + /omit-if-no-ref/ uart8_pins_a: uart8-0 { pins1 { @@ -3118,6 +3391,25 @@ pins { }; }; =20 + /omit-if-no-ref/ + i2c6_pins_b: i2c6-1 { + pins { + pinmux =3D , /* I2C6_SCL */ + ; /* I2C6_SDA */ + bias-disable; + drive-open-drain; + slew-rate =3D <0>; + }; + }; + + /omit-if-no-ref/ + i2c6_sleep_pins_b: i2c6-sleep-1 { + pins { + pinmux =3D , /* I2C6_SCL */ + ; /* I2C6_SDA */ + }; + }; + /omit-if-no-ref/ spi1_pins_a: spi1-0 { pins1 { --=20 2.39.5