From nobody Mon Feb 9 02:55:14 2026 Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38F2E205E3F; Wed, 5 Mar 2025 09:54:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=91.207.212.93 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741168450; cv=none; b=eHPVY04pY5Er5mqU2sdBCw8ryKLjlIryufB4SAuIfCUJr06Sb+KHOnR7Rl7253rmx+u966PPYUh9GpNFI7qcQTvIuvni0IPXci5tGRkQeMOma9D7JxTaaSvyjmF/I0WuIw24W1wbACgdBUG5oqQhCgbHsLWU2EVVW4cNuIGcoME= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741168450; c=relaxed/simple; bh=jiB4/6NxcdPBW0bNdUhxcALfkbBi6+y7zZz9AUW5g3g=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cDGvBGvv17d+0xv6/Q0k+757swrFAb8zQJlEdH0Yt30C1scJedLWKOdt0ICha0O0PnGg5sYObUPGr3R7h1QRHQX0m/fTUn4t9A8fI4Trd/lSv8cTi5Q1GDmN4UIEZzfWtmD8mZ8EjS46r0eHmSPBM1NoCtquWSVugEyhUtF6nRM= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com; spf=pass smtp.mailfrom=foss.st.com; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b=QK/T7l83; arc=none smtp.client-ip=91.207.212.93 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=foss.st.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=foss.st.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=foss.st.com header.i=@foss.st.com header.b="QK/T7l83" Received: from pps.filterd (m0046661.ppops.net [127.0.0.1]) by mx07-00178001.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 5259B7xH015061; Wed, 5 Mar 2025 10:53:55 +0100 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=foss.st.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=selector1; bh= mhvTaZuKOviAMTNavLZtF4RTa6aSH1vLPVWO7cdfE/U=; b=QK/T7l83yacrRjoE pK3YolCaUm5PnjS4Ctex5g+hcMKrw8zFffYmw7Cnnhw4L9oTewyPtYdRzt1DmXND a/rgy8+iFN7T/MEd4r/OX1n9beXuw4/YMcnZEEulEjwzcoKq7E9WvATA8YwTB3uT zLhtELO/ofwAV7d2AkZC+RQLj0CgDrjbdEsc4zqjmkiuvFsLbZ0WP9ugjRIkMCA0 SbVGWArdD4kIBwrTUYbqvz3WiQCGgEYyQnDILOge8EdALpgUufDNGAv99fMngF15 aIlyTQoNwnug73Jj0+N8Farl39gtUbIIAbR/q+NTDieYIsO065mZmy9eFR7Yhm9w mzTzvQ== Received: from beta.dmz-ap.st.com (beta.dmz-ap.st.com [138.198.100.35]) by mx07-00178001.pphosted.com (PPS) with ESMTPS id 456krt8b9d-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Wed, 05 Mar 2025 10:53:55 +0100 (CET) Received: from euls16034.sgp.st.com (euls16034.sgp.st.com [10.75.44.20]) by beta.dmz-ap.st.com (STMicroelectronics) with ESMTP id ECF5540082; Wed, 5 Mar 2025 10:52:45 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node5.st.com [10.75.129.134]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id EDA235A523A; Wed, 5 Mar 2025 10:49:50 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE5.st.com (10.75.129.134) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 5 Mar 2025 10:49:50 +0100 Received: from localhost (10.48.86.222) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 5 Mar 2025 10:49:50 +0100 From: Fabrice Gasnier To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v3 1/8] dt-bindings: mfd: stm32-lptimer: add support for stm32mp25 Date: Wed, 5 Mar 2025 10:49:28 +0100 Message-ID: <20250305094935.595667-2-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250305094935.595667-1-fabrice.gasnier@foss.st.com> References: <20250305094935.595667-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-05_03,2025-03-05_01,2024-11-22_01 Content-Type: text/plain; charset="utf-8" Add a new stm32mp25 compatible to stm32-lptimer dt-bindings, to support STM32MP25 SoC. Some features has been updated or added to the low-power timer: - new capture compare channels - up to two PWM channels - PWM input capture - peripheral interconnect in stm32mp25 has been updated (new triggers). - registers/bits has been added or revisited (IER access). So introduce a new compatible to handle this diversity. Signed-off-by: Fabrice Gasnier Reviewed-by: Rob Herring (Arm) --- Changes in V3: - Fix yaml indentation issue found by Rob's bot Changes in V2: - Use fallback compatibles, along with stm32mp25 specific compatible - trigger identifier can be up to 4 (e.g. from LPTIM1..5) --- .../bindings/mfd/st,stm32-lptimer.yaml | 40 ++++++++++++++++--- 1 file changed, 34 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml b/= Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml index d41308856408..4eabafb8079d 100644 --- a/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml +++ b/Documentation/devicetree/bindings/mfd/st,stm32-lptimer.yaml @@ -21,7 +21,12 @@ maintainers: =20 properties: compatible: - const: st,stm32-lptimer + oneOf: + - items: + - const: st,stm32mp25-lptimer + - const: st,stm32-lptimer + - items: + - const: st,stm32-lptimer =20 reg: maxItems: 1 @@ -48,13 +53,21 @@ properties: minItems: 1 maxItems: 2 =20 + power-domains: + maxItems: 1 + pwm: type: object additionalProperties: false =20 properties: compatible: - const: st,stm32-pwm-lp + oneOf: + - items: + - const: st,stm32mp25-pwm-lp + - const: st,stm32-pwm-lp + - items: + - const: st,stm32-pwm-lp =20 "#pwm-cells": const: 3 @@ -69,7 +82,12 @@ properties: =20 properties: compatible: - const: st,stm32-lptimer-counter + oneOf: + - items: + - const: st,stm32mp25-lptimer-counter + - const: st,stm32-lptimer-counter + - items: + - const: st,stm32-lptimer-counter =20 required: - compatible @@ -80,7 +98,12 @@ properties: =20 properties: compatible: - const: st,stm32-lptimer-timer + oneOf: + - items: + - const: st,stm32mp25-lptimer-timer + - const: st,stm32-lptimer-timer + - items: + - const: st,stm32-lptimer-timer =20 required: - compatible @@ -92,13 +115,18 @@ patternProperties: =20 properties: compatible: - const: st,stm32-lptimer-trigger + oneOf: + - items: + - const: st,stm32mp25-lptimer-trigger + - const: st,stm32-lptimer-trigger + - items: + - const: st,stm32-lptimer-trigger =20 reg: description: Identify trigger hardware block. items: minimum: 0 - maximum: 2 + maximum: 4 =20 required: - compatible --=20 2.25.1 From nobody Mon Feb 9 02:55:14 2026 Received: from mx08-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id EB9BD207A10; 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charset="utf-8" Add support for STM32MP25 SoC. A new hardware configuration register (HWCFGR2) has been added, to gather number of capture/compare channels, autonomous mode and input capture capability. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features. This can now be read from HWCFGR registers. Add new registers to the stm32-lptimer.h: CCMR1, CCR2, HWCFGR1/2 and VERR. Update the stm32_lptimer data struct so signal the number of capture/compare channels to the child devices. Also Remove some unused bit masks (CMPOK_ARROK / CMPOKCF_ARROKCF). Signed-off-by: Fabrice Gasnier --- Changes in V2: - rely on fallback compatible as no specific .data is associated to the driver. Compatibility is added by reading hardware configuration registers. - read version register, to be used by clockevent child driver - rename register/bits definitions --- drivers/mfd/stm32-lptimer.c | 33 ++++++++++++++++++++++++++++- include/linux/mfd/stm32-lptimer.h | 35 ++++++++++++++++++++++++++++--- 2 files changed, 64 insertions(+), 4 deletions(-) diff --git a/drivers/mfd/stm32-lptimer.c b/drivers/mfd/stm32-lptimer.c index b2704a9809c7..09073dbc9c80 100644 --- a/drivers/mfd/stm32-lptimer.c +++ b/drivers/mfd/stm32-lptimer.c @@ -6,6 +6,7 @@ * Inspired by Benjamin Gaignard's stm32-timers driver */ =20 +#include #include #include #include @@ -49,6 +50,36 @@ static int stm32_lptimer_detect_encoder(struct stm32_lpt= imer *ddata) return 0; } =20 +static int stm32_lptimer_detect_hwcfgr(struct stm32_lptimer *ddata) +{ + u32 val; + int ret; + + ret =3D regmap_read(ddata->regmap, STM32_LPTIM_VERR, &ddata->version); + if (ret) + return ret; + + /* Try to guess parameters from HWCFGR: e.g. encoder mode (STM32MP15) */ + ret =3D regmap_read(ddata->regmap, STM32_LPTIM_HWCFGR1, &val); + if (ret) + return ret; + + /* Fallback to legacy init if HWCFGR isn't present */ + if (!val) + return stm32_lptimer_detect_encoder(ddata); + + ddata->has_encoder =3D FIELD_GET(STM32_LPTIM_HWCFGR1_ENCODER, val); + + ret =3D regmap_read(ddata->regmap, STM32_LPTIM_HWCFGR2, &val); + if (ret) + return ret; + + /* Number of capture/compare channels */ + ddata->num_cc_chans =3D FIELD_GET(STM32_LPTIM_HWCFGR2_CHAN_NUM, val); + + return 0; +} + static int stm32_lptimer_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; @@ -73,7 +104,7 @@ static int stm32_lptimer_probe(struct platform_device *p= dev) if (IS_ERR(ddata->clk)) return PTR_ERR(ddata->clk); =20 - ret =3D stm32_lptimer_detect_encoder(ddata); + ret =3D stm32_lptimer_detect_hwcfgr(ddata); if (ret) return ret; =20 diff --git a/include/linux/mfd/stm32-lptimer.h b/include/linux/mfd/stm32-lp= timer.h index 06d3f11dc3c9..30ebd3152e1a 100644 --- a/include/linux/mfd/stm32-lptimer.h +++ b/include/linux/mfd/stm32-lptimer.h @@ -17,20 +17,28 @@ #define STM32_LPTIM_IER 0x08 /* Interrupt Enable Reg */ #define STM32_LPTIM_CFGR 0x0C /* Configuration Reg */ #define STM32_LPTIM_CR 0x10 /* Control Reg */ -#define STM32_LPTIM_CMP 0x14 /* Compare Reg */ +#define STM32_LPTIM_CMP 0x14 /* Compare Reg (MP25 CCR1) */ #define STM32_LPTIM_ARR 0x18 /* Autoreload Reg */ #define STM32_LPTIM_CNT 0x1C /* Counter Reg */ +#define STM32_LPTIM_CCMR1 0x2C /* Capture/Compare Mode MP25 */ +#define STM32_LPTIM_CCR2 0x34 /* Compare Reg2 MP25 */ + +#define STM32_LPTIM_HWCFGR2 0x3EC /* Hardware configuration register 2 - M= P25 */ +#define STM32_LPTIM_HWCFGR1 0x3F0 /* Hardware configuration register 1 - M= P15 */ +#define STM32_LPTIM_VERR 0x3F4 /* Version identification register - MP15 */ =20 /* STM32_LPTIM_ISR - bit fields */ +#define STM32_LPTIM_CMP2_ARROK (BIT(19) | BIT(4)) #define STM32_LPTIM_CMPOK_ARROK GENMASK(4, 3) #define STM32_LPTIM_ARROK BIT(4) #define STM32_LPTIM_CMPOK BIT(3) =20 /* STM32_LPTIM_ICR - bit fields */ -#define STM32_LPTIM_ARRMCF BIT(1) +#define STM32_LPTIM_CMP2OKCF_ARROKCF (BIT(19) | BIT(4)) #define STM32_LPTIM_CMPOKCF_ARROKCF GENMASK(4, 3) +#define STM32_LPTIM_ARRMCF BIT(1) =20 -/* STM32_LPTIM_IER - bit flieds */ +/* STM32_LPTIM_IER - bit fields */ #define STM32_LPTIM_ARRMIE BIT(1) =20 /* STM32_LPTIM_CR - bit fields */ @@ -53,16 +61,37 @@ /* STM32_LPTIM_ARR */ #define STM32_LPTIM_MAX_ARR 0xFFFF =20 +/* STM32_LPTIM_CCMR1 */ +#define STM32_LPTIM_CC2P GENMASK(19, 18) +#define STM32_LPTIM_CC2E BIT(17) +#define STM32_LPTIM_CC2SEL BIT(16) +#define STM32_LPTIM_CC1P GENMASK(3, 2) +#define STM32_LPTIM_CC1E BIT(1) +#define STM32_LPTIM_CC1SEL BIT(0) + +/* STM32_LPTIM_HWCFGR1 */ +#define STM32_LPTIM_HWCFGR1_ENCODER BIT(16) + +/* STM32_LPTIM_HWCFGR2 */ +#define STM32_LPTIM_HWCFGR2_CHAN_NUM GENMASK(3, 0) + +/* STM32_LPTIM_VERR */ +#define STM32_LPTIM_VERR_23 0x23 /* STM32MP25 */ + /** * struct stm32_lptimer - STM32 Low-Power Timer data assigned by parent de= vice * @clk: clock reference for this instance * @regmap: register map reference for this instance * @has_encoder: indicates this Low-Power Timer supports encoder mode + * @num_cc_chans: indicates the number of capture/compare channels + * @version: indicates the major and minor revision of the controller */ struct stm32_lptimer { struct clk *clk; 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charset="utf-8" From: Olivier Moysan Add support for STM32MP25 SoC. Use newly introduced compatible to handle this new HW variant. Add new trigger definitions that can be used by the stm32 analog-to-digital converter. Use compatible data to identify them. Signed-off-by: Olivier Moysan Signed-off-by: Fabrice Gasnier --- drivers/iio/trigger/stm32-lptimer-trigger.c | 109 +++++++++++++++--- include/linux/iio/timer/stm32-lptim-trigger.h | 9 ++ 2 files changed, 99 insertions(+), 19 deletions(-) diff --git a/drivers/iio/trigger/stm32-lptimer-trigger.c b/drivers/iio/trig= ger/stm32-lptimer-trigger.c index f1e18913236a..995234c1e7d5 100644 --- a/drivers/iio/trigger/stm32-lptimer-trigger.c +++ b/drivers/iio/trigger/stm32-lptimer-trigger.c @@ -16,16 +16,44 @@ #include #include =20 -/* List Low-Power Timer triggers */ -static const char * const stm32_lptim_triggers[] =3D { - LPTIM1_OUT, - LPTIM2_OUT, - LPTIM3_OUT, +/* Maximum triggers + one trailing null entry to indicate the end of array= */ +#define MAX_TRIGGERS 3 + +struct stm32_lptim_cfg { + const char * const (*triggers)[MAX_TRIGGERS]; + unsigned int nb_triggers; +}; + +/* List Low-Power Timer triggers for H7, MP13, MP15 */ +static const char * const stm32_lptim_triggers[][MAX_TRIGGERS] =3D { + { LPTIM1_OUT,}, + { LPTIM2_OUT,}, + { LPTIM3_OUT,}, +}; + +/* List Low-Power Timer triggers for STM32MP25 */ +static const char * const stm32mp25_lptim_triggers[][MAX_TRIGGERS] =3D { + { LPTIM1_CH1, LPTIM1_CH2, }, + { LPTIM2_CH1, LPTIM2_CH2, }, + { LPTIM3_CH1,}, + { LPTIM4_CH1,}, + { LPTIM5_OUT,}, +}; + +static const struct stm32_lptim_cfg stm32mp15_lptim_cfg =3D { + .triggers =3D stm32_lptim_triggers, + .nb_triggers =3D ARRAY_SIZE(stm32_lptim_triggers), +}; + +static const struct stm32_lptim_cfg stm32mp25_lptim_cfg =3D { + .triggers =3D stm32mp25_lptim_triggers, + .nb_triggers =3D ARRAY_SIZE(stm32mp25_lptim_triggers), }; =20 struct stm32_lptim_trigger { struct device *dev; - const char *trg; + const char * const *triggers; + struct list_head tr_list; }; =20 static int stm32_lptim_validate_device(struct iio_trigger *trig, @@ -54,25 +82,49 @@ bool is_stm32_lptim_trigger(struct iio_trigger *trig) } EXPORT_SYMBOL(is_stm32_lptim_trigger); =20 -static int stm32_lptim_setup_trig(struct stm32_lptim_trigger *priv) +static void stm32_lptim_unregister_triggers(struct stm32_lptim_trigger *pr= iv) { - struct iio_trigger *trig; + struct iio_trigger *tr; =20 - trig =3D devm_iio_trigger_alloc(priv->dev, "%s", priv->trg); - if (!trig) - return -ENOMEM; + list_for_each_entry(tr, &priv->tr_list, alloc_list) + iio_trigger_unregister(tr); +} + +static int stm32_lptim_register_triggers(struct stm32_lptim_trigger *priv) +{ + const char * const *cur =3D priv->triggers; + int ret; =20 - trig->dev.parent =3D priv->dev->parent; - trig->ops =3D &stm32_lptim_trigger_ops; - iio_trigger_set_drvdata(trig, priv); + INIT_LIST_HEAD(&priv->tr_list); =20 - return devm_iio_trigger_register(priv->dev, trig); + while (cur && *cur) { + struct iio_trigger *trig; + + trig =3D devm_iio_trigger_alloc(priv->dev, "%s", *cur); + if (!trig) + return -ENOMEM; + + trig->dev.parent =3D priv->dev->parent; + trig->ops =3D &stm32_lptim_trigger_ops; + iio_trigger_set_drvdata(trig, priv); + + ret =3D iio_trigger_register(trig); + if (ret) + return ret; + + list_add_tail(&trig->alloc_list, &priv->tr_list); + cur++; + } + + return 0; } =20 static int stm32_lptim_trigger_probe(struct platform_device *pdev) { struct stm32_lptim_trigger *priv; + struct stm32_lptim_cfg const *lptim_cfg; u32 index; + int ret; =20 priv =3D devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL); if (!priv) @@ -81,23 +133,42 @@ static int stm32_lptim_trigger_probe(struct platform_d= evice *pdev) if (device_property_read_u32(&pdev->dev, "reg", &index)) return -EINVAL; =20 - if (index >=3D ARRAY_SIZE(stm32_lptim_triggers)) + lptim_cfg =3D device_get_match_data(&pdev->dev); + + if (index >=3D lptim_cfg->nb_triggers) return -EINVAL; =20 priv->dev =3D &pdev->dev; - priv->trg =3D stm32_lptim_triggers[index]; + priv->triggers =3D lptim_cfg->triggers[index]; + + ret =3D stm32_lptim_register_triggers(priv); + if (ret) { + stm32_lptim_unregister_triggers(priv); + return ret; + } + + platform_set_drvdata(pdev, priv); + + return 0; +} + +static void stm32_lptim_trigger_remove(struct platform_device *pdev) +{ + struct stm32_lptim_trigger *priv =3D platform_get_drvdata(pdev); =20 - return stm32_lptim_setup_trig(priv); + stm32_lptim_unregister_triggers(priv); } =20 static const struct of_device_id stm32_lptim_trig_of_match[] =3D { - { .compatible =3D "st,stm32-lptimer-trigger", }, + { .compatible =3D "st,stm32-lptimer-trigger", .data =3D (void *)&stm32mp1= 5_lptim_cfg }, + { .compatible =3D "st,stm32mp25-lptimer-trigger", .data =3D (void *)&stm3= 2mp25_lptim_cfg}, {}, }; MODULE_DEVICE_TABLE(of, stm32_lptim_trig_of_match); =20 static struct platform_driver stm32_lptim_trigger_driver =3D { .probe =3D stm32_lptim_trigger_probe, + .remove =3D stm32_lptim_trigger_remove, .driver =3D { .name =3D "stm32-lptimer-trigger", .of_match_table =3D stm32_lptim_trig_of_match, diff --git a/include/linux/iio/timer/stm32-lptim-trigger.h b/include/linux/= iio/timer/stm32-lptim-trigger.h index a34dcf6a6001..ce3cf0addb2e 100644 --- a/include/linux/iio/timer/stm32-lptim-trigger.h +++ b/include/linux/iio/timer/stm32-lptim-trigger.h @@ -14,6 +14,15 @@ #define LPTIM1_OUT "lptim1_out" #define LPTIM2_OUT "lptim2_out" #define LPTIM3_OUT "lptim3_out" +#define LPTIM4_OUT "lptim4_out" +#define LPTIM5_OUT "lptim5_out" + +#define LPTIM1_CH1 "lptim1_ch1" +#define LPTIM1_CH2 "lptim1_ch2" +#define LPTIM2_CH1 "lptim2_ch1" +#define LPTIM2_CH2 "lptim2_ch2" +#define LPTIM3_CH1 "lptim3_ch1" +#define LPTIM4_CH1 "lptim4_ch1" =20 #if IS_REACHABLE(CONFIG_IIO_STM32_LPTIMER_TRIGGER) bool is_stm32_lptim_trigger(struct iio_trigger *trig); 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charset="utf-8" On stm32mp25, DIER (former IER) must only be modified when the lptimer is enabled. On earlier SoCs, it must be only be modified when it is disabled. Read the LPTIM_VERR register to properly manage the enable state, before accessing IER. Signed-off-by: Patrick Delaunay Signed-off-by: Fabrice Gasnier --- Changes in V2: - rely on fallback compatible as no specific .data is associated to the driver. Use version data from MFD core. - Added interrupt enable register access update in (missed in V1) --- drivers/clocksource/timer-stm32-lp.c | 26 ++++++++++++++++++++++---- 1 file changed, 22 insertions(+), 4 deletions(-) diff --git a/drivers/clocksource/timer-stm32-lp.c b/drivers/clocksource/tim= er-stm32-lp.c index a4c95161cb22..96d975adf7a4 100644 --- a/drivers/clocksource/timer-stm32-lp.c +++ b/drivers/clocksource/timer-stm32-lp.c @@ -25,6 +25,7 @@ struct stm32_lp_private { struct clock_event_device clkevt; unsigned long period; struct device *dev; + bool ier_wr_enabled; /* Enables LPTIMER before writing into IER register = */ }; =20 static struct stm32_lp_private* @@ -37,8 +38,15 @@ static int stm32_clkevent_lp_shutdown(struct clock_event= _device *clkevt) { struct stm32_lp_private *priv =3D to_priv(clkevt); =20 - regmap_write(priv->reg, STM32_LPTIM_CR, 0); + /* Disable LPTIMER either before or after writing IER register (else, kee= p it enabled) */ + if (!priv->ier_wr_enabled) + regmap_write(priv->reg, STM32_LPTIM_CR, 0); + regmap_write(priv->reg, STM32_LPTIM_IER, 0); + + if (priv->ier_wr_enabled) + regmap_write(priv->reg, STM32_LPTIM_CR, 0); + /* clear pending flags */ regmap_write(priv->reg, STM32_LPTIM_ICR, STM32_LPTIM_ARRMCF); =20 @@ -51,12 +59,21 @@ static int stm32_clkevent_lp_set_timer(unsigned long ev= t, { struct stm32_lp_private *priv =3D to_priv(clkevt); =20 - /* disable LPTIMER to be able to write into IER register*/ - regmap_write(priv->reg, STM32_LPTIM_CR, 0); + if (!priv->ier_wr_enabled) { + /* Disable LPTIMER to be able to write into IER register */ + regmap_write(priv->reg, STM32_LPTIM_CR, 0); + } else { + /* Enable LPTIMER to be able to write into IER register */ + regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); + } + /* enable ARR interrupt */ regmap_write(priv->reg, STM32_LPTIM_IER, STM32_LPTIM_ARRMIE); + /* enable LPTIMER to be able to write into ARR register */ - regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); + if (!priv->ier_wr_enabled) + regmap_write(priv->reg, STM32_LPTIM_CR, STM32_LPTIM_ENABLE); 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Wed, 5 Mar 2025 10:52:46 +0100 (CET) Received: from Webmail-eu.st.com (eqndag1node6.st.com [10.75.129.135]) by euls16034.sgp.st.com (STMicroelectronics) with ESMTP id ECFD85A8C93; Wed, 5 Mar 2025 10:49:54 +0100 (CET) Received: from SAFDAG1NODE1.st.com (10.75.90.17) by EQNDAG1NODE6.st.com (10.75.129.135) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 5 Mar 2025 10:49:54 +0100 Received: from localhost (10.48.86.222) by SAFDAG1NODE1.st.com (10.75.90.17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256) id 15.1.2507.39; Wed, 5 Mar 2025 10:49:54 +0100 From: Fabrice Gasnier To: , , , , , , , , CC: , , , , , , , , , , Subject: [PATCH v3 5/8] pwm: stm32-lp: add support for stm32mp25 Date: Wed, 5 Mar 2025 10:49:32 +0100 Message-ID: <20250305094935.595667-6-fabrice.gasnier@foss.st.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250305094935.595667-1-fabrice.gasnier@foss.st.com> References: <20250305094935.595667-1-fabrice.gasnier@foss.st.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: EQNCAS1NODE3.st.com (10.75.129.80) To SAFDAG1NODE1.st.com (10.75.90.17) X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-05_03,2025-03-05_01,2024-11-22_01 Add support for STM32MP25 SoC. A new compatible has been added to the dt-bindings. It represents handle new features, registers and bits diversity. It isn't used currently in the driver, as matching is done by retrieving MFD parent data. New dedicated capture/compare channels has been added: e.g. a new compare register for channel 2. Some controls (polarity / cc channel enable) are handled in CCMR register on this new variant (instead of wavepol bit). So, Low-power timer can now have up to two PWM outputs. Use device data from the MFD parent to configure the number of PWM channels e.g. 'npwm'. Update current get_state() and apply() ops to support either: - one PWM channel (as on older revision, or LPTIM5 on STM32MP25) - two PWM channels (e.g. LPTIM1/2/3/4 on STM32MP25 that has the full feature set) Introduce new routines to manage common prescaler, reload register and global enable bit. Signed-off-by: Fabrice Gasnier --- Changes in V2: - rely on fallback compatible as no specific .data is associated to the driver. Matching is achieved by using MFD parent data. - renamed registers/bits defintions --- drivers/pwm/pwm-stm32-lp.c | 219 ++++++++++++++++++++++++++++++++----- 1 file changed, 193 insertions(+), 26 deletions(-) diff --git a/drivers/pwm/pwm-stm32-lp.c b/drivers/pwm/pwm-stm32-lp.c index 5832dce8ed9d..4789eafb8bac 100644 --- a/drivers/pwm/pwm-stm32-lp.c +++ b/drivers/pwm/pwm-stm32-lp.c @@ -20,6 +20,7 @@ struct stm32_pwm_lp { struct clk *clk; struct regmap *regmap; + unsigned int num_cc_chans; }; =20 static inline struct stm32_pwm_lp *to_stm32_pwm_lp(struct pwm_chip *chip) @@ -30,13 +31,101 @@ static inline struct stm32_pwm_lp *to_stm32_pwm_lp(str= uct pwm_chip *chip) /* STM32 Low-Power Timer is preceded by a configurable power-of-2 prescale= r */ #define STM32_LPTIM_MAX_PRESCALER 128 =20 +static int stm32_pwm_lp_update_allowed(struct stm32_pwm_lp *priv, int chan= nel) +{ + int ret; + u32 ccmr1; + unsigned long ccmr; + + /* Only one PWM on this LPTIMER: enable, prescaler and reload value can b= e changed */ + if (!priv->num_cc_chans) + return true; + + ret =3D regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); + if (ret) + return ret; + ccmr =3D ccmr1 & (STM32_LPTIM_CC1E | STM32_LPTIM_CC2E); + + /* More than one channel enabled: enable, prescaler or ARR value can't be= changed */ + if (bitmap_weight(&ccmr, sizeof(u32) * BITS_PER_BYTE) > 1) + return false; + + /* + * Only one channel is enabled (or none): check status on the other chann= el, to + * report if enable, prescaler or ARR value can be changed. + */ + if (channel) + return !(ccmr1 & STM32_LPTIM_CC1E); + else + return !(ccmr1 & STM32_LPTIM_CC2E); +} + +static int stm32_pwm_lp_compare_channel_apply(struct stm32_pwm_lp *priv, i= nt channel, + bool enable, enum pwm_polarity polarity) +{ + u32 ccmr1, val, mask; + bool reenable; + int ret; + + /* No dedicated CC channel: nothing to do */ + if (!priv->num_cc_chans) + return 0; + + ret =3D regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); + if (ret) + return ret; + + if (channel) { + /* Must disable CC channel (CCxE) to modify polarity (CCxP), then re-ena= ble */ + reenable =3D (enable && FIELD_GET(STM32_LPTIM_CC2E, ccmr1)) && + (polarity !=3D FIELD_GET(STM32_LPTIM_CC2P, ccmr1)); + + mask =3D STM32_LPTIM_CC2SEL | STM32_LPTIM_CC2E | STM32_LPTIM_CC2P; + val =3D FIELD_PREP(STM32_LPTIM_CC2P, polarity); + val |=3D FIELD_PREP(STM32_LPTIM_CC2E, enable); + } else { + reenable =3D (enable && FIELD_GET(STM32_LPTIM_CC1E, ccmr1)) && + (polarity !=3D FIELD_GET(STM32_LPTIM_CC1P, ccmr1)); + + mask =3D STM32_LPTIM_CC1SEL | STM32_LPTIM_CC1E | STM32_LPTIM_CC1P; + val =3D FIELD_PREP(STM32_LPTIM_CC1P, polarity); + val |=3D FIELD_PREP(STM32_LPTIM_CC1E, enable); + } + + if (reenable) { + u32 cfgr, presc; + unsigned long rate; + unsigned int delay_us; + + ret =3D regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, + channel ? STM32_LPTIM_CC2E : STM32_LPTIM_CC1E, 0); + if (ret) + return ret; + /* + * After a write to the LPTIM_CCMRx register, a new write operation can = only be + * performed after a delay of at least (PRESC =C3=97 3) clock cycles + */ + ret =3D regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); + if (ret) + return ret; + presc =3D FIELD_GET(STM32_LPTIM_PRESC, cfgr); + rate =3D clk_get_rate(priv->clk) >> presc; + if (!rate) + return -EINVAL; + delay_us =3D 3 * DIV_ROUND_UP(USEC_PER_SEC, rate); + usleep_range(delay_us, delay_us * 2); + } + + return regmap_update_bits(priv->regmap, STM32_LPTIM_CCMR1, mask, val); +} + static int stm32_pwm_lp_apply(struct pwm_chip *chip, struct pwm_device *pw= m, const struct pwm_state *state) { struct stm32_pwm_lp *priv =3D to_stm32_pwm_lp(chip); unsigned long long prd, div, dty; struct pwm_state cstate; - u32 val, mask, cfgr, presc =3D 0; + u32 arr, val, mask, cfgr, presc =3D 0; bool reenable; int ret; =20 @@ -45,10 +134,28 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, s= truct pwm_device *pwm, =20 if (!state->enabled) { if (cstate.enabled) { - /* Disable LP timer */ - ret =3D regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + /* Disable CC channel if any */ + ret =3D stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, false, + state->polarity); if (ret) return ret; + ret =3D regmap_write(priv->regmap, pwm->hwpwm ? + STM32_LPTIM_CCR2 : STM32_LPTIM_CMP, 0); + if (ret) + return ret; + + /* Check if the timer can be disabled */ + ret =3D stm32_pwm_lp_update_allowed(priv, pwm->hwpwm); + if (ret < 0) + return ret; + + if (ret) { + /* Disable LP timer */ + ret =3D regmap_write(priv->regmap, STM32_LPTIM_CR, 0); + if (ret) + return ret; + } + /* disable clock to PWM counter */ clk_disable(priv->clk); } @@ -79,6 +186,23 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, st= ruct pwm_device *pwm, dty =3D prd * state->duty_cycle; do_div(dty, state->period); =20 + ret =3D regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); + if (ret) + return ret; + + /* + * When there are several channels, they share the same prescaler and rel= oad value. + * Check if this can be changed, or the values are the same for all chann= els. + */ + if (!stm32_pwm_lp_update_allowed(priv, pwm->hwpwm)) { + ret =3D regmap_read(priv->regmap, STM32_LPTIM_ARR, &arr); + if (ret) + return ret; + + if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) !=3D presc) || (arr !=3D prd - 1= )) + return -EBUSY; + } + if (!cstate.enabled) { /* enable clock to drive PWM counter */ ret =3D clk_enable(priv->clk); @@ -86,15 +210,20 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, s= truct pwm_device *pwm, return ret; } =20 - ret =3D regmap_read(priv->regmap, STM32_LPTIM_CFGR, &cfgr); - if (ret) - goto err; - if ((FIELD_GET(STM32_LPTIM_PRESC, cfgr) !=3D presc) || - (FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) !=3D state->polarity)) { + ((FIELD_GET(STM32_LPTIM_WAVPOL, cfgr) !=3D state->polarity) && !priv-= >num_cc_chans)) { val =3D FIELD_PREP(STM32_LPTIM_PRESC, presc); - val |=3D FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); - mask =3D STM32_LPTIM_PRESC | STM32_LPTIM_WAVPOL; + mask =3D STM32_LPTIM_PRESC; + + if (!priv->num_cc_chans) { + /* + * WAVPOL bit is only available when no capature compare channel is use= d, + * e.g. on LPTIMER instances that have only one output channel. CCMR1 is + * used otherwise. + */ + val |=3D FIELD_PREP(STM32_LPTIM_WAVPOL, state->polarity); + mask |=3D STM32_LPTIM_WAVPOL; + } =20 /* Must disable LP timer to modify CFGR */ reenable =3D true; @@ -120,20 +249,27 @@ static int stm32_pwm_lp_apply(struct pwm_chip *chip, = struct pwm_device *pwm, if (ret) goto err; =20 - ret =3D regmap_write(priv->regmap, STM32_LPTIM_CMP, prd - (1 + dty)); + /* Write CMP/CCRx register and ensure it's been properly written */ + ret =3D regmap_write(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_= LPTIM_CMP, + prd - (1 + dty)); if (ret) goto err; =20 - /* ensure CMP & ARR registers are properly written */ - ret =3D regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, + /* ensure ARR and CMP/CCRx registers are properly written */ + ret =3D regmap_read_poll_timeout(priv->regmap, STM32_LPTIM_ISR, val, pwm-= >hwpwm ? + (val & STM32_LPTIM_CMP2_ARROK) =3D=3D STM32_LPTIM_CMP2_ARROK : (val & STM32_LPTIM_CMPOK_ARROK) =3D=3D STM32_LPTIM_CMPOK_ARROK, 100, 1000); if (ret) { dev_err(pwmchip_parent(chip), "ARR/CMP registers write issue\n"); goto err; } - ret =3D regmap_write(priv->regmap, STM32_LPTIM_ICR, - STM32_LPTIM_CMPOKCF_ARROKCF); + ret =3D regmap_write(priv->regmap, STM32_LPTIM_ICR, pwm->hwpwm ? + STM32_LPTIM_CMP2OKCF_ARROKCF : STM32_LPTIM_CMPOKCF_ARROKCF); + if (ret) + goto err; + + ret =3D stm32_pwm_lp_compare_channel_apply(priv, pwm->hwpwm, true, state-= >polarity); if (ret) goto err; =20 @@ -161,11 +297,22 @@ static int stm32_pwm_lp_get_state(struct pwm_chip *ch= ip, { struct stm32_pwm_lp *priv =3D to_stm32_pwm_lp(chip); unsigned long rate =3D clk_get_rate(priv->clk); - u32 val, presc, prd; + u32 val, presc, prd, ccmr1; + bool enabled; u64 tmp; =20 regmap_read(priv->regmap, STM32_LPTIM_CR, &val); - state->enabled =3D !!FIELD_GET(STM32_LPTIM_ENABLE, val); + enabled =3D !!FIELD_GET(STM32_LPTIM_ENABLE, val); + if (priv->num_cc_chans) { + /* There's a CC chan, need to also check if it's enabled */ + regmap_read(priv->regmap, STM32_LPTIM_CCMR1, &ccmr1); + if (pwm->hwpwm) + enabled &=3D !!FIELD_GET(STM32_LPTIM_CC2E, ccmr1); + else + enabled &=3D !!FIELD_GET(STM32_LPTIM_CC1E, ccmr1); + } + state->enabled =3D enabled; + /* Keep PWM counter clock refcount in sync with PWM initial state */ if (state->enabled) { int ret =3D clk_enable(priv->clk); @@ -176,14 +323,21 @@ static int stm32_pwm_lp_get_state(struct pwm_chip *ch= ip, =20 regmap_read(priv->regmap, STM32_LPTIM_CFGR, &val); presc =3D FIELD_GET(STM32_LPTIM_PRESC, val); - state->polarity =3D FIELD_GET(STM32_LPTIM_WAVPOL, val); + if (priv->num_cc_chans) { + if (pwm->hwpwm) + state->polarity =3D FIELD_GET(STM32_LPTIM_CC2P, ccmr1); + else + state->polarity =3D FIELD_GET(STM32_LPTIM_CC1P, ccmr1); + } else { + state->polarity =3D FIELD_GET(STM32_LPTIM_WAVPOL, val); + } =20 regmap_read(priv->regmap, STM32_LPTIM_ARR, &prd); tmp =3D prd + 1; tmp =3D (tmp << presc) * NSEC_PER_SEC; state->period =3D DIV_ROUND_CLOSEST_ULL(tmp, rate); =20 - regmap_read(priv->regmap, STM32_LPTIM_CMP, &val); + regmap_read(priv->regmap, pwm->hwpwm ? STM32_LPTIM_CCR2 : STM32_LPTIM_CMP= , &val); tmp =3D prd - val; tmp =3D (tmp << presc) * NSEC_PER_SEC; state->duty_cycle =3D DIV_ROUND_CLOSEST_ULL(tmp, rate); @@ -201,15 +355,25 @@ static int stm32_pwm_lp_probe(struct platform_device = *pdev) struct stm32_lptimer *ddata =3D dev_get_drvdata(pdev->dev.parent); struct stm32_pwm_lp *priv; struct pwm_chip *chip; + unsigned int npwm; int ret; =20 - chip =3D devm_pwmchip_alloc(&pdev->dev, 1, sizeof(*priv)); + if (!ddata->num_cc_chans) { + /* No dedicated CC channel, so there's only one PWM channel */ + npwm =3D 1; + } else { + /* There are dedicated CC channels, each with one PWM output */ + npwm =3D ddata->num_cc_chans; + } + + chip =3D devm_pwmchip_alloc(&pdev->dev, npwm, sizeof(*priv)); if (IS_ERR(chip)) return PTR_ERR(chip); priv =3D to_stm32_pwm_lp(chip); =20 priv->regmap =3D ddata->regmap; priv->clk =3D ddata->clk; + priv->num_cc_chans =3D ddata->num_cc_chans; chip->ops =3D &stm32_pwm_lp_ops; =20 ret =3D devm_pwmchip_add(&pdev->dev, chip); @@ -225,12 +389,15 @@ static int stm32_pwm_lp_suspend(struct device *dev) { struct pwm_chip *chip =3D dev_get_drvdata(dev); struct pwm_state state; - - pwm_get_state(&chip->pwms[0], &state); - if (state.enabled) { - dev_err(dev, "The consumer didn't stop us (%s)\n", - chip->pwms[0].label); - return -EBUSY; + unsigned int i; + + for (i =3D 0; i < chip->npwm; i++) { + pwm_get_state(&chip->pwms[i], &state); + if (state.enabled) { + dev_err(dev, "The consumer didn't stop us (%s)\n", + chip->pwms[i].label); + return -EBUSY; + } } =20 return pinctrl_pm_select_sleep_state(dev); --=20 2.25.1 From nobody Mon Feb 9 02:55:14 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7000E2063F2; Wed, 5 Mar 2025 09:54:12 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=185.132.182.106 ARC-Seal: i=1; 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charset="utf-8" Enable the STM32 LP timer MFD core and clockevent drivers used on STM32MP257F-EV1 board, for PSCI OSI. Signed-off-by: Fabrice Gasnier --- Changes in v2: - dropped unused IIO trigger, PWM and counter driver unused on upstream board currently, as advised by Krzysztof --- arch/arm64/configs/defconfig | 2 ++ 1 file changed, 2 insertions(+) diff --git a/arch/arm64/configs/defconfig b/arch/arm64/configs/defconfig index 1f25423de383..b29b2350ae27 100644 --- a/arch/arm64/configs/defconfig +++ b/arch/arm64/configs/defconfig @@ -775,6 +775,7 @@ CONFIG_MFD_TI_LP873X=3Dm CONFIG_MFD_TPS65219=3Dy CONFIG_MFD_TPS6594_I2C=3Dm CONFIG_MFD_ROHM_BD718XX=3Dy +CONFIG_MFD_STM32_LPTIMER=3Dm CONFIG_MFD_WCD934X=3Dm CONFIG_MFD_KHADAS_MCU=3Dm CONFIG_REGULATOR_FIXED_VOLTAGE=3Dy @@ -1401,6 +1402,7 @@ CONFIG_CLK_RENESAS_VBATTB=3Dm CONFIG_HWSPINLOCK=3Dy CONFIG_HWSPINLOCK_QCOM=3Dy CONFIG_TEGRA186_TIMER=3Dy +CONFIG_CLKSRC_STM32_LP=3Dy CONFIG_RENESAS_OSTM=3Dy CONFIG_ARM_MHU=3Dy CONFIG_IMX_MBOX=3Dy --=20 2.25.1 From nobody Mon Feb 9 02:55:14 2026 Received: from mx07-00178001.pphosted.com (mx07-00178001.pphosted.com [185.132.182.106]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1D40C205E0B; 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charset="utf-8" Add low-power timer (LPTimer) support on STM32MP25 SoC. The full feature set is implemented in LPTIM1/2/3/4. LPTIM5 supports a smaller set of features (no capture/compare) channel. Still, LPTIM5 can be used as single PWM, counter, trigger or timer. Signed-off-by: Fabrice Gasnier --- Changes in V2: - Adopt two compatibles: newly introduced "st,stm32mp25-..." compatible, and fallback "st,stm32-...". --- arch/arm64/boot/dts/st/stm32mp251.dtsi | 177 +++++++++++++++++++++++++ 1 file changed, 177 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp251.dtsi b/arch/arm64/boot/dts/s= t/stm32mp251.dtsi index f3c6cdfd7008..505176276e72 100644 --- a/arch/arm64/boot/dts/st/stm32mp251.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp251.dtsi @@ -238,6 +238,78 @@ rifsc: bus@42080000 { #access-controller-cells =3D <1>; ranges; =20 + lptimer1: timer@40090000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x40090000 0x400>; + interrupts-extended =3D <&exti1 47 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM1>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 17>; + power-domains =3D <&RET_PD>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@0 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <0>; + status =3D "disabled"; + }; + }; + + lptimer2: timer@400a0000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x400a0000 0x400>; + interrupts-extended =3D <&exti1 48 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM2>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 18>; + power-domains =3D <&RET_PD>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@1 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <1>; + status =3D "disabled"; + }; + }; + i2s2: audio-controller@400b0000 { compatible =3D "st,stm32mp25-i2s"; reg =3D <0x400b0000 0x400>; @@ -799,6 +871,111 @@ i2c8: i2c@46040000 { status =3D "disabled"; }; =20 + lptimer3: timer@46050000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x46050000 0x400>; + interrupts-extended =3D <&exti2 29 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM3>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 19>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@2 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <2>; + status =3D "disabled"; + }; + }; + + lptimer4: timer@46060000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x46060000 0x400>; + interrupts-extended =3D <&exti2 30 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM4>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 20>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@3 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <3>; + status =3D "disabled"; + }; + }; + + lptimer5: timer@46070000 { + compatible =3D "st,stm32mp25-lptimer", "st,stm32-lptimer"; + reg =3D <0x46070000 0x400>; + interrupts-extended =3D <&exti2 31 IRQ_TYPE_LEVEL_HIGH>; + clocks =3D <&rcc CK_KER_LPTIM5>; + clock-names =3D "mux"; + #address-cells =3D <1>; + #size-cells =3D <0>; + access-controllers =3D <&rifsc 21>; + wakeup-source; + status =3D "disabled"; + + counter { + compatible =3D "st,stm32mp25-lptimer-counter", "st,stm32-lptimer-coun= ter"; + status =3D "disabled"; + }; + + pwm { + compatible =3D "st,stm32mp25-pwm-lp", "st,stm32-pwm-lp"; + #pwm-cells =3D <3>; + status =3D "disabled"; + }; + + timer { + compatible =3D "st,stm32mp25-lptimer-timer", "st,stm32-lptimer-timer"; + status =3D "disabled"; + }; + + trigger@4 { + compatible =3D "st,stm32mp25-lptimer-trigger", "st,stm32-lptimer-trig= ger"; + reg =3D <4>; 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charset="utf-8" During the low power modes the generic ARM timer is deactivated, so the the tick broadcast is used, based on LPTIMER3 which is clocked by LSE on STMicroelectronics boards. Signed-off-by: Patrick Delaunay Signed-off-by: Fabrice Gasnier --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/d= ts/st/stm32mp257f-ev1.dts index 1b88485a62a1..242115863ab4 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -190,6 +190,14 @@ &i2c8 { status =3D "disabled"; }; =20 +/* use LPTIMER with tick broadcast for suspend mode */ +&lptimer3 { + status =3D "okay"; + timer { + status =3D "okay"; + }; +}; + &rtc { status =3D "okay"; }; --=20 2.25.1