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charset="utf-8" Add bindings for Omnivision OX05B1S sensor. Also add compatible for Omnivision OS08A20 sensor. Signed-off-by: Mirela Rabulea Reviewed-by: Krzysztof Kozlowski --- Changes in v4: Collect Reviewed-by Changes in v3: Use unevaluatedProperties: false and drop orientation/rotation Drop items and keep alphabetical order in compatible property Shorten the description for reset_gpio Make the supplies required. Use generic node name (camera instead of ox05b1s) Changes in v2: Small updates on description Update subject, drop "bindings" and "driver" Just one binding patch (squash os08a20 bindings) Re-flow to 80 columns. Drop clock name (not needed in case of single clock) Make the clock required property, strictly from sensor module point of vie= w, it is mandatory (will use a fixed clock for nxp board) Add regulators: avdd, dvdd, dovdd Add $ref: /schemas/media/video-interface-devices.yaml Drop assigned-clock* properties (defined in clocks.yaml) Keep "additionalProperties : false" and orientation/rotation (unevaluatedP= roperties: false was suggested, but only orientation/rotation are needed fr= om video-interface-devices.yaml) Include assigned-clock* in the example, for completeness sake (although it= was also suggested to omit them) .../bindings/media/i2c/ovti,ox05b1s.yaml | 119 ++++++++++++++++++ 1 file changed, 119 insertions(+) create mode 100644 Documentation/devicetree/bindings/media/i2c/ovti,ox05b1= s.yaml diff --git a/Documentation/devicetree/bindings/media/i2c/ovti,ox05b1s.yaml = b/Documentation/devicetree/bindings/media/i2c/ovti,ox05b1s.yaml new file mode 100644 index 000000000000..9f35b4e67bea --- /dev/null +++ b/Documentation/devicetree/bindings/media/i2c/ovti,ox05b1s.yaml @@ -0,0 +1,119 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2024 NXP +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/i2c/ovti,ox05b1s.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Omnivision OX05B1S Image Sensor + +maintainers: + - Mirela Rabulea + +description: + The Omnivision OX05B1S is a 1/2.5-Inch CMOS image sensor with an active + array size of 2592 x 1944. It is programmable through I2C interface. + Image data is available via MIPI CSI-2 serial data output. + +allOf: + - $ref: /schemas/media/video-interface-devices.yaml# + +properties: + compatible: + enum: + - ovti,os08a20 + - ovti,ox05b1s + + reg: + maxItems: 1 + + clocks: + description: Input clock (24 MHz) + maxItems: 1 + + reset-gpios: + description: Active low XSHUTDOWN pin + maxItems: 1 + + avdd-supply: + description: Power for analog circuit (2.8V) + + dovdd-supply: + description: Power for I/O circuit (1.8V) + + dvdd-supply: + description: Power for digital circuit (1.2V) + + port: + $ref: /schemas/graph.yaml#/$defs/port-base + additionalProperties: false + description: MIPI CSI-2 transmitter port + + properties: + endpoint: + $ref: /schemas/media/video-interfaces.yaml# + unevaluatedProperties: false + + properties: + data-lanes: + anyOf: + - items: + - const: 1 + - const: 2 + - items: + - const: 1 + - const: 2 + - const: 3 + - const: 4 + required: + - data-lanes + + required: + - endpoint + +required: + - compatible + - reg + - clocks + - port + - avdd-supply + - dovdd-supply + - dvdd-supply + +unevaluatedProperties: false + +examples: + - | + #include + + i2c { + #address-cells =3D <1>; + #size-cells =3D <0>; + + camera@36 { + compatible =3D "ovti,ox05b1s"; + reg =3D <0x36>; + clocks =3D <&ox05b1s_clk>; + + assigned-clocks =3D <&ox05b1s_clk>; + assigned-clock-parents =3D <&ox05b1s_clk_parent>; + assigned-clock-rates =3D <24000000>; + + reset-gpios =3D <&gpio1 6 GPIO_ACTIVE_LOW>; + + avdd-supply =3D <&camera_avdd_2v8>; + dovdd-supply =3D <&camera_dovdd_1v8>; + dvdd-supply =3D <&camera_dvdd_1v2>; + + orientation =3D <2>; + rotation =3D <0>; + + port { + ox05b1s_mipi_0_ep: endpoint { + remote-endpoint =3D <&mipi_csi0_ep>; + data-lanes =3D <1 2 3 4>; + }; + }; + }; + }; +... --=20 2.25.1 From nobody Sun Feb 8 11:37:16 2026 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2063.outbound.protection.outlook.com [40.107.20.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A9C020550B; Wed, 5 Mar 2025 09:44:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Received: from AS4PR04MB9244.eurprd04.prod.outlook.com (2603:10a6:20b:4e3::9) by AM0PR04MB6945.eurprd04.prod.outlook.com (2603:10a6:208:17f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8511.17; Wed, 5 Mar 2025 09:44:27 +0000 Received: from AS4PR04MB9244.eurprd04.prod.outlook.com ([fe80::7303:2cc8:d109:d7c1]) by AS4PR04MB9244.eurprd04.prod.outlook.com ([fe80::7303:2cc8:d109:d7c1%3]) with mapi id 15.20.8511.017; Wed, 5 Mar 2025 09:44:27 +0000 From: Mirela Rabulea To: mchehab@kernel.org, sakari.ailus@linux.intel.com, hverkuil-cisco@xs4all.nl, laurent.pinchart+renesas@ideasonboard.com, robh@kernel.org, krzk+dt@kernel.org, bryan.odonoghue@linaro.org, laurentiu.palcu@nxp.com, robert.chiras@nxp.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, LnxRevLi@nxp.com, kieran.bingham@ideasonboard.com, hdegoede@redhat.com, dave.stevenson@raspberrypi.com, mike.rudenko@gmail.com, alain.volmat@foss.st.com, devicetree@vger.kernel.org, conor+dt@kernel.org, alexander.stein@ew.tq-group.com, umang.jain@ideasonboard.com, zhi.mao@mediatek.com, festevam@denx.de, julien.vuillaumier@nxp.com Subject: [PATCH v4 2/4] media: ox05b1s: Add omnivision OX05B1S raw sensor driver Date: Wed, 5 Mar 2025 11:43:57 +0200 Message-Id: <20250305094359.299895-3-mirela.rabulea@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250305094359.299895-1-mirela.rabulea@nxp.com> References: <20250305094359.299895-1-mirela.rabulea@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM9P250CA0020.EURP250.PROD.OUTLOOK.COM (2603:10a6:20b:21c::25) To AS4PR04MB9244.eurprd04.prod.outlook.com (2603:10a6:20b:4e3::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS4PR04MB9244:EE_|AM0PR04MB6945:EE_ X-MS-Office365-Filtering-Correlation-Id: 24c9f203-2f2b-4c94-0972-08dd5bca51ba X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|52116014|7416014|1800799024|376014|38350700014; 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charset="utf-8" Add a v4l2 subdevice driver for the Omnivision OX05B1S RGB-IR sensor. The Omnivision OX05B1S is a 1/2.5-Inch CMOS image sensor with an active array size of 2592 x 1944. The following features are supported for OX05B1S: - Manual exposure an gain control support - vblank/hblank control support - Supported resolution: 2592 x 1944 @ 30fps (SGRBG10) Signed-off-by: Mirela Rabulea --- Changes in v4: Switch to Y media bus codes. The CFA pattern control will be implemented w= hen patches get merged, or maybe separatelly as RFC? Add pixel_rate member to mode struct, remove fps member. We do not have in= formation how to calculate the pixel rate from the PLL parameters that can = be made public. Use register macros for the registers that are documented. User register g= roup macros, where individual registers are not documented Remove some uneeded local variable initialisations Fix extra/missing spaces Add missing ending \n Use return -ENODEV & return 0 to ease reading Rename retval to ret in probe for consistency Use devm_mutex_init instead of mutex_init Replace more dev_err's with dev_err_probe Constify more structs Remove some unneded ending commas after a terminator Fix smatch error in ox05b1s_s_ctrl: error: typename in expression Fix a seeries of smatch warnings like: warning: symbol 'ovx5b_init_setting= _2592x1944' was not declared. Should it be static? Shorten some more lines to 80 columns Changes in v3: Use helpers from v4l2-cci.h (drop ox05b1s_write_reg, ox05b1s_read_reg, ox0= 5b1s_set_hts/vts/exp/analog_gain, ox05b1s_regmap_config) Don't hardcode timing registers: remove timing registers x_output_size/y_o= utput_size from register configuration list, add them to ox05b1s_apply_curr= ent_mode Remove HTS,VTS from register config list as they are written by HBLANK and= VBLANK controls through __v4l2_ctrl_handler_setup ox05b1s register config cleaning (remove all registers that were at their = default value, and more, keep only what seems mandatory to be able to strea= m) Use const for ox05b1s_supported_modes Device should be silent on success, use dev_dbg. Drop unneeded {} Fixed an error introduced in v2 in ox05b1s_nearest_size (set_fmt for 4k BG= GR12 mode was stuck) Fix an issue in ox05b1s_set_fmt, the format was saved in subdev state only= for _TRY, save it also for _ACTIVE Changes in v2: Use dev_err_probe for missing clock, since it is now required property, an= d use NULL for devm_clk_get (no name for single clock), remove check for no= n NULL sensor->sensor_clk Remove dev_err message for devm_regmap_init_i2c allocation error Added spaces inside brackets, wrap lines to 80 Remove some redundant initializations Add regulators Make "sizes" a pointer Use struct v4l2_area instead of u32[2] array Remove the count for supported_modes[] and supported_codes[], instead use= sentinel element at the end Consequently, update ox05b1s_enum_mbus_code, ox05b1s_enum_frame_size, ox0= 5b1s_nearest_size, ox05b1s_find_code, to not use the count Remove .h files for modes, however did not move this code in the driver fi= le but added a separate c file for all supported modes Refactor register lists to allow multiple register arrays per mode Use GPL-2.0-only instead of GPL-2.0 drivers/media/i2c/Kconfig | 1 + drivers/media/i2c/Makefile | 1 + drivers/media/i2c/ox05b1s/Kconfig | 10 + drivers/media/i2c/ox05b1s/Makefile | 2 + drivers/media/i2c/ox05b1s/ox05b1s.h | 22 + drivers/media/i2c/ox05b1s/ox05b1s_mipi.c | 951 ++++++++++++++++++++++ drivers/media/i2c/ox05b1s/ox05b1s_modes.c | 77 ++ 7 files changed, 1064 insertions(+) create mode 100644 drivers/media/i2c/ox05b1s/Kconfig create mode 100644 drivers/media/i2c/ox05b1s/Makefile create mode 100644 drivers/media/i2c/ox05b1s/ox05b1s.h create mode 100644 drivers/media/i2c/ox05b1s/ox05b1s_mipi.c create mode 100644 drivers/media/i2c/ox05b1s/ox05b1s_modes.c diff --git a/drivers/media/i2c/Kconfig b/drivers/media/i2c/Kconfig index 8ba096b8ebca..5cda062c0463 100644 --- a/drivers/media/i2c/Kconfig +++ b/drivers/media/i2c/Kconfig @@ -700,6 +700,7 @@ config VIDEO_VGXY61 =20 source "drivers/media/i2c/ccs/Kconfig" source "drivers/media/i2c/et8ek8/Kconfig" +source "drivers/media/i2c/ox05b1s/Kconfig" =20 endif =20 diff --git a/drivers/media/i2c/Makefile b/drivers/media/i2c/Makefile index fbb988bd067a..028eb08e648c 100644 --- a/drivers/media/i2c/Makefile +++ b/drivers/media/i2c/Makefile @@ -114,6 +114,7 @@ obj-$(CONFIG_VIDEO_OV9282) +=3D ov9282.o obj-$(CONFIG_VIDEO_OV9640) +=3D ov9640.o obj-$(CONFIG_VIDEO_OV9650) +=3D ov9650.o obj-$(CONFIG_VIDEO_OV9734) +=3D ov9734.o +obj-$(CONFIG_VIDEO_OX05B1S) +=3D ox05b1s/ obj-$(CONFIG_VIDEO_RDACM20) +=3D rdacm20.o obj-$(CONFIG_VIDEO_RDACM21) +=3D rdacm21.o obj-$(CONFIG_VIDEO_RJ54N1) +=3D rj54n1cb0c.o diff --git a/drivers/media/i2c/ox05b1s/Kconfig b/drivers/media/i2c/ox05b1s/= Kconfig new file mode 100644 index 000000000000..48fcd04b20d5 --- /dev/null +++ b/drivers/media/i2c/ox05b1s/Kconfig @@ -0,0 +1,10 @@ +config VIDEO_OX05B1S + tristate "OmniVision raw sensor support OX05B1S" + depends on OF + depends on GPIOLIB + select REGMAP_I2C + help + This is a Video4Linux2 sensor driver for the Omnivision OX05B1S RGB-IR = sensor. + This is a 1/2.5-Inch CMOS image sensor with an active array size of 259= 2 x 1944. + It is programmable through I2C interface. + The output is on MIPI CSI-2 interface. diff --git a/drivers/media/i2c/ox05b1s/Makefile b/drivers/media/i2c/ox05b1s= /Makefile new file mode 100644 index 000000000000..0b38dbf98bcd --- /dev/null +++ b/drivers/media/i2c/ox05b1s/Makefile @@ -0,0 +1,2 @@ +ox05b1s-objs :=3D ox05b1s_modes.o ox05b1s_mipi.o +obj-$(CONFIG_VIDEO_OX05B1S) +=3D ox05b1s.o diff --git a/drivers/media/i2c/ox05b1s/ox05b1s.h b/drivers/media/i2c/ox05b1= s/ox05b1s.h new file mode 100644 index 000000000000..2a87d69864f9 --- /dev/null +++ b/drivers/media/i2c/ox05b1s/ox05b1s.h @@ -0,0 +1,22 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +/* + * Copyright (C) 2024, NXP + */ + +#ifndef OX05B1S_H +#define OX05B1S_H + +#include + +struct ox05b1s_reg { + u32 addr; + u32 data; +}; + +struct ox05b1s_reglist { + const struct ox05b1s_reg *regs; +}; + +extern const struct ox05b1s_reglist ox05b1s_reglist_2592x1944[]; + +#endif /* OX05B1S_H */ diff --git a/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c b/drivers/media/i2c/o= x05b1s/ox05b1s_mipi.c new file mode 100644 index 000000000000..1026216ddd5b --- /dev/null +++ b/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c @@ -0,0 +1,951 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * A V4L2 driver for Omnivision OX05B1S RGB-IR camera. + * Copyright (C) 2024, NXP + * + * Inspired from Sony imx219, imx290, imx214 and imx334 camera drivers + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include "ox05b1s.h" + +#define OX05B1S_SENS_PAD_SOURCE 0 +#define OX05B1S_SENS_PADS_NUM 1 + +#define OX05B1S_REG_SW_STB CCI_REG8(0x0100) +#define OX05B1S_REG_SW_RST CCI_REG8(0x0103) +#define OX05B1S_REG_CHIP_ID CCI_REG24(0x300a) +#define OX05B1S_REG_TIMING_HTS CCI_REG16(0x380c) +#define OX05B1S_REG_TIMING_VTS CCI_REG16(0x380e) +#define OX05B1S_REG_EXPOSURE CCI_REG16(0x3501) +#define OX05B1S_REG_GAIN CCI_REG16(0x3508) +#define OX05B1S_REG_X_OUTPUT_SIZE CCI_REG16(0x3808) +#define OX05B1S_REG_Y_OUTPUT_SIZE CCI_REG16(0x380a) + +#define client_to_ox05b1s(client)\ + container_of(i2c_get_clientdata(client), struct ox05b1s, subdev) + +struct ox05b1s_sizes { + u32 code; + const struct v4l2_area *sizes; +}; + +struct ox05b1s_plat_data { + char name[20]; + u32 chip_id; + u32 native_width; + u32 native_height; + u32 active_top; + u32 active_left; + u32 active_width; + u32 active_height; + const struct ox05b1s_mode *supported_modes; + u32 default_mode_index; + const struct ox05b1s_sizes *supported_codes; +}; + +struct ox05b1s_ctrls { + struct v4l2_ctrl_handler handler; + struct v4l2_ctrl *link_freq; + struct v4l2_ctrl *pixel_rate; + struct v4l2_ctrl *hblank; + struct v4l2_ctrl *vblank; + struct v4l2_ctrl *gain; + struct v4l2_ctrl *exposure; +}; + +struct ox05b1s_mode { + u32 index; + u32 width; + u32 height; + u32 code; + u32 bpp; + u32 vts; /* default VTS */ + u32 hts; /* default HTS */ + u32 exp; /* max exposure */ + bool h_bin; /* horizontal binning */ + s64 pixel_rate; + const struct ox05b1s_reglist *reg_data; +}; + +/* regulator supplies */ +static const char * const ox05b1s_supply_name[] =3D { + "AVDD", /* Analog voltage supply, 2.8 volts */ + "DVDD", /* Digital I/O voltage supply, 1.8 volts */ + "DOVDD", /* Digital voltage supply, 1.2 volts */ +}; + +#define OX05B1S_NUM_SUPPLIES ARRAY_SIZE(ox05b1s_supply_name) + +struct ox05b1s { + struct i2c_client *i2c_client; + struct regmap *regmap; + struct gpio_desc *rst_gpio; + struct regulator_bulk_data supplies[OX05B1S_NUM_SUPPLIES]; + struct clk *sensor_clk; + const struct ox05b1s_plat_data *model; + struct v4l2_subdev subdev; + struct media_pad pads[OX05B1S_SENS_PADS_NUM]; + const struct ox05b1s_mode *mode; + struct mutex lock; /* sensor lock */ + u32 stream_status; + struct ox05b1s_ctrls ctrls; +}; + +#define OX05B1S_PIXEL_RATE_48M 48000000 +static const struct ox05b1s_mode ox05b1s_supported_modes[] =3D { + { + /* 5Mp GRBG10, 30fps */ + .index =3D 0, + .width =3D 2592, + .height =3D 1944, + .code =3D MEDIA_BUS_FMT_Y10_1X10, + .bpp =3D 10, + .vts =3D 0x850, + .hts =3D 0x2f0, + .exp =3D 0x850 - 8, + .h_bin =3D false, + .pixel_rate =3D OX05B1S_PIXEL_RATE_48M, + .reg_data =3D ox05b1s_reglist_2592x1944, + }, { + /* sentinel */ + } +}; + +/* keep in sync with ox05b1s_supported_modes */ +static const struct v4l2_area ox05b1s_sgrbg10_sizes[] =3D { + { + .width =3D 2592, + .height =3D 1944, + }, { + /* sentinel */ + } +}; + +static const struct ox05b1s_sizes ox05b1s_supported_codes[] =3D { + { + .code =3D MEDIA_BUS_FMT_Y10_1X10, + .sizes =3D ox05b1s_sgrbg10_sizes, + }, { + /* sentinel */ + } +}; + +static int ox05b1s_power_on(struct ox05b1s *sensor) +{ + struct device *dev =3D &sensor->i2c_client->dev; + int ret; + + ret =3D regulator_bulk_enable(OX05B1S_NUM_SUPPLIES, sensor->supplies); + if (ret) { + dev_err(dev, "Failed to enable regulators\n"); + return ret; + } + + /* get out of powerdown and reset */ + gpiod_set_value_cansleep(sensor->rst_gpio, 0); + + ret =3D clk_prepare_enable(sensor->sensor_clk); + if (ret < 0) { + dev_err(dev, "Enable sensor clk fail ret=3D%d\n", ret); + goto reg_off; + } + + /* with XVCLK@24MHz, t2 =3D 6ms before first ox05b1s SCCB transaction */ + fsleep(6000); + + return 0; + +reg_off: + regulator_bulk_disable(OX05B1S_NUM_SUPPLIES, sensor->supplies); + + return ret; +} + +static int ox05b1s_power_off(struct ox05b1s *sensor) +{ + gpiod_set_value_cansleep(sensor->rst_gpio, 1); + + /* XVCLK must be active for 512 cycles after last SCCB transaction */ + fsleep(350); /* 512 cycles =3D 0.34 ms at 24MHz */ + clk_disable_unprepare(sensor->sensor_clk); + + regulator_bulk_disable(OX05B1S_NUM_SUPPLIES, sensor->supplies); + + return 0; +} + +static int ox05b1s_runtime_suspend(struct device *dev) +{ + struct v4l2_subdev *sd =3D dev_get_drvdata(dev); + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + + return ox05b1s_power_off(sensor); +} + +static int ox05b1s_runtime_resume(struct device *dev) +{ + struct v4l2_subdev *sd =3D dev_get_drvdata(dev); + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + + return ox05b1s_power_on(sensor); +} + +#define OX05B1S_MAX_REG_BULK 16 +static int ox05b1s_write_reg_array(struct ox05b1s *sensor, + const struct ox05b1s_reg *reg_array) +{ + struct device *dev =3D &sensor->i2c_client->dev; + const struct ox05b1s_reg *table =3D reg_array; + u8 vals[OX05B1S_MAX_REG_BULK]; + int i; + int ret; + + while (table->addr) { + for (i =3D 0; i < OX05B1S_MAX_REG_BULK; i++) { + if (table[i].addr !=3D (table[0].addr + i)) + break; + vals[i] =3D table[i].data; + } + ret =3D regmap_bulk_write(sensor->regmap, table->addr, vals, i); + if (ret) { + dev_err(dev, "Failed to write reg addr=3D%x, count %d\n", + table->addr, i); + return ret; + } + table +=3D i; + } + + return 0; +} + +static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) +{ + return &container_of(ctrl->handler, struct ox05b1s, + ctrls.handler)->subdev; +} + +static int ox05b1s_s_ctrl(struct v4l2_ctrl *ctrl) +{ + struct v4l2_subdev *sd =3D ctrl_to_sd(ctrl); + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + u32 w =3D sensor->mode->width; + u32 h =3D sensor->mode->height; + int ret =3D 0; + u32 hts; + + /* apply V4L2 controls values only if power is already up */ + if (!pm_runtime_get_if_in_use(&client->dev)) + return 0; + + /* s_ctrl holds sensor lock */ + switch (ctrl->id) { + case V4L2_CID_VBLANK: + ret =3D cci_write(sensor->regmap, OX05B1S_REG_TIMING_VTS, + h + ctrl->val, NULL); + break; + case V4L2_CID_HBLANK: + hts =3D (sensor->mode->h_bin) ? + w + ctrl->val : (w + ctrl->val) / 2; + ret =3D cci_write(sensor->regmap, OX05B1S_REG_TIMING_HTS, + hts, NULL); + break; + case V4L2_CID_PIXEL_RATE: + /* Read-only, but we adjust it based on mode. */ + break; + case V4L2_CID_ANALOGUE_GAIN: + ret =3D cci_write(sensor->regmap, OX05B1S_REG_GAIN, + ctrl->val, NULL); + break; + case V4L2_CID_EXPOSURE: + ret =3D cci_write(sensor->regmap, OX05B1S_REG_EXPOSURE, + ctrl->val, NULL); + break; + default: + ret =3D -EINVAL; + break; + } + + pm_runtime_put(&client->dev); + + return ret; +} + +static const struct v4l2_ctrl_ops ox05b1s_ctrl_ops =3D { + .s_ctrl =3D ox05b1s_s_ctrl, +}; + +/* + * MIPI CSI-2 link frequencies. + * link_freq =3D (pixel_rate * bpp) / (2 * data_lanes) + */ +static const s64 ox05b1s_csi2_link_freqs[] =3D { + 200000000 +}; + +/* Link freq for default mode: 1080p RAW10, 4 data lanes 800 Mbps/lane. */ +#define OX05B1S_DEFAULT_LINK_FREQ 0 + +static int ox05b1s_init_controls(struct ox05b1s *sensor) +{ + const struct v4l2_ctrl_ops *ops =3D &ox05b1s_ctrl_ops; + struct ox05b1s_ctrls *ctrls =3D &sensor->ctrls; + struct v4l2_ctrl_handler *hdl =3D &ctrls->handler; + struct device *dev =3D &sensor->i2c_client->dev; + struct v4l2_fwnode_device_properties props; + int ret; + + v4l2_ctrl_handler_init(hdl, 7); + + /* we can use our own mutex for the ctrl lock */ + hdl->lock =3D &sensor->lock; + + /* Clock related controls */ + ctrls->link_freq =3D v4l2_ctrl_new_int_menu(hdl, ops, + V4L2_CID_LINK_FREQ, + ARRAY_SIZE(ox05b1s_csi2_link_freqs) - 1, + OX05B1S_DEFAULT_LINK_FREQ, + ox05b1s_csi2_link_freqs); + + /* mode dependent, actual range set in ox05b1s_update_controls */ + ctrls->pixel_rate =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_PIXEL_RATE, + 0, 0, 1, 0); + + ctrls->hblank =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_HBLANK, + 0, 0, 1, 0); + + ctrls->vblank =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_VBLANK, + 0, 0, 1, 0); + + ctrls->exposure =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_EXPOSURE, + 0, 0, 1, 0); + + ctrls->gain =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN, + 0, 0xFFFF, 1, 0x80); + + if (hdl->error) { + ret =3D hdl->error; + goto free_ctrls; + } + + ctrls->link_freq->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; + ctrls->pixel_rate->flags |=3D V4L2_CTRL_FLAG_READ_ONLY; + + ret =3D v4l2_fwnode_device_parse(dev, &props); + if (ret) + goto free_ctrls; + + ret =3D v4l2_ctrl_new_fwnode_properties(hdl, ops, &props); + if (ret) + goto free_ctrls; + + sensor->subdev.ctrl_handler =3D hdl; + return 0; + +free_ctrls: + dev_err(dev, "Failed to init controls\n"); + v4l2_ctrl_handler_free(hdl); + return ret; +} + +static int ox05b1s_apply_current_mode(struct ox05b1s *sensor); + +static int ox05b1s_s_stream(struct v4l2_subdev *sd, int enable) +{ + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + int ret; + + if (enable) { + ret =3D pm_runtime_resume_and_get(&client->dev); + if (ret < 0) + return ret; + ret =3D ox05b1s_apply_current_mode(sensor); + if (!ret) + ret =3D cci_write(sensor->regmap, OX05B1S_REG_SW_STB, + 0x01, NULL); + } else { + ret =3D cci_write(sensor->regmap, OX05B1S_REG_SW_STB, 0x00, NULL); + } + + sensor->stream_status =3D enable; + + if (!enable || ret) { + pm_runtime_mark_last_busy(&sensor->i2c_client->dev); + pm_runtime_put_autosuspend(&client->dev); + } + + return 0; +} + +static void ox05b1s_update_pad_format(struct ox05b1s *sensor, + const struct ox05b1s_mode *mode, + struct v4l2_mbus_framefmt *fmt) +{ + fmt->code =3D mode->code; + fmt->width =3D mode->width; + fmt->height =3D mode->height; + fmt->field =3D V4L2_FIELD_NONE; + fmt->colorspace =3D V4L2_COLORSPACE_RAW; + fmt->quantization =3D V4L2_QUANTIZATION_FULL_RANGE; + fmt->xfer_func =3D V4L2_XFER_FUNC_NONE; +} + +static int ox05b1s_init_state(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state) +{ + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + struct v4l2_mbus_framefmt *format; + + /* Initialize the format. */ + format =3D v4l2_subdev_state_get_format(state, 0); + ox05b1s_update_pad_format(sensor, &sensor->model->supported_modes[0], + format); + + return 0; +} + +static int ox05b1s_enum_mbus_code(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_mbus_code_enum *code) +{ + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + const struct ox05b1s_sizes *supported_codes =3D sensor->model->supported_= codes; + int i =3D 0; + + while (i++ < code->index && supported_codes->code) + supported_codes++; + if (!supported_codes->code) /* code->index outside supported_codes[] */ + return -EINVAL; + + code->code =3D supported_codes->code; + + return 0; +} + +static int ox05b1s_enum_frame_size(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_frame_size_enum *fse) +{ + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + const struct ox05b1s_sizes *supported_codes =3D sensor->model->supported_= codes; + const struct v4l2_area *sizes; + int i =3D 0; + + if (fse->pad !=3D 0) + return -EINVAL; + + while (supported_codes->code) { + if (supported_codes->code =3D=3D fse->code) + break; + supported_codes++; + } + + if (!supported_codes->code) /* fse->code not in supported_codes[] */ + return -EINVAL; + + sizes =3D supported_codes->sizes; + while (i++ < fse->index && sizes->width) + sizes++; + if (!sizes->width) /* fse->index outside sizes[] */ + return -EINVAL; + + fse->min_width =3D sizes->width; + fse->max_width =3D fse->min_width; + fse->min_height =3D sizes->height; + fse->max_height =3D fse->min_height; + + return 0; +} + +/* Update control ranges based on current streaming mode, needs sensor loc= k */ +static int ox05b1s_update_controls(struct ox05b1s *sensor) +{ + int ret; + struct device *dev =3D &sensor->i2c_client->dev; + u32 hts =3D sensor->mode->hts; + u32 hblank; + u32 vts =3D sensor->mode->vts; + u32 vblank =3D vts - sensor->mode->height; + u64 pixel_rate =3D sensor->mode->pixel_rate; + u32 min_exp =3D 8; + u32 max_exp =3D vts - 8; + + ret =3D __v4l2_ctrl_modify_range(sensor->ctrls.pixel_rate, pixel_rate, + pixel_rate, 1, pixel_rate); + if (ret) { + dev_err(dev, "Modify range for pixel_rate %llu-%llu failed\n", + pixel_rate, pixel_rate); + goto out; + } + + if (sensor->mode->h_bin) + hblank =3D hts - sensor->mode->width; + else + hblank =3D 2 * hts - sensor->mode->width; + + ret =3D __v4l2_ctrl_modify_range(sensor->ctrls.hblank, hblank, hblank, + 1, hblank); + if (ret) { + dev_err(dev, "Modify range for hblank %u-%u failed\n", + hblank, hblank); + goto out; + } + __v4l2_ctrl_s_ctrl(sensor->ctrls.hblank, + sensor->ctrls.hblank->default_value); + + ret =3D __v4l2_ctrl_modify_range(sensor->ctrls.vblank, 0, vblank * 4, + 1, vblank); + if (ret) { + dev_err(dev, "Modify range for vblank %u-%u failed\n", + vblank, vblank); + goto out; + } + __v4l2_ctrl_s_ctrl(sensor->ctrls.vblank, + sensor->ctrls.vblank->default_value); + + ret =3D __v4l2_ctrl_modify_range(sensor->ctrls.exposure, min_exp, max_exp, + 1, max_exp / 2); + if (ret) { + dev_err(dev, "Modify range for exposure %u-%u failed\n", + min_exp, max_exp); + goto out; + } + __v4l2_ctrl_s_ctrl(sensor->ctrls.exposure, + sensor->ctrls.exposure->default_value); + +out: + return ret; +} + +/* needs sensor lock and power on */ +static int ox05b1s_apply_current_mode(struct ox05b1s *sensor) +{ + struct device *dev =3D &sensor->i2c_client->dev; + const struct ox05b1s_reglist *reg_data =3D sensor->mode->reg_data; + u32 w =3D sensor->mode->width; + u32 h =3D sensor->mode->height; + int ret; + + cci_write(sensor->regmap, OX05B1S_REG_SW_RST, 0x01, &ret); + + while (reg_data->regs) { + ret =3D ox05b1s_write_reg_array(sensor, reg_data->regs); + if (ret) + goto out; + reg_data++; + } + + cci_write(sensor->regmap, OX05B1S_REG_X_OUTPUT_SIZE, w, &ret); + cci_write(sensor->regmap, OX05B1S_REG_Y_OUTPUT_SIZE, h, &ret); + if (ret) + goto out; + + /* setup handler will write actual controls into sensor registers */ + ret =3D __v4l2_ctrl_handler_setup(&sensor->ctrls.handler); + +out: + if (ret < 0) + dev_err(dev, "Failed to apply mode %dx%d,bpp=3D%d\n", w, h, + sensor->mode->bpp); + + return ret; +} + +/* similar with v4l2_find_nearest_size but filter for mbus code, needs sen= sor lock */ +static const struct ox05b1s_mode *ox05b1s_nearest_size(const struct ox05b1= s_mode *supported_modes, + struct v4l2_subdev_format *fmt) +{ + u32 err, min_error =3D U32_MAX; + const struct ox05b1s_mode *best =3D NULL; + + if (!supported_modes) + return NULL; + + for (; supported_modes->width; supported_modes++) { + const u32 w =3D supported_modes->width; + const u32 h =3D supported_modes->height; + + if (supported_modes->code !=3D fmt->format.code) + continue; + + err =3D abs(w - fmt->format.width) + abs(h - fmt->format.height); + if (err > min_error) + continue; + + min_error =3D err; + best =3D supported_modes; + if (!err) + break; + } + + return best; +} + +/* get a valid mbus code, either the requested one or the default one */ +static u32 ox05b1s_find_code(const struct ox05b1s_plat_data *model, u32 co= de) +{ + u32 found_code =3D 0; + const struct ox05b1s_sizes *supported_codes =3D model->supported_codes; + + while (supported_codes->code) { + if (supported_codes->code =3D=3D code) { + found_code =3D code; + break; + } + supported_codes++; + } + + if (!supported_codes->code) /* code not in supported_codes[] */ + found_code =3D supported_codes[model->default_mode_index].code; + + return found_code; +} + +static int ox05b1s_set_fmt(struct v4l2_subdev *sd, + struct v4l2_subdev_state *state, + struct v4l2_subdev_format *fmt) +{ + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + struct device *dev =3D &sensor->i2c_client->dev; + struct v4l2_mbus_framefmt *format; + const struct ox05b1s_mode *mode; + + /* if no matching mbus code found, use the one from the default mode */ + fmt->format.code =3D ox05b1s_find_code(sensor->model, fmt->format.code); + mode =3D ox05b1s_nearest_size(sensor->model->supported_modes, fmt); + + fmt->format.width =3D mode->width; + fmt->format.height =3D mode->height; + fmt->format.field =3D V4L2_FIELD_NONE; + + format =3D v4l2_subdev_state_get_format(state, 0); + *format =3D fmt->format; + if (fmt->which =3D=3D V4L2_SUBDEV_FORMAT_TRY) + return 0; + + sensor->mode =3D mode; + + /* update controls that depend on current mode */ + ox05b1s_update_controls(sensor); + + dev_dbg(dev, "Set mode index=3D%d, %d x %d, code=3D0x%x\n", + sensor->mode->index, + fmt->format.width, fmt->format.height, fmt->format.code); + + return 0; +} + +static u8 ox05b1s_code2dt(const u32 code) +{ + switch (code) { + case MEDIA_BUS_FMT_Y10_1X10: + return MIPI_CSI2_DT_RAW10; + default: + return MIPI_CSI2_DT_RAW10; + } +} + +static int ox05b1s_get_frame_desc(struct v4l2_subdev *sd, unsigned int pad, + struct v4l2_mbus_frame_desc *fd) +{ + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + + fd->type =3D V4L2_MBUS_FRAME_DESC_TYPE_CSI2; + fd->num_entries =3D 1; + + /* get sensor current code */ + mutex_lock(&sensor->lock); + fd->entry[0].pixelcode =3D sensor->mode->code; + mutex_unlock(&sensor->lock); + + fd->entry[0].bus.csi2.vc =3D 0; + fd->entry[0].bus.csi2.dt =3D ox05b1s_code2dt(fd->entry[0].pixelcode); + + return 0; +} + +static int ox05b1s_get_selection(struct v4l2_subdev *sd, + struct v4l2_subdev_state *sd_state, + struct v4l2_subdev_selection *sel) +{ + struct i2c_client *client =3D v4l2_get_subdevdata(sd); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + + switch (sel->target) { + case V4L2_SEL_TGT_NATIVE_SIZE: + case V4L2_SEL_TGT_CROP_BOUNDS: + sel->r.top =3D 0; + sel->r.left =3D 0; + sel->r.width =3D sensor->model->native_width; + sel->r.height =3D sensor->model->native_height; + return 0; + case V4L2_SEL_TGT_CROP: + case V4L2_SEL_TGT_CROP_DEFAULT: + sel->r.top =3D sensor->model->active_top; + sel->r.left =3D sensor->model->active_left; + sel->r.width =3D sensor->model->active_width; + sel->r.height =3D sensor->model->active_height; + return 0; + } + + return -EINVAL; +} + +static const struct v4l2_subdev_video_ops ox05b1s_subdev_video_ops =3D { + .s_stream =3D ox05b1s_s_stream +}; + +static const struct v4l2_subdev_pad_ops ox05b1s_subdev_pad_ops =3D { + .set_fmt =3D ox05b1s_set_fmt, + .get_fmt =3D v4l2_subdev_get_fmt, + .get_frame_desc =3D ox05b1s_get_frame_desc, + .enum_mbus_code =3D ox05b1s_enum_mbus_code, + .enum_frame_size =3D ox05b1s_enum_frame_size, + .get_selection =3D ox05b1s_get_selection +}; + +static const struct v4l2_subdev_ops ox05b1s_subdev_ops =3D { + .video =3D &ox05b1s_subdev_video_ops, + .pad =3D &ox05b1s_subdev_pad_ops +}; + +static const struct v4l2_subdev_internal_ops ox05b1s_internal_ops =3D { + .init_state =3D ox05b1s_init_state +}; + +static void ox05b1s_get_gpios(struct ox05b1s *sensor) +{ + struct device *dev =3D &sensor->i2c_client->dev; + + sensor->rst_gpio =3D devm_gpiod_get_optional(dev, "reset", + GPIOD_OUT_HIGH); + if (IS_ERR(sensor->rst_gpio)) + dev_warn(dev, "No sensor reset pin available\n"); +} + +static int ox05b1s_get_regulators(struct ox05b1s *sensor) +{ + struct device *dev =3D &sensor->i2c_client->dev; + unsigned int i; + + for (i =3D 0; i < OX05B1S_NUM_SUPPLIES; i++) + sensor->supplies[i].supply =3D ox05b1s_supply_name[i]; + + return devm_regulator_bulk_get(dev, OX05B1S_NUM_SUPPLIES, + sensor->supplies); +} + +static int ox05b1s_read_chip_id(struct ox05b1s *sensor) +{ + struct device *dev =3D &sensor->i2c_client->dev; + u64 chip_id; + char *camera_name; + int ret; + + ret =3D cci_read(sensor->regmap, OX05B1S_REG_CHIP_ID, &chip_id, NULL); + if (ret) { + dev_err(dev, "Camera chip_id read error\n"); + return -ENODEV; + } + + switch (chip_id) { + case 0x580542: + camera_name =3D "ox05b1s"; + break; + default: + camera_name =3D "unknown"; + break; + } + + if (chip_id =3D=3D sensor->model->chip_id) { + dev_dbg(dev, "Camera %s detected, chip_id=3D%llx\n", + camera_name, chip_id); + } else { + dev_err(dev, "Detected %s camera (chip_id=3D%llx), but expected %s (chip= _id=3D%x)\n", + camera_name, chip_id, + sensor->model->name, sensor->model->chip_id); + return -ENODEV; + } + + return 0; +} + +static int ox05b1s_probe(struct i2c_client *client) +{ + int ret; + struct device *dev =3D &client->dev; + struct v4l2_subdev *sd; + struct ox05b1s *sensor; + + sensor =3D devm_kzalloc(dev, sizeof(*sensor), GFP_KERNEL); + if (!sensor) + return -ENOMEM; + + sensor->regmap =3D devm_cci_regmap_init_i2c(client, 16); + if (IS_ERR(sensor->regmap)) + return PTR_ERR(sensor->regmap); + + sensor->i2c_client =3D client; + + sensor->model =3D of_device_get_match_data(dev); + + ox05b1s_get_gpios(sensor); + + /* Get system clock, xvclk */ + sensor->sensor_clk =3D devm_clk_get(dev, NULL); + if (IS_ERR(sensor->sensor_clk)) + return dev_err_probe(dev, PTR_ERR(sensor->sensor_clk), + "Failed to get xvclk\n"); + + ret =3D ox05b1s_get_regulators(sensor); + if (ret) + return dev_err_probe(dev, ret, "Failed to get regulators\n"); + + sd =3D &sensor->subdev; + v4l2_i2c_subdev_init(sd, client, &ox05b1s_subdev_ops); + sd->internal_ops =3D &ox05b1s_internal_ops; + sd->flags |=3D V4L2_SUBDEV_FL_HAS_DEVNODE; + sd->dev =3D &client->dev; + sd->entity.function =3D MEDIA_ENT_F_CAM_SENSOR; + sensor->pads[OX05B1S_SENS_PAD_SOURCE].flags =3D MEDIA_PAD_FL_SOURCE; + ret =3D media_entity_pads_init(&sd->entity, OX05B1S_SENS_PADS_NUM, + sensor->pads); + if (ret) + goto probe_out; + + devm_mutex_init(dev, &sensor->lock); + + ret =3D ox05b1s_init_controls(sensor); + if (ret) + goto probe_err_entity_cleanup; + + /* power on manually */ + ret =3D ox05b1s_power_on(sensor); + if (ret) { + dev_err_probe(dev, ret, "Failed to power on\n"); + goto probe_err_free_ctrls; + } + + pm_runtime_set_active(dev); + pm_runtime_get_noresume(dev); + pm_runtime_enable(dev); + + ret =3D ox05b1s_read_chip_id(sensor); + if (ret) + goto probe_err_pm_runtime; + + v4l2_i2c_subdev_set_name(sd, client, sensor->model->name, NULL); + + /* Centrally managed subdev active state */ + sd->state_lock =3D &sensor->lock; + ret =3D v4l2_subdev_init_finalize(sd); + if (ret < 0) { + dev_err_probe(dev, ret, "Subdev init error: %d\n", ret); + goto probe_err_pm_runtime; + } + + ret =3D v4l2_async_register_subdev_sensor(sd); + if (ret < 0) { + dev_err_probe(&client->dev, ret, + "Async register failed, ret=3D%d\n", ret); + goto probe_err_subdev_cleanup; + } + + sensor->mode =3D &sensor->model->supported_modes[0]; + ox05b1s_update_controls(sensor); + + pm_runtime_set_autosuspend_delay(dev, 1000); + pm_runtime_use_autosuspend(dev); + pm_runtime_put_autosuspend(dev); + + return 0; + +probe_err_subdev_cleanup: + v4l2_subdev_cleanup(sd); +probe_err_pm_runtime: + pm_runtime_put_noidle(dev); + pm_runtime_disable(dev); + ox05b1s_runtime_suspend(dev); +probe_err_free_ctrls: + v4l2_ctrl_handler_free(&sensor->ctrls.handler); +probe_err_entity_cleanup: + media_entity_cleanup(&sd->entity); +probe_out: + return ret; +} + +static void ox05b1s_remove(struct i2c_client *client) +{ + struct v4l2_subdev *sd =3D i2c_get_clientdata(client); + struct ox05b1s *sensor =3D client_to_ox05b1s(client); + struct device *dev =3D &client->dev; + + pm_runtime_disable(dev); + if (!pm_runtime_status_suspended(dev)) + ox05b1s_runtime_suspend(dev); + pm_runtime_set_suspended(dev); + v4l2_async_unregister_subdev(sd); + v4l2_subdev_cleanup(sd); + media_entity_cleanup(&sd->entity); + v4l2_ctrl_handler_free(&sensor->ctrls.handler); +} + +static DEFINE_RUNTIME_DEV_PM_OPS(ox05b1s_pm_ops, ox05b1s_runtime_suspend, + ox05b1s_runtime_resume, NULL); + +static const struct ox05b1s_plat_data ox05b1s_data =3D { + .name =3D "ox05b1s", + .chip_id =3D 0x580542, + .native_width =3D 2608, /* 8 dummy + 2592 active + 8 dummy */ + .native_height =3D 1960, /* 8 dummy + 1944 active + 8 dummy */ + .active_top =3D 8, + .active_left =3D 8, + .active_width =3D 2592, + .active_height =3D 1944, + .supported_modes =3D ox05b1s_supported_modes, + .default_mode_index =3D 0, + .supported_codes =3D ox05b1s_supported_codes +}; + +static const struct of_device_id ox05b1s_of_match[] =3D { + { + .compatible =3D "ovti,ox05b1s", + .data =3D &ox05b1s_data, + }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, ox05b1s_of_match); + +static struct i2c_driver ox05b1s_i2c_driver =3D { + .driver =3D { + .name =3D "ox05b1s", + .pm =3D pm_ptr(&ox05b1s_pm_ops), + .of_match_table =3D ox05b1s_of_match, + }, + .probe =3D ox05b1s_probe, + .remove =3D ox05b1s_remove +}; + +module_i2c_driver(ox05b1s_i2c_driver); +MODULE_DESCRIPTION("Omnivision OX05B1S MIPI Camera Subdev Driver"); +MODULE_AUTHOR("Mirela Rabulea "); +MODULE_LICENSE("GPL"); diff --git a/drivers/media/i2c/ox05b1s/ox05b1s_modes.c b/drivers/media/i2c/= ox05b1s/ox05b1s_modes.c new file mode 100644 index 000000000000..9a1f3a89077c --- /dev/null +++ b/drivers/media/i2c/ox05b1s/ox05b1s_modes.c @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Register configurations for all sensor supported modes + * Copyright (C) 2024, NXP + * Copyright (C) 2024, Omnivision + * Copyright (C) 2024, Verisilicon + * + */ + +#include +#include "ox05b1s.h" + +#define OX05B1S_REG_PLL1_CTRL_REG07 CCI_REG8(0x0307) +#define OX05B1S_REG_PLL3_CTRL_REG4A CCI_REG8(0x034a) +#define OX05B1S_REG_PLL_MONITOR_REG0B CCI_REG8(0x040b) +#define OX05B1S_REG_PLL_MONITOR_REG0C CCI_REG8(0x040c) +#define OX05B1S_REG_SC_CMMN_REG09 CCI_REG8(0x3009) +#define OX05B1S_REG_GROUP_HLD_REG19 CCI_REG8(0x3219) +#define OX05B1S_REG_ANA_REG CCI_REG8(0x3600) +#define OX05B1S_REG_SENSOR_CTRL02 CCI_REG8(0x3702) +#define OX05B1S_REG_TIMING_CTRL CCI_REG8(0x3800) +#define OX05B1S_REG_MIPI_CORE_REG02 CCI_REG8(0x4802) +#define OX05B1S_REG_MIPI_CORE_REG1B CCI_REG8(0x481b) +#define OX05B1S_REG_PCLK_PERIOD CCI_REG8(0x4837) + +/* + * Register configuration for Omnivision OX05B1S raw camera + * 2592X1944_30FPS_FULL_RGBIr 2592 1944 + */ +static const struct ox05b1s_reg ovx5b_init_setting_2592x1944[] =3D { + { 0x0107, 0x01 }, /* Reserved */ + { OX05B1S_REG_PLL1_CTRL_REG07, 0x02 }, + { OX05B1S_REG_PLL3_CTRL_REG4A, 0x05 }, + { OX05B1S_REG_PLL_MONITOR_REG0B, 0x5c }, + { OX05B1S_REG_PLL_MONITOR_REG0C, 0xcd }, + { OX05B1S_REG_SC_CMMN_REG09, 0x2e }, + { OX05B1S_REG_GROUP_HLD_REG19, 0x08 }, + { OX05B1S_REG_ANA_REG + 0x84, 0x6d }, + { OX05B1S_REG_ANA_REG + 0x85, 0x6d }, + { OX05B1S_REG_ANA_REG + 0x86, 0x6d }, + { OX05B1S_REG_ANA_REG + 0x87, 0x6d }, + { OX05B1S_REG_ANA_REG + 0x8c, 0x07 }, + { OX05B1S_REG_ANA_REG + 0x8d, 0x07 }, + { OX05B1S_REG_ANA_REG + 0x8e, 0x07 }, + { OX05B1S_REG_ANA_REG + 0x8f, 0x00 }, + { OX05B1S_REG_ANA_REG + 0x90, 0x04 }, + { OX05B1S_REG_ANA_REG + 0x91, 0x04 }, + { OX05B1S_REG_ANA_REG + 0x92, 0x04 }, + { OX05B1S_REG_ANA_REG + 0x93, 0x04 }, + { OX05B1S_REG_ANA_REG + 0x98, 0x00 }, + { OX05B1S_REG_ANA_REG + 0xa0, 0x05 }, + { OX05B1S_REG_ANA_REG + 0xa2, 0x16 }, + { OX05B1S_REG_ANA_REG + 0xa3, 0x03 }, + { OX05B1S_REG_ANA_REG + 0xa4, 0x07 }, + { OX05B1S_REG_ANA_REG + 0xa5, 0x24 }, + { OX05B1S_REG_ANA_REG + 0xe3, 0x09 }, + { OX05B1S_REG_SENSOR_CTRL02, 0x0a }, + { OX05B1S_REG_TIMING_CTRL + 0x21, 0x04 }, /* mirror */ + { OX05B1S_REG_TIMING_CTRL + 0x22, 0x10 }, + { OX05B1S_REG_TIMING_CTRL + 0x2b, 0x03 }, + { OX05B1S_REG_TIMING_CTRL + 0x66, 0x10 }, + { OX05B1S_REG_TIMING_CTRL + 0x6c, 0x46 }, + { OX05B1S_REG_TIMING_CTRL + 0x6d, 0x08 }, + { OX05B1S_REG_TIMING_CTRL + 0x6e, 0x7b }, + { OX05B1S_REG_MIPI_CORE_REG02, 0x00 }, + { OX05B1S_REG_MIPI_CORE_REG1B, 0x3c }, + { OX05B1S_REG_PCLK_PERIOD, 0x19 }, + { /* sentinel*/ } +}; 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charset="utf-8" Add maintainer for Omnivision OX05B1S sensor driver. Signed-off-by: Mirela Rabulea --- Changes in v4: None Changes in v3: None Changes in v2: None MAINTAINERS | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/MAINTAINERS b/MAINTAINERS index 3c10a18fac78..a9d0fa44403a 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -17635,6 +17635,16 @@ S: Maintained T: git git://linuxtv.org/media.git F: drivers/media/i2c/ov9734.c =20 +OMNIVISION OX05B1S SENSOR DRIVER +M: Mirela Rabulea +R: Laurentiu Palcu +R: Robert Chiras +L: linux-media@vger.kernel.org +S: Maintained +T: git git://linuxtv.org/media_tree.git +F: Documentation/devicetree/bindings/media/i2c/ovti,ox05b1s.yaml +F: drivers/media/i2c/ox05b1s/* + ONBOARD USB HUB DRIVER M: Matthias Kaehlcke L: linux-usb@vger.kernel.org --=20 2.25.1 From nobody Sun Feb 8 11:37:16 2026 Received: from EUR05-DB8-obe.outbound.protection.outlook.com (mail-db8eur05on2063.outbound.protection.outlook.com [40.107.20.63]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C7C27205E37; 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Received: from AS4PR04MB9244.eurprd04.prod.outlook.com (2603:10a6:20b:4e3::9) by AM0PR04MB6945.eurprd04.prod.outlook.com (2603:10a6:208:17f::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.8511.17; Wed, 5 Mar 2025 09:44:31 +0000 Received: from AS4PR04MB9244.eurprd04.prod.outlook.com ([fe80::7303:2cc8:d109:d7c1]) by AS4PR04MB9244.eurprd04.prod.outlook.com ([fe80::7303:2cc8:d109:d7c1%3]) with mapi id 15.20.8511.017; Wed, 5 Mar 2025 09:44:31 +0000 From: Mirela Rabulea To: mchehab@kernel.org, sakari.ailus@linux.intel.com, hverkuil-cisco@xs4all.nl, laurent.pinchart+renesas@ideasonboard.com, robh@kernel.org, krzk+dt@kernel.org, bryan.odonoghue@linaro.org, laurentiu.palcu@nxp.com, robert.chiras@nxp.com Cc: linux-media@vger.kernel.org, linux-kernel@vger.kernel.org, LnxRevLi@nxp.com, kieran.bingham@ideasonboard.com, hdegoede@redhat.com, dave.stevenson@raspberrypi.com, mike.rudenko@gmail.com, alain.volmat@foss.st.com, devicetree@vger.kernel.org, conor+dt@kernel.org, alexander.stein@ew.tq-group.com, umang.jain@ideasonboard.com, zhi.mao@mediatek.com, festevam@denx.de, julien.vuillaumier@nxp.com Subject: [PATCH v4 4/4] media: ox05b1s: Add support for Omnivision OS08A20 raw sensor Date: Wed, 5 Mar 2025 11:43:59 +0200 Message-Id: <20250305094359.299895-5-mirela.rabulea@nxp.com> X-Mailer: git-send-email 2.25.1 In-Reply-To: <20250305094359.299895-1-mirela.rabulea@nxp.com> References: <20250305094359.299895-1-mirela.rabulea@nxp.com> Content-Transfer-Encoding: quoted-printable X-ClientProxiedBy: AM9P250CA0020.EURP250.PROD.OUTLOOK.COM (2603:10a6:20b:21c::25) To AS4PR04MB9244.eurprd04.prod.outlook.com (2603:10a6:20b:4e3::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: AS4PR04MB9244:EE_|AM0PR04MB6945:EE_ X-MS-Office365-Filtering-Correlation-Id: df9ac2c9-a32b-4664-086b-08dd5bca5402 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|52116014|7416014|1800799024|376014|38350700014; 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charset="utf-8" This is an 8 megapixel raw10/raw12 sensor with HDR capabilities. HDR mode control is supported, with one HDR mode: staggered HDR with 2 exposures on separate virtual channels. However, for now, only one exposure (VC 0) is accessible via get_frame_desc. Supported resolutions: - 1920 x 1080 @ 60fps (SBGGR10, no HDR) - 1920 x 1080 @ 30fps (SBGGR10, HDR) - 3840 x 2160 @ 30fps (SBGGR12, no HDR) - 3840 x 2160 @ 15fps (SBGGR12, HDR) - 3840 x 2160 @ 30fps (SBGGR10, no HDR) - 3840 x 2160 @ 15fps (SBGGR10, HDR) Signed-off-by: Mirela Rabulea --- Changes in v4: Switch to Y media bus codes. The CFA pattern control will be implemented w= hen patches get merged, or maybe separatelly as RFC? Add pixel_rate member to mode struct, remove fps member. We do not have in= formation how to calculate the pixel rate from the PLL parameters that can = be made public. Use register macros for the registers that are documented. User register g= roup macros, where individual registers are not documented Constify more structs Remove some unneded ending commas after a terminator Fix a seeries of smatch warnings like: warning: symbol 'os08a20_init_setti= ng_common' was not declared. Should it be static? Shorten some more lines to 80 columns Changes in v3: Don't hardcode timing registers: remove timing registers x_output_size/y_o= utput_size from register configuration list, add them to ox05b1s_apply_curr= ent_mode Remove HTS,VTS from register config list as they are written by HBLANK and= VBLANK controls through __v4l2_ctrl_handler_setup Use const for os08a20_supported_modes=09 os08a20 register config cleaning (remove all registers that were at their = default value, and more, keep only what seems mandatory to be able to strea= m) Let the 4k 10bit mode by default without hdr, all 3 modes are now by defau= lt without hdr, staggered hdr may be enabled via v4l2-ctl for any of them. Separate the 10/12 bit register settings into separate lists: os08a20_init= _setting_10bit, os08a20_init_setting_12bit Update commit description: rearrange supported resolutions and remove 1 du= plicate line, state HDR limitation Increase a bit the default vts for 1080p, to get exactly 60fps, it was 62.= 61 Use regmap_update_bits() directly and remove ox05b1s_regmap_update_bits() Changes in v2: Add spaces inside brackets, wrap lines to 80 Remove some redundant initialization Use a loop in os08a20_enable_staggered_hdr/os08a20_disable_staggered_hdr, = for that, add a register settings array for HDR enabling/disabling Make "sizes" a pointer Remove mode headers, add supported modes in the dedicated c file, ox05b1s_= modes.c=20 Refactor register lists, for os08a20 use a common list for all modes, and = also specific lists per mode drivers/media/i2c/ox05b1s/ox05b1s.h | 4 + drivers/media/i2c/ox05b1s/ox05b1s_mipi.c | 187 +++++++++++++++++++++- drivers/media/i2c/ox05b1s/ox05b1s_modes.c | 110 +++++++++++++ 3 files changed, 300 insertions(+), 1 deletion(-) diff --git a/drivers/media/i2c/ox05b1s/ox05b1s.h b/drivers/media/i2c/ox05b1= s/ox05b1s.h index 2a87d69864f9..58454e10150b 100644 --- a/drivers/media/i2c/ox05b1s/ox05b1s.h +++ b/drivers/media/i2c/ox05b1s/ox05b1s.h @@ -17,6 +17,10 @@ struct ox05b1s_reglist { const struct ox05b1s_reg *regs; }; =20 +extern const struct ox05b1s_reglist os08a20_reglist_4k_10b[]; +extern const struct ox05b1s_reglist os08a20_reglist_4k_12b[]; +extern const struct ox05b1s_reglist os08a20_reglist_1080p_10b[]; + extern const struct ox05b1s_reglist ox05b1s_reglist_2592x1944[]; =20 #endif /* OX05B1S_H */ diff --git a/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c b/drivers/media/i2c/o= x05b1s/ox05b1s_mipi.c index 1026216ddd5b..bc578fc61f1f 100644 --- a/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c +++ b/drivers/media/i2c/ox05b1s/ox05b1s_mipi.c @@ -40,6 +40,7 @@ struct ox05b1s_sizes { const struct v4l2_area *sizes; }; =20 +struct ox05b1s; struct ox05b1s_plat_data { char name[20]; u32 chip_id; @@ -52,6 +53,9 @@ struct ox05b1s_plat_data { const struct ox05b1s_mode *supported_modes; u32 default_mode_index; const struct ox05b1s_sizes *supported_codes; + const char * const *hdr_modes; + u32 hdr_modes_count; + int (*set_hdr_mode)(struct ox05b1s *sensor, u32 hdr_mode); }; =20 struct ox05b1s_ctrls { @@ -62,6 +66,7 @@ struct ox05b1s_ctrls { struct v4l2_ctrl *vblank; struct v4l2_ctrl *gain; struct v4l2_ctrl *exposure; + struct v4l2_ctrl *hdr_mode; }; =20 struct ox05b1s_mode { @@ -102,6 +107,87 @@ struct ox05b1s { struct ox05b1s_ctrls ctrls; }; =20 +#define OS08A20_PIXEL_RATE_144M 144000000 +#define OS08A20_PIXEL_RATE_288M 288000000 +static const struct ox05b1s_mode os08a20_supported_modes[] =3D { + { + /* 1080p BGGR10, no hdr, 60fps */ + .index =3D 0, + .width =3D 1920, + .height =3D 1080, + .code =3D MEDIA_BUS_FMT_Y10_1X10, + .bpp =3D 10, + .vts =3D 0x4d3, + .hts =3D 0x790, + .exp =3D 0x4d3 - 8, + .h_bin =3D true, + .pixel_rate =3D OS08A20_PIXEL_RATE_144M, + .reg_data =3D os08a20_reglist_1080p_10b, + }, { + /* 4k BGGR10, no hdr, 30fps */ + .index =3D 1, + .width =3D 3840, + .height =3D 2160, + .code =3D MEDIA_BUS_FMT_Y10_1X10, + .bpp =3D 10, + .vts =3D 0x90a, + .hts =3D 0x818, + .exp =3D 0x90a - 8, + .h_bin =3D false, + .pixel_rate =3D OS08A20_PIXEL_RATE_288M, + .reg_data =3D os08a20_reglist_4k_10b, + }, { + /* 4k BGGR12, no hdr, 30fps */ + .index =3D 2, + .width =3D 3840, + .height =3D 2160, + .code =3D MEDIA_BUS_FMT_Y12_1X12, + .bpp =3D 12, + .vts =3D 0x8f0, + .hts =3D 0x814, + .exp =3D 0x8f0 - 8, + .h_bin =3D false, + .pixel_rate =3D OS08A20_PIXEL_RATE_288M, + .reg_data =3D os08a20_reglist_4k_12b, + }, { + /* sentinel */ + } +}; + +/* keep in sync with os08a20_supported_modes */ +static const struct v4l2_area os08a20_sbggr10_sizes[] =3D { + { + .width =3D 1920, + .height =3D 1080, + }, { + .width =3D 3840, + .height =3D 2160, + }, { + /* sentinel */ + } +}; + +static const struct v4l2_area os08a20_sbggr12_sizes[] =3D { + { + .width =3D 3840, + .height =3D 2160, + }, { + /* sentinel */ + } +}; + +static const struct ox05b1s_sizes os08a20_supported_codes[] =3D { + { + .code =3D MEDIA_BUS_FMT_Y10_1X10, + .sizes =3D os08a20_sbggr10_sizes, + }, { + .code =3D MEDIA_BUS_FMT_Y12_1X12, + .sizes =3D os08a20_sbggr12_sizes, + }, { + /* sentinel */ + } +}; + #define OX05B1S_PIXEL_RATE_48M 48000000 static const struct ox05b1s_mode ox05b1s_supported_modes[] =3D { { @@ -231,6 +317,62 @@ static int ox05b1s_write_reg_array(struct ox05b1s *sen= sor, return 0; } =20 +static const char * const os08a20_hdr_modes[] =3D { + "NO HDR", /* No HDR, single exposure */ + "HDR Staggered", /* Staggered HDR mode, 2 exposures on separate VC */ +}; + +static const struct ox05b1s_reg os08a20_init_setting_hdr_en[] =3D { + { 0x3661, BIT(0) }, /* CORE1[0] STG_HDR_ALIGN_EN */ + { 0x3821, BIT(5) }, /* FORMAT2[5] STG_HDR_EN */ + { 0x4813, BIT(3) }, /* MIPI_CTRL_13[3] */ + { 0x486e, BIT(2) }, /* MIPI_CTRL_6E[2] MIPI_VC_ENABLE */ +}; + +static int os08a20_enable_staggered_hdr(struct ox05b1s *sensor) +{ + int ret; + + for (int i =3D 0; i < ARRAY_SIZE(os08a20_init_setting_hdr_en); i++) { + ret =3D regmap_update_bits(sensor->regmap, + os08a20_init_setting_hdr_en[i].addr, + os08a20_init_setting_hdr_en[i].data, + os08a20_init_setting_hdr_en[i].data); + if (ret) + return ret; + } + + return 0; +} + +static int os08a20_disable_staggered_hdr(struct ox05b1s *sensor) +{ + int ret; + + for (int i =3D 0; i < ARRAY_SIZE(os08a20_init_setting_hdr_en); i++) { + ret =3D regmap_update_bits(sensor->regmap, + os08a20_init_setting_hdr_en[i].addr, + os08a20_init_setting_hdr_en[i].data, + 0); + if (ret) + return ret; + } + + return 0; +} + +static int os08a20_set_hdr_mode(struct ox05b1s *sensor, u32 hdr_mode) +{ + switch (hdr_mode) { + case 0: + return os08a20_disable_staggered_hdr(sensor); + case 1: + return os08a20_enable_staggered_hdr(sensor); + default: + return -EINVAL; + } +} + static inline struct v4l2_subdev *ctrl_to_sd(struct v4l2_ctrl *ctrl) { return &container_of(ctrl->handler, struct ox05b1s, @@ -274,6 +416,12 @@ static int ox05b1s_s_ctrl(struct v4l2_ctrl *ctrl) ret =3D cci_write(sensor->regmap, OX05B1S_REG_EXPOSURE, ctrl->val, NULL); break; + case V4L2_CID_HDR_SENSOR_MODE: + if (sensor->model->set_hdr_mode) + ret =3D sensor->model->set_hdr_mode(sensor, ctrl->val); + else + ret =3D -EINVAL; + break; default: ret =3D -EINVAL; break; @@ -336,6 +484,13 @@ static int ox05b1s_init_controls(struct ox05b1s *senso= r) ctrls->gain =3D v4l2_ctrl_new_std(hdl, ops, V4L2_CID_ANALOGUE_GAIN, 0, 0xFFFF, 1, 0x80); =20 + if (sensor->model->hdr_modes) + ctrls->hdr_mode =3D v4l2_ctrl_new_std_menu_items(hdl, ops, V4L2_CID_HDR_= SENSOR_MODE, + sensor->model->hdr_modes_count - 1, + 0, 0, sensor->model->hdr_modes); + else + ctrls->hdr_mode =3D NULL; + if (hdl->error) { ret =3D hdl->error; goto free_ctrls; @@ -658,6 +813,8 @@ static u8 ox05b1s_code2dt(const u32 code) switch (code) { case MEDIA_BUS_FMT_Y10_1X10: return MIPI_CSI2_DT_RAW10; + case MEDIA_BUS_FMT_Y12_1X12: + return MIPI_CSI2_DT_RAW12; default: return MIPI_CSI2_DT_RAW10; } @@ -768,6 +925,9 @@ static int ox05b1s_read_chip_id(struct ox05b1s *sensor) } =20 switch (chip_id) { + case 0x530841: + camera_name =3D "os08a20"; + break; case 0x580542: camera_name =3D "ox05b1s"; break; @@ -912,6 +1072,24 @@ static void ox05b1s_remove(struct i2c_client *client) static DEFINE_RUNTIME_DEV_PM_OPS(ox05b1s_pm_ops, ox05b1s_runtime_suspend, ox05b1s_runtime_resume, NULL); =20 +static const struct ox05b1s_plat_data os08a20_data =3D { + .name =3D "os08a20", + .chip_id =3D 0x530841, + .native_width =3D 3872, /* 16 dummy + 3840 active + 16 dummy */ + .native_height =3D 2192, /* 16 dummy + 2160 active + 16 dummy */ + .active_top =3D 16, + .active_left =3D 16, + .active_width =3D 3840, + .active_height =3D 2160, + .supported_modes =3D os08a20_supported_modes, + .default_mode_index =3D 0, + .supported_codes =3D os08a20_supported_codes, + .hdr_modes =3D os08a20_hdr_modes, + .hdr_modes_count =3D ARRAY_SIZE(os08a20_hdr_modes), + .set_hdr_mode =3D os08a20_set_hdr_mode, + +}; + static const struct ox05b1s_plat_data ox05b1s_data =3D { .name =3D "ox05b1s", .chip_id =3D 0x580542, @@ -923,10 +1101,17 @@ static const struct ox05b1s_plat_data ox05b1s_data = =3D { .active_height =3D 1944, .supported_modes =3D ox05b1s_supported_modes, .default_mode_index =3D 0, - .supported_codes =3D ox05b1s_supported_codes + .supported_codes =3D ox05b1s_supported_codes, + .hdr_modes =3D NULL, + .hdr_modes_count =3D 0, + .set_hdr_mode =3D NULL }; =20 static const struct of_device_id ox05b1s_of_match[] =3D { + { + .compatible =3D "ovti,os08a20", + .data =3D &os08a20_data, + }, { .compatible =3D "ovti,ox05b1s", .data =3D &ox05b1s_data, diff --git a/drivers/media/i2c/ox05b1s/ox05b1s_modes.c b/drivers/media/i2c/= ox05b1s/ox05b1s_modes.c index 9a1f3a89077c..e17c32a90cba 100644 --- a/drivers/media/i2c/ox05b1s/ox05b1s_modes.c +++ b/drivers/media/i2c/ox05b1s/ox05b1s_modes.c @@ -10,6 +10,116 @@ #include #include "ox05b1s.h" =20 +#define OS08A20_REG_MIPI_BIT_10_12 CCI_REG8(0x031e) +/* Analog Control Registers 0x3600-0x3637 */ +#define OS08A20_REG_ANA_CTRL CCI_REG8(0x3600) +#define OS08A20_REG_CORE_0 CCI_REG8(0x3660) +/* Sensor Timing Control Registers 0x3700-0x37ff */ +#define OS08A20_REG_SENSOR_TIMING_CTRL CCI_REG8(0x3700) +#define OS08A20_REG_X_ODD_INC CCI_REG8(0x3814) +#define OS08A20_REG_Y_ODD_INC CCI_REG8(0x3816) +#define OS08A20_REG_FORMAT1 CCI_REG8(0x3820) +#define OS08A20_REG_FORMAT2 CCI_REG8(0x3821) +#define OS08A20_REG_PCLK_PERIOD CCI_REG8(0x4837) +#define OS08A20_REG_ISP_CTRL_1 CCI_REG8(0x5001) +#define OS08A20_REG_ISP_CTRL_5 CCI_REG8(0x5005) + +/* Common register configuration for Omnivision OS08A20 raw camera */ +static const struct ox05b1s_reg os08a20_init_setting_common[] =3D { + { OS08A20_REG_ANA_CTRL + 0x05, 0x50 }, + { OS08A20_REG_ANA_CTRL + 0x10, 0x39 }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x5e, 0x0b }, + { OS08A20_REG_ISP_CTRL_1, 0x42 }, + { OS08A20_REG_ISP_CTRL_5, 0x00 }, + { /* sentinel*/ } +}; + +/* Common register configuration for Omnivision OS08A20 10 bit */ +static const struct ox05b1s_reg os08a20_init_setting_10bit[] =3D { + { OS08A20_REG_MIPI_BIT_10_12, 0x09 }, + { OS08A20_REG_ANA_CTRL + 0x09, 0xb5 }, + { OS08A20_REG_CORE_0, 0x43 }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x06, 0x35 }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x0a, 0x00 }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x0b, 0x98 }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x09, 0x49 }, + { /* sentinel*/ } +}; + +/* Common register configuration for Omnivision OS08A20 12 bit */ +static const struct ox05b1s_reg os08a20_init_setting_12bit[] =3D { + { OS08A20_REG_MIPI_BIT_10_12, 0x0a }, + { OS08A20_REG_ANA_CTRL + 0x09, 0xdb }, + { OS08A20_REG_CORE_0, 0xd3 }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x06, 0x6a }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x0a, 0x01 }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x0b, 0x30 }, + { OS08A20_REG_SENSOR_TIMING_CTRL + 0x09, 0x48 }, + { /* sentinel*/ } +}; + +/* Mode specific register configurations for Omnivision OS08A20 raw camera= */ + +/* OS08A20 3840 x 2160 @30fps BGGR10 no more HDR */ +static const struct ox05b1s_reg os08a20_init_setting_4k_10b[] =3D { + { OS08A20_REG_FORMAT2, 0x04 }, /* mirror */ + { OS08A20_REG_PCLK_PERIOD, 0x10 }, + { /* sentinel*/ } +}; + +/* OS08A20 3840 x 2160 @30fps BGGR12 */ +static const struct ox05b1s_reg os08a20_init_setting_4k_12b[] =3D { + { OS08A20_REG_FORMAT2, 0x04 }, /* mirror */ + { OS08A20_REG_PCLK_PERIOD, 0x10 }, + { /* sentinel*/ } +}; + +/* OS08A20 1920 x 1080 @60fps BGGR10 */ +static const struct ox05b1s_reg os08a20_init_setting_1080p_10b[] =3D { + { OS08A20_REG_X_ODD_INC, 0x03 }, + { OS08A20_REG_Y_ODD_INC, 0x03 }, + { OS08A20_REG_FORMAT1, 0x01 }, /* vertical bining */ + { OS08A20_REG_FORMAT2, 0x05 }, /* mirror, horizontal bining */ + { OS08A20_REG_PCLK_PERIOD, 0x16 }, + { /* sentinel*/ } +}; + +const struct ox05b1s_reglist os08a20_reglist_4k_10b[] =3D { + { + .regs =3D os08a20_init_setting_common + }, { + .regs =3D os08a20_init_setting_10bit + }, { + .regs =3D os08a20_init_setting_4k_10b + }, { + /* sentinel */ + } +}; + +const struct ox05b1s_reglist os08a20_reglist_4k_12b[] =3D { + { + .regs =3D os08a20_init_setting_common + }, { + .regs =3D os08a20_init_setting_12bit + }, { + .regs =3D os08a20_init_setting_4k_12b + }, { + /* sentinel */ + } +}; + +const struct ox05b1s_reglist os08a20_reglist_1080p_10b[] =3D { + { + .regs =3D os08a20_init_setting_common + }, { + .regs =3D os08a20_init_setting_10bit + }, { + .regs =3D os08a20_init_setting_1080p_10b + }, { + /* sentinel */ + } +}; + #define OX05B1S_REG_PLL1_CTRL_REG07 CCI_REG8(0x0307) #define OX05B1S_REG_PLL3_CTRL_REG4A CCI_REG8(0x034a) #define OX05B1S_REG_PLL_MONITOR_REG0B CCI_REG8(0x040b) --=20 2.25.1