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Wed, 05 Mar 2025 11:05:27 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:19 +0100 Subject: [PATCH v2 1/7] dt-bindings: media: qcom,sm8550-iris: document SM8650 IRIS accelerator Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250305-topic-sm8x50-iris-v10-v2-1-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=1966; i=neil.armstrong@linaro.org; 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Reviewed-by: Rob Herring (Arm) Signed-off-by: Neil Armstrong Reviewed-by: Bryan O'Donoghue Reviewed-by: Vikash Garodia --- .../bindings/media/qcom,sm8550-iris.yaml | 33 ++++++++++++++++++= ---- 1 file changed, 28 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml = b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml index e424ea84c211f473a799481fd5463a16580187ed..536cf458dcb08141e5a1ec8c3df= 964196e599a57 100644 --- a/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml +++ b/Documentation/devicetree/bindings/media/qcom,sm8550-iris.yaml @@ -14,12 +14,11 @@ description: The iris video processing unit is a video encode and decode accelerator present on Qualcomm platforms. =20 -allOf: - - $ref: qcom,venus-common.yaml# - properties: compatible: - const: qcom,sm8550-iris + enum: + - qcom,sm8550-iris + - qcom,sm8650-iris =20 power-domains: maxItems: 4 @@ -49,11 +48,15 @@ properties: - const: video-mem =20 resets: - maxItems: 1 + minItems: 1 + maxItems: 3 =20 reset-names: + minItems: 1 items: - const: bus + - const: xo + - const: core =20 iommus: maxItems: 2 @@ -75,6 +78,26 @@ required: - iommus - dma-coherent =20 +allOf: + - $ref: qcom,venus-common.yaml# + - if: + properties: + compatible: + enum: + - qcom,sm8650-iris + then: + properties: + resets: + minItems: 3 + reset-names: + minItems: 3 + else: + properties: + resets: + maxItems: 1 + reset-names: + maxItems: 1 + unevaluatedProperties: false =20 examples: --=20 2.34.1 From nobody Mon Feb 9 00:30:34 2026 Received: from mail-wm1-f50.google.com (mail-wm1-f50.google.com [209.85.128.50]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDCF5253F3D for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In order to support vpu33, the iris_vpu_power_off_controller needs to be reused and extended, but the AON_WRAPPER_MVP_NOC_LPI_CONTROL cannot be set from the power_off_controller sequence like vpu2 and vpu3 so split the power_off_controller into 3 steps: - iris_vpu_power_off_controller_begin - iris_vpu_power_off_controller_end - iris_vpu_power_off_controller_disable And use them in a common iris_vpu_power_off_controller() for vpu2 and vpu3 based platforms. Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_vpu_common.c | 46 ++++++++++++++++--= ---- 1 file changed, 33 insertions(+), 13 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index fe9896d66848cdcd8c67bd45bbf3b6ce4a01ab10..d6ce92f3c7544e44dccca26bf6a= 4c95a720f9229 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -211,33 +211,29 @@ int iris_vpu_prepare_pc(struct iris_core *core) return -EAGAIN; } =20 -static int iris_vpu_power_off_controller(struct iris_core *core) +static void iris_vpu_power_off_controller_begin(struct iris_core *core) { - u32 val =3D 0; - int ret; - writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CP= U_CS_X2RPMH); +} =20 - writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONT= ROL); - - ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, - val, val & BIT(0), 200, 2000); - if (ret) - goto disable_power; +static int iris_vpu_power_off_controller_end(struct iris_core *core) +{ + u32 val =3D 0; + int ret; =20 writel(REQ_POWER_DOWN_PREP, core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_CON= TROL); =20 ret =3D readl_poll_timeout(core->reg_base + WRAPPER_IRIS_CPU_NOC_LPI_STAT= US, val, val & BIT(0), 200, 2000); if (ret) - goto disable_power; + return ret; =20 writel(0x0, core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_CONTROL); =20 ret =3D readl_poll_timeout(core->reg_base + WRAPPER_DEBUG_BRIDGE_LPI_STAT= US, val, val =3D=3D 0, 200, 2000); if (ret) - goto disable_power; + return ret; =20 writel(CTL_AXI_CLK_HALT | CTL_CLK_HALT, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); @@ -245,10 +241,34 @@ static int iris_vpu_power_off_controller(struct iris_= core *core) writel(0x0, core->reg_base + WRAPPER_TZ_QNS4PDXFIFO_RESET); writel(0x0, core->reg_base + WRAPPER_TZ_CTL_AXI_CLOCK_CONFIG); =20 -disable_power: + return 0; +} + +static void iris_vpu_power_off_controller_disable(struct iris_core *core) +{ iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); iris_disable_unprepare_clock(core, IRIS_AXI_CLK); iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); +} + +static int iris_vpu_power_off_controller(struct iris_core *core) +{ + u32 val =3D 0; + int ret; + + iris_vpu_power_off_controller_begin(core); + + writel(REQ_POWER_DOWN_PREP, core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONT= ROL); + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, + val, val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + iris_vpu_power_off_controller_end(core); + +disable_power: + iris_vpu_power_off_controller_disable(core); =20 return 0; } --=20 2.34.1 From nobody Mon Feb 9 00:30:34 2026 Received: from mail-wm1-f51.google.com (mail-wm1-f51.google.com [209.85.128.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDEB3254B12 for ; Wed, 5 Mar 2025 19:05:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Wed, 05 Mar 2025 11:05:30 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-391241bd151sm2045218f8f.21.2025.03.05.11.05.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 11:05:29 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:21 +0100 Subject: [PATCH v2 3/7] media: platform: qcom/iris: add power_off_controller to vpu_ops Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250305-topic-sm8x50-iris-v10-v2-3-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE In order to support the SM8650 iris33 hardware, we need to provide a specific constoller power off sequences via the vpu_ops callbacks. Add the callback, and use the current helper for currently supported platforms. Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_vpu2.c | 1 + drivers/media/platform/qcom/iris/iris_vpu3.c | 2 ++ drivers/media/platform/qcom/iris/iris_vpu_common.c | 14 ++++++++++---- drivers/media/platform/qcom/iris/iris_vpu_common.h | 2 ++ 4 files changed, 15 insertions(+), 4 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu2.c b/drivers/media/p= latform/qcom/iris/iris_vpu2.c index 8f502aed43ce2fa6a272a2ce14ff1ca54d3e63a2..7cf1bfc352d34b897451061b5c1= 4fbe90276433d 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu2.c +++ b/drivers/media/platform/qcom/iris/iris_vpu2.c @@ -34,5 +34,6 @@ static u64 iris_vpu2_calc_freq(struct iris_inst *inst, si= ze_t data_size) =20 const struct vpu_ops iris_vpu2_ops =3D { .power_off_hw =3D iris_vpu_power_off_hw, + .power_off_controller =3D iris_vpu_power_off_controller, .calc_freq =3D iris_vpu2_calc_freq, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/p= latform/qcom/iris/iris_vpu3.c index b484638e6105a69319232f667ee7ae95e3853698..95f362633c95b101ecfda6480c4= c0b73416bd00c 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3.c @@ -117,6 +117,8 @@ static u64 iris_vpu3_calculate_frequency(struct iris_in= st *inst, size_t data_siz } =20 const struct vpu_ops iris_vpu3_ops =3D { + .reset_controller =3D iris_vpu_reset_controller, .power_off_hw =3D iris_vpu3_power_off_hardware, + .power_off_controller =3D iris_vpu_power_off_controller, .calc_freq =3D iris_vpu3_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index d6ce92f3c7544e44dccca26bf6a4c95a720f9229..3b3e1ca1e42183561ee78c89f50= 946fd0cc3c3ab 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -251,7 +251,7 @@ static void iris_vpu_power_off_controller_disable(struc= t iris_core *core) iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); } =20 -static int iris_vpu_power_off_controller(struct iris_core *core) +int iris_vpu_power_off_controller(struct iris_core *core) { u32 val =3D 0; int ret; @@ -284,23 +284,29 @@ void iris_vpu_power_off(struct iris_core *core) { dev_pm_opp_set_rate(core->dev, 0); core->iris_platform_data->vpu_ops->power_off_hw(core); - iris_vpu_power_off_controller(core); + core->iris_platform_data->vpu_ops->power_off_controller(core); iris_unset_icc_bw(core); =20 if (!iris_vpu_watchdog(core, core->intr_status)) disable_irq_nosync(core->irq); } =20 -static int iris_vpu_power_on_controller(struct iris_core *core) +static int iris_vpu_reset_controller(struct iris_core *core) { u32 rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; + + return reset_control_bulk_reset(rst_tbl_size, core->resets); +} + +static int iris_vpu_power_on_controller(struct iris_core *core) +{ int ret; =20 ret =3D iris_enable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_= CTRL_POWER_DOMAIN]); if (ret) return ret; =20 - ret =3D reset_control_bulk_reset(rst_tbl_size, core->resets); + ret =3D iris_vpu_reset_controller(core); if (ret) goto err_disable_power; =20 diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index 63fa1fa5a4989e48aebdb6c7619c140000c0b44c..f8965661c602f990d5a7057565f= 79df4112d097e 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -13,6 +13,7 @@ extern const struct vpu_ops iris_vpu3_ops; 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Wed, 05 Mar 2025 11:05:30 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-391241bd151sm2045218f8f.21.2025.03.05.11.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 11:05:30 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:22 +0100 Subject: [PATCH v2 4/7] media: platform: qcom/iris: introduce optional controller_rst_tbl Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250305-topic-sm8x50-iris-v10-v2-4-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Introduce an optional controller_rst_tbl use to store reset lines used to reset part of the controller. This is necessary for the vpu3 support, when the xo reset line must be asserted separately from the other reset line on power off operation. Factor the iris_init_resets() logic to allow requesting multiple reset tables. Signed-off-by: Neil Armstrong Reviewed-by: Bryan O'Donoghue --- drivers/media/platform/qcom/iris/iris_core.h | 1 + .../platform/qcom/iris/iris_platform_common.h | 2 ++ drivers/media/platform/qcom/iris/iris_probe.c | 39 +++++++++++++++---= ---- 3 files changed, 30 insertions(+), 12 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_core.h b/drivers/media/p= latform/qcom/iris/iris_core.h index 37fb4919fecc62182784b4dca90fcab47dd38a80..78143855b277cd3ebdc7a1e7f35= f6df284aa364c 100644 --- a/drivers/media/platform/qcom/iris/iris_core.h +++ b/drivers/media/platform/qcom/iris/iris_core.h @@ -82,6 +82,7 @@ struct iris_core { struct clk_bulk_data *clock_tbl; u32 clk_count; struct reset_control_bulk_data *resets; + struct reset_control_bulk_data *controller_resets; const struct iris_platform_data *iris_platform_data; enum iris_core_state state; dma_addr_t iface_q_table_daddr; diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index f6b15d2805fb2004699709bb12cd7ce9b052180c..fdd40fd80178c4c66b37e392d07= a0a62f492f108 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -156,6 +156,8 @@ struct iris_platform_data { unsigned int clk_tbl_size; const char * const *clk_rst_tbl; unsigned int clk_rst_tbl_size; + const char * const *controller_rst_tbl; + unsigned int controller_rst_tbl_size; u64 dma_mask; const char *fwname; u32 pas_id; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index aca442dcc153830e6252d1dca87afb38c0b9eb8f..4f8bce6e2002bffee4c93dcaaf6= e52bf4e40992e 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -91,25 +91,40 @@ static int iris_init_clocks(struct iris_core *core) return 0; } =20 -static int iris_init_resets(struct iris_core *core) +static int iris_init_reset_table(struct iris_core *core, + struct reset_control_bulk_data **resets, + const char * const *rst_tbl, u32 rst_tbl_size) { - const char * const *rst_tbl; - u32 rst_tbl_size; u32 i =3D 0; =20 - rst_tbl =3D core->iris_platform_data->clk_rst_tbl; - rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; - - core->resets =3D devm_kzalloc(core->dev, - sizeof(*core->resets) * rst_tbl_size, - GFP_KERNEL); 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Wed, 05 Mar 2025 11:05:31 -0800 (PST) Received: from arrakeen.starnux.net ([2a01:e0a:982:cbb0:8261:5fff:fe11:bdda]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-391241bd151sm2045218f8f.21.2025.03.05.11.05.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 05 Mar 2025 11:05:31 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:23 +0100 Subject: [PATCH v2 5/7] media: platform: qcom/iris: rename iris_vpu3 to iris_vpu3x Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250305-topic-sm8x50-iris-v10-v2-5-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The vpu33 HW is very close to vpu3, and shares most of the operations, so rename file to vpu3x since we'll handle all vpu3 variants in it. Signed-off-by: Neil Armstrong Reviewed-by: Dikshita Agarwal --- drivers/media/platform/qcom/iris/Makefile | 2 +- drivers/media/platform/qcom/iris/{iris_vpu3.c =3D> iris_vpu3x.c} | 0 2 files changed, 1 insertion(+), 1 deletion(-) diff --git a/drivers/media/platform/qcom/iris/Makefile b/drivers/media/plat= form/qcom/iris/Makefile index 35390534534e93f4617c1036a05ca0921567ba1d..473aaf655448180ade917e64228= 9677fc1277f99 100644 --- a/drivers/media/platform/qcom/iris/Makefile +++ b/drivers/media/platform/qcom/iris/Makefile @@ -20,7 +20,7 @@ qcom-iris-objs +=3D \ iris_vb2.o \ iris_vdec.o \ iris_vpu2.o \ - iris_vpu3.o \ + iris_vpu3x.o \ iris_vpu_buffer.o \ iris_vpu_common.o \ =20 diff --git a/drivers/media/platform/qcom/iris/iris_vpu3.c b/drivers/media/p= latform/qcom/iris/iris_vpu3x.c similarity index 100% rename from drivers/media/platform/qcom/iris/iris_vpu3.c rename to drivers/media/platform/qcom/iris/iris_vpu3x.c --=20 2.34.1 From nobody Mon Feb 9 00:30:34 2026 Received: from mail-wr1-f52.google.com (mail-wr1-f52.google.com [209.85.221.52]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6BEF72561CE for ; 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a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE The IRIS acceleration found in the SM8650 platforms uses the vpu33 hardware version, and requires a slighly different reset and power off sequences in order to properly get out of runtime suspend. Signed-off-by: Neil Armstrong --- drivers/media/platform/qcom/iris/iris_vpu3x.c | 144 +++++++++++++++++= ++-- drivers/media/platform/qcom/iris/iris_vpu_common.c | 4 +- drivers/media/platform/qcom/iris/iris_vpu_common.h | 3 + 3 files changed, 137 insertions(+), 14 deletions(-) diff --git a/drivers/media/platform/qcom/iris/iris_vpu3x.c b/drivers/media/= platform/qcom/iris/iris_vpu3x.c index 95f362633c95b101ecfda6480c4c0b73416bd00c..109f663d031ab5f5ee8b58eb2a7= 81eb27d2675aa 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu3x.c +++ b/drivers/media/platform/qcom/iris/iris_vpu3x.c @@ -4,11 +4,13 @@ */ =20 #include +#include =20 #include "iris_instance.h" #include "iris_vpu_common.h" #include "iris_vpu_register_defines.h" =20 +#define AON_BASE_OFFS 0x000E0000 #define AON_MVP_NOC_RESET 0x0001F000 =20 #define WRAPPER_CORE_CLOCK_CONFIG (WRAPPER_BASE_OFFS + 0x88) @@ -25,7 +27,16 @@ =20 #define VCODEC_SS_IDLE_STATUSN (VCODEC_BASE_OFFS + 0x70) =20 -static bool iris_vpu3_hw_power_collapsed(struct iris_core *core) +#define AON_WRAPPER_MVP_NOC_LPI_CONTROL (AON_BASE_OFFS) +#define AON_WRAPPER_MVP_NOC_LPI_STATUS (AON_BASE_OFFS + 0x4) + +#define AON_WRAPPER_MVP_NOC_CORE_SW_RESET (AON_BASE_OFFS + 0x18) +#define SW_RESET BIT(0) +#define AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL (AON_BASE_OFFS + 0x20) +#define NOC_HALT BIT(0) +#define AON_WRAPPER_SPARE (AON_BASE_OFFS + 0x28) + +static bool iris_vpu3x_hw_power_collapsed(struct iris_core *core) { u32 value, pwr_status; =20 @@ -35,13 +46,13 @@ static bool iris_vpu3_hw_power_collapsed(struct iris_co= re *core) return pwr_status ? false : true; } =20 -static void iris_vpu3_power_off_hardware(struct iris_core *core) +static int iris_vpu3x_power_off_hardware_begin(struct iris_core *core) { u32 reg_val =3D 0, value, i; int ret; =20 - if (iris_vpu3_hw_power_collapsed(core)) - goto disable_power; + if (iris_vpu3x_hw_power_collapsed(core)) + return 1; =20 dev_err(core->dev, "video hw is power on\n"); =20 @@ -53,9 +64,29 @@ static void iris_vpu3_power_off_hardware(struct iris_cor= e *core) ret =3D readl_poll_timeout(core->reg_base + VCODEC_SS_IDLE_STATUSN + 4 *= i, reg_val, reg_val & 0x400000, 2000, 20000); if (ret) - goto disable_power; + return ret; } =20 + return 0; +} + +static void iris_vpu3x_power_off_hardware_end(struct iris_core *core) +{ + writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, + core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); + writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); +} + +static void iris_vpu3_power_off_hardware(struct iris_core *core) +{ + u32 reg_val =3D 0; + int ret; + + ret =3D iris_vpu3x_power_off_hardware_begin(core); + if (ret) + goto disable_power; + writel(VIDEO_NOC_RESET_REQ, core->reg_base + AON_WRAPPER_MVP_NOC_RESET_RE= Q); =20 ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_RESET_ACK, @@ -70,16 +101,100 @@ static void iris_vpu3_power_off_hardware(struct iris_= core *core) if (ret) goto disable_power; =20 - writel(CORE_BRIDGE_SW_RESET | CORE_BRIDGE_HW_RESET_DISABLE, - core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); - writel(CORE_BRIDGE_HW_RESET_DISABLE, core->reg_base + CPU_CS_AHB_BRIDGE_S= YNC_RESET); - writel(0x0, core->reg_base + CPU_CS_AHB_BRIDGE_SYNC_RESET); + iris_vpu3x_power_off_hardware_end(core); + +disable_power: + iris_vpu_power_off_hw(core); +} + +static void iris_vpu33_power_off_hardware(struct iris_core *core) +{ + u32 reg_val =3D 0; + int ret; + + ret =3D iris_vpu3x_power_off_hardware_begin(core); + if (ret) + goto disable_power; + + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_MVP_NOC_LPI_STATU= S, + reg_val, reg_val & BIT(0), 200, 2000); + if (ret) + goto disable_power; + + /* set MNoC to low power, set PD_NOC_QREQ (bit 0) */ + writel(BIT(0), core->reg_base + AON_WRAPPER_MVP_NOC_LPI_CONTROL); + + iris_vpu3x_power_off_hardware_end(core); =20 disable_power: iris_vpu_power_off_hw(core); } =20 -static u64 iris_vpu3_calculate_frequency(struct iris_inst *inst, size_t da= ta_size) +static int iris_vpu33_power_off_controller(struct iris_core *core) +{ + u32 xo_rst_tbl_size =3D core->iris_platform_data->controller_rst_tbl_size; + u32 clk_rst_tbl_size =3D core->iris_platform_data->clk_rst_tbl_size; + u32 val =3D 0; + int ret; + + iris_vpu_power_off_controller_begin(core); + + ret =3D iris_vpu_power_off_controller_end(core); + if (ret) + goto disable_power; + + reset_control_bulk_reset(clk_rst_tbl_size, core->resets); + + /* Disable MVP NoC clock */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val |=3D NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + /* enable MVP NoC reset */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val |=3D SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + /* poll AON spare register bit0 to become zero with 50ms timeout */ + ret =3D readl_poll_timeout(core->reg_base + AON_WRAPPER_SPARE, + val, (val & BIT(0)) =3D=3D 0, 1000, 50000); + if (ret) + goto disable_power; + + /* enable bit(1) to avoid cvp noc xo reset */ + val =3D readl(core->reg_base + AON_WRAPPER_SPARE); + val |=3D BIT(1); + writel(val, core->reg_base + AON_WRAPPER_SPARE); + + reset_control_bulk_assert(xo_rst_tbl_size, core->controller_resets); + + /* De-assert MVP NoC reset */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + val &=3D ~SW_RESET; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_SW_RESET); + + usleep_range(80, 100); + + reset_control_bulk_deassert(xo_rst_tbl_size, core->controller_resets); + + /* reset AON spare register */ + writel(0, core->reg_base + AON_WRAPPER_SPARE); + + /* Enable MVP NoC clock */ + val =3D readl(core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + val &=3D ~NOC_HALT; + writel(val, core->reg_base + AON_WRAPPER_MVP_NOC_CORE_CLK_CONTROL); + + iris_disable_unprepare_clock(core, IRIS_CTRL_CLK); + +disable_power: + iris_disable_power_domains(core, core->pmdomain_tbl->pd_devs[IRIS_CTRL_PO= WER_DOMAIN]); + iris_disable_unprepare_clock(core, IRIS_AXI_CLK); + + return 0; +} + +static u64 iris_vpu3x_calculate_frequency(struct iris_inst *inst, size_t d= ata_size) { struct platform_inst_caps *caps =3D inst->core->iris_platform_data->inst_= caps; struct v4l2_format *inp_f =3D inst->fmt_src; @@ -117,8 +232,13 @@ static u64 iris_vpu3_calculate_frequency(struct iris_i= nst *inst, size_t data_siz } =20 const struct vpu_ops iris_vpu3_ops =3D { - .reset_controller =3D iris_vpu_reset_controller, .power_off_hw =3D iris_vpu3_power_off_hardware, .power_off_controller =3D iris_vpu_power_off_controller, - .calc_freq =3D iris_vpu3_calculate_frequency, + .calc_freq =3D iris_vpu3x_calculate_frequency, +}; + +const struct vpu_ops iris_vpu33_ops =3D { + .power_off_hw =3D iris_vpu33_power_off_hardware, + .power_off_controller =3D iris_vpu33_power_off_controller, + .calc_freq =3D iris_vpu3x_calculate_frequency, }; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.c b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.c index 3b3e1ca1e42183561ee78c89f50946fd0cc3c3ab..43c62e2ee593146b8e3448e8c7c= ab44ef1a15bf2 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.c +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.c @@ -211,12 +211,12 @@ int iris_vpu_prepare_pc(struct iris_core *core) return -EAGAIN; } =20 -static void iris_vpu_power_off_controller_begin(struct iris_core *core) +void iris_vpu_power_off_controller_begin(struct iris_core *core) { writel(MSK_SIGNAL_FROM_TENSILICA | MSK_CORE_POWER_ON, core->reg_base + CP= U_CS_X2RPMH); } =20 -static int iris_vpu_power_off_controller_end(struct iris_core *core) +int iris_vpu_power_off_controller_end(struct iris_core *core) { u32 val =3D 0; int ret; diff --git a/drivers/media/platform/qcom/iris/iris_vpu_common.h b/drivers/m= edia/platform/qcom/iris/iris_vpu_common.h index f8965661c602f990d5a7057565f79df4112d097e..4af3cb0d44e00be498fc7ba648c= 68f1ef2cb0f20 100644 --- a/drivers/media/platform/qcom/iris/iris_vpu_common.h +++ b/drivers/media/platform/qcom/iris/iris_vpu_common.h @@ -10,6 +10,7 @@ struct iris_core; =20 extern const struct vpu_ops iris_vpu2_ops; extern const struct vpu_ops iris_vpu3_ops; +extern const struct vpu_ops iris_vpu33_ops; =20 struct vpu_ops { void (*power_off_hw)(struct iris_core *core); @@ -23,6 +24,8 @@ void iris_vpu_clear_interrupt(struct iris_core *core); int iris_vpu_watchdog(struct iris_core *core, u32 intr_status); int iris_vpu_prepare_pc(struct iris_core *core); int iris_vpu_power_on(struct iris_core *core); +void iris_vpu_power_off_controller_begin(struct iris_core *core); +int iris_vpu_power_off_controller_end(struct iris_core *core); int iris_vpu_power_off_controller(struct iris_core *core); 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Wed, 05 Mar 2025 11:05:32 -0800 (PST) From: Neil Armstrong Date: Wed, 05 Mar 2025 20:05:25 +0100 Subject: [PATCH v2 7/7] media: platform: qcom/iris: add sm8650 support Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250305-topic-sm8x50-iris-v10-v2-7-bd65a3fc099e@linaro.org> References: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> In-Reply-To: <20250305-topic-sm8x50-iris-v10-v2-0-bd65a3fc099e@linaro.org> To: Vikash Garodia , Dikshita Agarwal , Abhinav Kumar , Mauro Carvalho Chehab , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel Cc: linux-media@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Neil Armstrong X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=5217; i=neil.armstrong@linaro.org; h=from:subject:message-id; bh=neXImAtQA6tzq28UA2f7Fc6YFrL/8512jm9dsPst4Uw=; b=owEBbQKS/ZANAwAKAXfc29rIyEnRAcsmYgBnyKB1HLO9Z9d394GsUYIIHIi6x+YViVfgPszprcEs 3N73EoWJAjMEAAEKAB0WIQQ9U8YmyFYF/h30LIt33NvayMhJ0QUCZ8igdQAKCRB33NvayMhJ0fSOEA CXRdQdRV1ZYZOurILMyVtf3HyF/wL0JbBB3ktMurqv7RarFp8KAcdq9CcXOVjpTq575rTJMwF3j1p9 Ug9CCZ8lAOuDkpxyW/tQx3bwOeZEf7HZ91nRwWd0ZJsL0ZuH/H4PhM44RlzgGxvJcDixEmnmdQte25 t04c8VcLrooeMi5rkGRn0f5d7uW1GlEmQey7Hfq64ND1/w73pO7iPc2AjykO7D/IRLMiuxDzwEgcAy CHz0w4Sz2CxkTGkXhVeLFCs+I73Dazhgrdjq062pZPUqS6eWzPXSJm/wPI2jkl+7hAXf6z+W2/d0fv KrqhEDUjBLJcwYE4wvvesrPLffBdNt4xhU2sAMesrc2G6BXQWQv33Y9kguT4x+nQYJB4OJdyVDbIfr 3G1VdvAWsWBO4oFppgMpQeEW12/7bq3tq8BwCPUp4NqSW3JQ9FxadAVShQ+XlxTGraGRIUoSPR/b7I NXAf/hARIMF2LAx9uYUhncKpeLL3EeBqX7e6rSl8kHDKyUVwTu/fHjgb8kWWr4+rUqPqs7BdR1XyKr OwRjlo0PweXOzVt7TSz+TdP+P9o+cUXiO0MmaKQUB0dHXMgW3BJjWTpQnnM1KPnEM31Oku35y0Vx6R UUWXaRBR+p2MLIArCI3GE3KdxQFR55ASP6+r5rg2jXu9XZD3L+08w/026ncg== X-Developer-Key: i=neil.armstrong@linaro.org; a=openpgp; fpr=89EC3D058446217450F22848169AB7B1A4CFF8AE Add support for the SM8650 platform by re-using the SM8550 definitions and using the vpu33 ops. The SM8650/vpu33 requires more reset lines, but the H.284 decoder capabilities are identical. Signed-off-by: Neil Armstrong --- .../platform/qcom/iris/iris_platform_common.h | 1 + .../platform/qcom/iris/iris_platform_sm8550.c | 64 ++++++++++++++++++= ++++ drivers/media/platform/qcom/iris/iris_probe.c | 4 ++ 3 files changed, 69 insertions(+) diff --git a/drivers/media/platform/qcom/iris/iris_platform_common.h b/driv= ers/media/platform/qcom/iris/iris_platform_common.h index fdd40fd80178c4c66b37e392d07a0a62f492f108..6bc3a7975b04d612f6c89206eae= 95dac678695fc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_common.h +++ b/drivers/media/platform/qcom/iris/iris_platform_common.h @@ -35,6 +35,7 @@ enum pipe_type { =20 extern struct iris_platform_data sm8250_data; extern struct iris_platform_data sm8550_data; +extern struct iris_platform_data sm8650_data; =20 enum platform_clk_type { IRIS_AXI_CLK, diff --git a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c b/driv= ers/media/platform/qcom/iris/iris_platform_sm8550.c index 35d278996c430f2856d0fe59586930061a271c3e..d0f8fa960d53367023e41bc5807= ba3f8beae2efc 100644 --- a/drivers/media/platform/qcom/iris/iris_platform_sm8550.c +++ b/drivers/media/platform/qcom/iris/iris_platform_sm8550.c @@ -144,6 +144,10 @@ static const struct icc_info sm8550_icc_table[] =3D { =20 static const char * const sm8550_clk_reset_table[] =3D { "bus" }; =20 +static const char * const sm8650_clk_reset_table[] =3D { "bus", "core" }; + +static const char * const sm8650_controller_reset_table[] =3D { "xo" }; + static const struct bw_info sm8550_bw_table_dec[] =3D { { ((4096 * 2160) / 256) * 60, 1608000 }, { ((4096 * 2160) / 256) * 30, 826000 }, @@ -264,3 +268,63 @@ struct iris_platform_data sm8550_data =3D { .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), }; + +/* + * Shares most of SM8550 data except: + * - vpu_ops to iris_vpu33_ops + * - clk_rst_tbl to sm8650_clk_reset_table + * - controller_rst_tbl to sm8650_controller_reset_table + * - fwname to "qcom/vpu/vpu33_p4.mbn" + */ +struct iris_platform_data sm8650_data =3D { + .get_instance =3D iris_hfi_gen2_get_instance, + .init_hfi_command_ops =3D iris_hfi_gen2_command_ops_init, + .init_hfi_response_ops =3D iris_hfi_gen2_response_ops_init, + .vpu_ops =3D &iris_vpu33_ops, + .set_preset_registers =3D iris_set_sm8550_preset_registers, + .icc_tbl =3D sm8550_icc_table, + .icc_tbl_size =3D ARRAY_SIZE(sm8550_icc_table), + .clk_rst_tbl =3D sm8650_clk_reset_table, + .clk_rst_tbl_size =3D ARRAY_SIZE(sm8650_clk_reset_table), + .controller_rst_tbl =3D sm8650_controller_reset_table, + .controller_rst_tbl_size =3D ARRAY_SIZE(sm8650_controller_reset_table), + .bw_tbl_dec =3D sm8550_bw_table_dec, + .bw_tbl_dec_size =3D ARRAY_SIZE(sm8550_bw_table_dec), + .pmdomain_tbl =3D sm8550_pmdomain_table, + .pmdomain_tbl_size =3D ARRAY_SIZE(sm8550_pmdomain_table), + .opp_pd_tbl =3D sm8550_opp_pd_table, + .opp_pd_tbl_size =3D ARRAY_SIZE(sm8550_opp_pd_table), + .clk_tbl =3D sm8550_clk_table, + .clk_tbl_size =3D ARRAY_SIZE(sm8550_clk_table), + /* Upper bound of DMA address range */ + .dma_mask =3D 0xe0000000 - 1, + .fwname =3D "qcom/vpu/vpu33_p4.mbn", + .pas_id =3D IRIS_PAS_ID, + .inst_caps =3D &platform_inst_cap_sm8550, + .inst_fw_caps =3D inst_fw_cap_sm8550, + .inst_fw_caps_size =3D ARRAY_SIZE(inst_fw_cap_sm8550), + .tz_cp_config_data =3D &tz_cp_config_sm8550, + .core_arch =3D VIDEO_ARCH_LX, + .hw_response_timeout =3D HW_RESPONSE_TIMEOUT_VALUE, + .ubwc_config =3D &ubwc_config_sm8550, + .num_vpp_pipe =3D 4, + .max_session_count =3D 16, + .max_core_mbpf =3D ((8192 * 4352) / 256) * 2, + .input_config_params =3D + sm8550_vdec_input_config_params, + .input_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_input_config_params), + .output_config_params =3D + sm8550_vdec_output_config_params, + .output_config_params_size =3D + ARRAY_SIZE(sm8550_vdec_output_config_params), + .dec_input_prop =3D sm8550_vdec_subscribe_input_properties, + .dec_input_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_input_propertie= s), + .dec_output_prop =3D sm8550_vdec_subscribe_output_properties, + .dec_output_prop_size =3D ARRAY_SIZE(sm8550_vdec_subscribe_output_propert= ies), + + .dec_ip_int_buf_tbl =3D sm8550_dec_ip_int_buf_tbl, + .dec_ip_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_ip_int_buf_tbl), + .dec_op_int_buf_tbl =3D sm8550_dec_op_int_buf_tbl, + .dec_op_int_buf_tbl_size =3D ARRAY_SIZE(sm8550_dec_op_int_buf_tbl), +}; diff --git a/drivers/media/platform/qcom/iris/iris_probe.c b/drivers/media/= platform/qcom/iris/iris_probe.c index 4f8bce6e2002bffee4c93dcaaf6e52bf4e40992e..7cd8650fbe9c09598670530103e= 3d5edf32953e7 100644 --- a/drivers/media/platform/qcom/iris/iris_probe.c +++ b/drivers/media/platform/qcom/iris/iris_probe.c @@ -345,6 +345,10 @@ static const struct of_device_id iris_dt_match[] =3D { .data =3D &sm8250_data, }, #endif + { + .compatible =3D "qcom,sm8650-iris", + .data =3D &sm8650_data, + }, { }, }; MODULE_DEVICE_TABLE(of, iris_dt_match); --=20 2.34.1