From nobody Sat Feb 7 05:01:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A5C851917CD; Thu, 6 Mar 2025 07:12:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245171; cv=none; b=V7tJxsWA5I/8kLkkvg5ceOA765IGXaJeJx4SnTaOeqQlQKUC83cELDGnKec9m58Vq6WKZdsYsLt2UqDsIp9kwn3zK6y/jBQdU2Fo3gShR5TbW1P9ydyZ14vF4Uru6c7P8HSoRbBRP8kKxl8sV+BeU5zw5X1L2Ma5Uq25ceaTO78= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245171; c=relaxed/simple; bh=BfCpvXPQPn7mcskR6IEtxlwl46LOxQ6OOV0rkXcU5do=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=AHRhM8au6JZhcLhJ5Y+cBcRLe/8wbRmv2h0IzK0gnOWoCkj0v9wkvR5dQ4CzoBGeqA93mUs8UqevbB6kDWvpxO4YvtpCnzG/UES5wVg0FtTZiDWYejdv3Hay8eq1E1Z9NyNQUd3dO8OTsnb2AtkprIbhuic9k5xmwYgAyA2DV7A= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=FE8stspL; arc=none smtp.client-ip=192.198.163.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="FE8stspL" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741245170; x=1772781170; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=BfCpvXPQPn7mcskR6IEtxlwl46LOxQ6OOV0rkXcU5do=; b=FE8stspL8jmm79iAUz0l+IlwzYfLAQB2tcnmNfei8wXl681Few6sg7+U 5k7TxAx9inYKnIyGT1ElifhjsYPfaQv2P9ML3M+ma1Z6NaIFVjQ5HuUJy aBy42mL0mnsCrnjz+K0nq4OEhKMqldOF8knIOVZx6DfZZ+kf7cmCZRkye WoA5zPBFW8SJNv3DXcrtLC9QZtY9fQIrqdY3r+5XUwnyRjucVQphpWwNJ tzsttjLp6kVgZRvajIFGHuCcljaaeAwOe3itqd1gZHSEQHdJIkEcy6q38 dXF967VbmT0uuiSH5yr6rG8xyDkYI9HDtJIyZ3M337+vl9fMBB3cZ/5Gj w==; X-CSE-ConnectionGUID: 16BdQ/ZbSyeAaHUORHAR4g== X-CSE-MsgGUID: QRrWPt8FS3eh/LzrBGs7aQ== X-IronPort-AV: E=McAfee;i="6700,10204,11363"; a="41490161" X-IronPort-AV: E=Sophos;i="6.14,225,1736841600"; d="scan'208";a="41490161" Received: from fmviesa004.fm.intel.com ([10.60.135.144]) by fmvoesa112.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:12:49 -0800 X-CSE-ConnectionGUID: 2xfomYqyTUG2CkFXqS9P+w== X-CSE-MsgGUID: AWk+Tr2AQOybelNYBXIKMg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,225,1736841600"; d="scan'208";a="124032134" Received: from sho10-mobl1.amr.corp.intel.com (HELO desk) ([10.125.145.178]) by fmviesa004-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:12:48 -0800 Date: Wed, 5 Mar 2025 23:12:47 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v6 1/5] x86/cpu: Name CPU matching macro more generically (and shorten) Message-ID: <20250305-add-cpu-type-v6-1-4741735bcd75@linux.intel.com> X-Mailer: b4 0.14.1 References: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" To add cpu-type to the existing CPU matching infrastructure, the base macro X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE need to append _CPU_TYPE. This makes an already long name longer, and somewhat incomprehensible. To avoid this, rename the base macro to X86_MATCH_CPU. The macro name doesn't need to explicitly tell everything that it matches. The arguments to the macro already hints that. For consistency, use this base macro to define X86_MATCH_VFM and friends. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu_device_id.h | 101 ++++++++++---------------------= ---- 1 file changed, 29 insertions(+), 72 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cp= u_device_id.h index ba32e0f44cba..bb5acba69bd1 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -57,7 +57,7 @@ #define X86_CPU_ID_FLAG_ENTRY_VALID BIT(0) =20 /** - * X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE - Base macro for CPU match= ing + * X86_MATCH_CPU - Base macro for CPU matching * @_vendor: The vendor name, e.g. INTEL, AMD, HYGON, ..., ANY * The name is expanded to X86_VENDOR_@_vendor * @_family: The family number or X86_FAMILY_ANY @@ -74,19 +74,7 @@ * into another macro at the usage site for good reasons, then please * start this local macro with X86_MATCH to allow easy grepping. */ -#define X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(_vendor, _family, _mo= del, \ - _steppings, _feature, _data) { \ - .vendor =3D X86_VENDOR_##_vendor, \ - .family =3D _family, \ - .model =3D _model, \ - .steppings =3D _steppings, \ - .feature =3D _feature, \ - .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, \ - .driver_data =3D (unsigned long) _data \ -} - -#define X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE(_vendor, _family, _= model, \ - _steppings, _feature, _data) { \ +#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _dat= a) { \ .vendor =3D _vendor, \ .family =3D _family, \ .model =3D _model, \ @@ -106,13 +94,10 @@ * @_data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * The steppings arguments of X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE= () is - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature,= data) \ - X86_MATCH_VENDOR_FAM_MODEL_STEPPINGS_FEATURE(vendor, family, model, \ - X86_STEPPING_ANY, feature, data) +#define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature,= data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ + feature, data) =20 /** * X86_MATCH_VENDOR_FAM_FEATURE - Macro for matching vendor, family and CP= U feature @@ -123,13 +108,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, \ - X86_MODEL_ANY, feature, data) +#define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) =20 /** * X86_MATCH_VENDOR_FEATURE - Macro for matching vendor and CPU feature @@ -139,12 +121,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ - X86_MATCH_VENDOR_FAM_FEATURE(vendor, X86_FAMILY_ANY, feature, data) +#define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, X86_FAMILY_ANY, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) =20 /** * X86_MATCH_FEATURE - Macro for matching a CPU feature @@ -152,12 +132,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_FEATURE(feature, data) \ - X86_MATCH_VENDOR_FEATURE(ANY, feature, data) +#define X86_MATCH_FEATURE(feature, data) \ + X86_MATCH_CPU(X86_VENDOR_ANY, X86_FAMILY_ANY, X86_MODEL_ANY, \ + X86_STEPPING_ANY, feature, data) =20 /** * X86_MATCH_VENDOR_FAM_MODEL - Match vendor, family and model @@ -168,13 +146,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments of X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set to wildcards. */ -#define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ - X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, \ - X86_FEATURE_ANY, data) +#define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ + X86_FEATURE_ANY, data) =20 /** * X86_MATCH_VENDOR_FAM - Match vendor and family @@ -184,12 +159,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is casted to unsigned long internally. - * - * All other missing arguments to X86_MATCH_VENDOR_FAM_MODEL_FEATURE() are - * set of wildcards. */ -#define X86_MATCH_VENDOR_FAM(vendor, family, data) \ - X86_MATCH_VENDOR_FAM_MODEL(vendor, family, X86_MODEL_ANY, data) +#define X86_MATCH_VENDOR_FAM(vendor, family, data) \ + X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ + X86_STEPPING_ANY, X86_FEATURE_ANY, data) =20 /** * X86_MATCH_VFM - Match encoded vendor/family/model @@ -197,15 +170,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * Stepping and feature are set to wildcards */ -#define X86_MATCH_VFM(vfm, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) +#define X86_MATCH_VFM(vfm, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, X86_FEATURE_ANY, data) =20 #define __X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins) /** @@ -215,16 +183,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * feature is set to wildcard */ -#define X86_MATCH_VFM_STEPS(vfm, min_step, max_step, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - __X86_STEPPINGS(min_step, max_step), \ - X86_FEATURE_ANY, data) +#define X86_MATCH_VFM_STEPS(vfm, min_step, max_step, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + __X86_STEPPINGS(min_step, max_step), X86_FEATURE_ANY, data) =20 /** * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature @@ -233,15 +195,10 @@ * @data: Driver specific data or NULL. The internal storage * format is unsigned long. The supplied value, pointer * etc. is cast to unsigned long internally. - * - * Steppings is set to wildcard */ -#define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ - X86_MATCH_VENDORID_FAM_MODEL_STEPPINGS_FEATURE( \ - VFM_VENDOR(vfm), \ - VFM_FAMILY(vfm), \ - VFM_MODEL(vfm), \ - X86_STEPPING_ANY, feature, data) +#define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, feature, data) =20 extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *mat= ch); extern bool x86_match_min_microcode_rev(const struct x86_cpu_id *table); --=20 2.34.1 From nobody Sat Feb 7 05:01:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3EA501917CD; Thu, 6 Mar 2025 07:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245187; cv=none; b=p84mK9gWuuwJ+IE++y4YHLEalkKFj9qsbfzcEopLjeKpjeqlmkBGYEzmLjf5HHrphLXw8FldAiIy1WLZuUCG+6dnRMHslEpaDdiw9ojY/nCH8JyHH1XVyLi9j0lsiXVf5jedtW4OrIqc6tpeJn1aRdNKkOSf1AMp5BwcfWXWw6Y= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245187; c=relaxed/simple; bh=2jCaiISqvFS4dZP9GtAMqBBgeQ1YQSjF5Bhg73fRmQo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=UoFesVkvFNpyWVylnI6SuPxiiSxpjRmN2QxRWsNv+YojmxS3p/oOUwoRRihvC7rmyBvlZCJgFCcY0JW07FP69wThxMaLA+WHeRw2uwnt3veODGL2u5AyYFlHbYt54OdJZTANl5PP3Uf9oSnGbiElADkWVmRvUeCvQzsDhS5m8Ik= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=DTw7k/nj; arc=none smtp.client-ip=198.175.65.13 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="DTw7k/nj" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741245186; x=1772781186; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=2jCaiISqvFS4dZP9GtAMqBBgeQ1YQSjF5Bhg73fRmQo=; b=DTw7k/nj099P7WBlNYHvk9xMUxp7dLG7oAM/xPRFLBPvL1yQFb2jfeKb b3j5BTuEdwZvXai1AGFs2+foewwYvOAf19VtG9elrwJb/8u5yJxT3cCBU jdKKlpbEGYP2/Ta+jXCwofRiRQHGCLfeqUnDGGatCjyDq4s2SpH/GAsEz nJD1VFtBmyWN42wRenTE0arGFzg/Rk3aWJMXw1oLlJD0DCKo1aHXDSFn6 8jPLRDAdOccJXLXY4LKY8L3oj98aPaZx7rn0Bd8rpoyobrlRMbT5SRFnN kCgYR3Le26g19Zb2VBaJQJyt3SGHgmV6vV36Xy+wK5BY4kOPDQ7Y8ooMk g==; X-CSE-ConnectionGUID: p3I2merSTXGk+IiztWRECg== X-CSE-MsgGUID: sAKex9MQREyK2ETO9kaQ4g== X-IronPort-AV: E=McAfee;i="6700,10204,11363"; a="53225410" X-IronPort-AV: E=Sophos;i="6.14,225,1736841600"; d="scan'208";a="53225410" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:13:06 -0800 X-CSE-ConnectionGUID: Av2EsDcNSzeMLFeM4zrgkw== X-CSE-MsgGUID: 8EsCOCMuT/eBtwSf4HTCew== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="149868458" Received: from sho10-mobl1.amr.corp.intel.com (HELO desk) ([10.125.145.178]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:13:04 -0800 Date: Wed, 5 Mar 2025 23:13:03 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v6 2/5] x86/cpu: Add cpu_type to struct x86_cpu_id Message-ID: <20250305-add-cpu-type-v6-2-4741735bcd75@linux.intel.com> X-Mailer: b4 0.14.1 References: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" In addition to matching vendor/family/model/feature, for hybrid variants it is required to also match cpu-type also. For example some CPU vulnerabilities like RFDS only affects a specific cpu-type. To be able to also match CPUs based on their type, add a new field cpu_type to struct x86_cpu_id which is used by the CPU-matching tables. Introduce X86_CPU_TYPE_ANY for the cases that don't care about the cpu-type. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/include/asm/cpu_device_id.h | 34 ++++++++++++++++++++++++--------= -- include/linux/mod_devicetable.h | 2 ++ 2 files changed, 26 insertions(+), 10 deletions(-) diff --git a/arch/x86/include/asm/cpu_device_id.h b/arch/x86/include/asm/cp= u_device_id.h index bb5acba69bd1..20dd91146e75 100644 --- a/arch/x86/include/asm/cpu_device_id.h +++ b/arch/x86/include/asm/cpu_device_id.h @@ -74,13 +74,14 @@ * into another macro at the usage site for good reasons, then please * start this local macro with X86_MATCH to allow easy grepping. */ -#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _dat= a) { \ +#define X86_MATCH_CPU(_vendor, _family, _model, _steppings, _feature, _cpu= _type, _data) { \ .vendor =3D _vendor, \ .family =3D _family, \ .model =3D _model, \ .steppings =3D _steppings, \ .feature =3D _feature, \ .flags =3D X86_CPU_ID_FLAG_ENTRY_VALID, \ + .cpu_type =3D _cpu_type, \ .driver_data =3D (unsigned long) _data \ } =20 @@ -97,7 +98,7 @@ */ #define X86_MATCH_VENDOR_FAM_MODEL_FEATURE(vendor, family, model, feature,= data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ - feature, data) + feature, X86_CPU_TYPE_ANY, data) =20 /** * X86_MATCH_VENDOR_FAM_FEATURE - Macro for matching vendor, family and CP= U feature @@ -111,7 +112,7 @@ */ #define X86_MATCH_VENDOR_FAM_FEATURE(vendor, family, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) =20 /** * X86_MATCH_VENDOR_FEATURE - Macro for matching vendor and CPU feature @@ -124,7 +125,7 @@ */ #define X86_MATCH_VENDOR_FEATURE(vendor, feature, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, X86_FAMILY_ANY, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) =20 /** * X86_MATCH_FEATURE - Macro for matching a CPU feature @@ -135,7 +136,7 @@ */ #define X86_MATCH_FEATURE(feature, data) \ X86_MATCH_CPU(X86_VENDOR_ANY, X86_FAMILY_ANY, X86_MODEL_ANY, \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) =20 /** * X86_MATCH_VENDOR_FAM_MODEL - Match vendor, family and model @@ -149,7 +150,7 @@ */ #define X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, model, X86_STEPPING_ANY, \ - X86_FEATURE_ANY, data) + X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) =20 /** * X86_MATCH_VENDOR_FAM - Match vendor and family @@ -162,7 +163,7 @@ */ #define X86_MATCH_VENDOR_FAM(vendor, family, data) \ X86_MATCH_CPU(X86_VENDOR_##vendor, family, X86_MODEL_ANY, \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) + X86_STEPPING_ANY, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) =20 /** * X86_MATCH_VFM - Match encoded vendor/family/model @@ -173,7 +174,7 @@ */ #define X86_MATCH_VFM(vfm, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - X86_STEPPING_ANY, X86_FEATURE_ANY, data) + X86_STEPPING_ANY, X86_FEATURE_ANY, X86_CPU_TYPE_ANY, data) =20 #define __X86_STEPPINGS(mins, maxs) GENMASK(maxs, mins) /** @@ -186,7 +187,8 @@ */ #define X86_MATCH_VFM_STEPS(vfm, min_step, max_step, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - __X86_STEPPINGS(min_step, max_step), X86_FEATURE_ANY, data) + __X86_STEPPINGS(min_step, max_step), X86_FEATURE_ANY, \ + X86_CPU_TYPE_ANY, data) =20 /** * X86_MATCH_VFM_FEATURE - Match encoded vendor/family/model/feature @@ -198,7 +200,19 @@ */ #define X86_MATCH_VFM_FEATURE(vfm, feature, data) \ X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ - X86_STEPPING_ANY, feature, data) + X86_STEPPING_ANY, feature, X86_CPU_TYPE_ANY, data) + +/** + * X86_MATCH_VFM_CPU_TYPE - Match encoded vendor/family/model/cpu-type + * @vfm: Encoded 8-bits each for vendor, family, model + * @cpu_type: CPU type e.g. P-core, E-core on Intel + * @data: Driver specific data or NULL. The internal storage + * format is unsigned long. The supplied value, pointer + * etc. is cast to unsigned long internally. + */ +#define X86_MATCH_VFM_CPU_TYPE(vfm, cpu_type, data) \ + X86_MATCH_CPU(VFM_VENDOR(vfm), VFM_FAMILY(vfm), VFM_MODEL(vfm), \ + X86_STEPPING_ANY, X86_FEATURE_ANY, cpu_type, data) =20 extern const struct x86_cpu_id *x86_match_cpu(const struct x86_cpu_id *mat= ch); extern bool x86_match_min_microcode_rev(const struct x86_cpu_id *table); diff --git a/include/linux/mod_devicetable.h b/include/linux/mod_devicetabl= e.h index d67614f7b7f1..18e996acb49a 100644 --- a/include/linux/mod_devicetable.h +++ b/include/linux/mod_devicetable.h @@ -692,6 +692,7 @@ struct x86_cpu_id { __u16 feature; /* bit index */ /* Solely for kernel-internal use: DO NOT EXPORT to userspace! */ __u16 flags; + __u8 cpu_type; kernel_ulong_t driver_data; }; =20 @@ -703,6 +704,7 @@ struct x86_cpu_id { #define X86_STEP_MIN 0 #define X86_STEP_MAX 0xf #define X86_FEATURE_ANY 0 /* Same as FPU, you can't test for that */ +#define X86_CPU_TYPE_ANY 0 =20 /* * Generic table type for matching CPU features. --=20 2.34.1 From nobody Sat Feb 7 05:01:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.12]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 69E471917CD; Thu, 6 Mar 2025 07:13:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.12 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245203; cv=none; b=tHPSaoP3TVf+x8XrFbvPn/Thp2gXmOML1o/Nsqdz4te1XTFQOCe9yBefkhOTAHNPrgu1omrgV+lSF07j0ey0Uc53ZX+d1Jal8nF5WiFYCwsEIAPbCaJ7xbX9TV973qRWJLl8Mma4pVRtv5VSeYJXuaX6FA9QWq7DT1vC5ofjfhs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245203; c=relaxed/simple; bh=iJvFa/7K5dAtQaIXR9nA65sdMTeAt66cxKMWMtQuwTo=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=IGqqNtMO1TUFMGF03z1n270L8n2L0SndI0Csfl0wdyyoJgU6HdcBn5oBnuGWbMH18miKXdSchl7nLmFW9W3NGrtNspF0X0KUzyKr24X882kDXWyGgC8hH65tNpO31EL3NAQsBnmVQYB11U0Lt5u8xTS4UG1Z149kEn8UonouX/I= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=jeUEHFPw; arc=none smtp.client-ip=198.175.65.12 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="jeUEHFPw" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741245202; x=1772781202; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=iJvFa/7K5dAtQaIXR9nA65sdMTeAt66cxKMWMtQuwTo=; b=jeUEHFPwvZUNjGWtdfq3X4B2Eo/bpadKPZiDGjduMCoCqoCFveWK/4q6 uk244eV8eJWY3DGaH1Cojma4goViyrJM5ZSJNq6bc7B5wEHdqsfgCAiBx TA3fQxGAU3sLwERk1a0nv5KU5hCuWEK/Up5sR6mw5Me9RGF+TRyYEazlz 6t4Xnah+W8jSZVphFWAbpe8eDugfZTOgWjcmP+KXUlYGzY627aUARgeTz sLTzN6o4NplxG5Vg3GUSw52u7bAlIvwa1xo/MolzH4461xXkRGgIrjROq zVUrB4PYGQiMQI9c5MIXemUGfrTKu8rY+dxKJOf4gbY51EjY5OOBoiLpD w==; X-CSE-ConnectionGUID: JSyzCGXNT6Wo7YRoWeYung== X-CSE-MsgGUID: 6Wd3s4pxS92+96f3QTDiuA== X-IronPort-AV: E=McAfee;i="6700,10204,11363"; a="53640941" X-IronPort-AV: E=Sophos;i="6.14,225,1736841600"; d="scan'208";a="53640941" Received: from fmviesa010.fm.intel.com ([10.60.135.150]) by orvoesa104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:13:22 -0800 X-CSE-ConnectionGUID: QXHgulKdQmWWAsDZeuB7Ag== X-CSE-MsgGUID: hL/THvytTMWRyj5D40sDgw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,225,1736841600"; d="scan'208";a="119442084" Received: from sho10-mobl1.amr.corp.intel.com (HELO desk) ([10.125.145.178]) by fmviesa010-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:13:20 -0800 Date: Wed, 5 Mar 2025 23:13:20 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v6 3/5] x86/cpu: Update x86_match_cpu() to also use cpu-type Message-ID: <20250305-add-cpu-type-v6-3-4741735bcd75@linux.intel.com> X-Mailer: b4 0.14.1 References: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Non-hybrid CPU variants that share the same Family/Model could be differentiated by their cpu-type. x86_match_cpu() currently does not use cpu-type for CPU matching. Dave Hansen suggested to use below conditions to match CPU-type: 1. If CPU_TYPE_ANY (the wildcard), then matched 2. If hybrid, then matched 3. If !hybrid, look at the boot CPU and compare the cpu-type to determine if it is a match. This special case for hybrid systems allows more compact vulnerability list. Imagine that "Haswell" CPUs might or might not be hybrid and that only Atom cores are vulnerable to Meltdown. That means there are three possibilities: 1. P-core only 2. Atom only 3. Atom + P-core (aka. hybrid) One might be tempted to code up the vulnerability list like this: MATCH( HASWELL, X86_FEATURE_HYBRID, MELTDOWN) MATCH_TYPE(HASWELL, ATOM, MELTDOWN) Logically, this matches #2 and #3. But that's a little silly. You would only ask for the "ATOM" match in cases where there *WERE* hybrid cores in play. You shouldn't have to _also_ ask for hybrid cores explicitly. In short, assume that processors that enumerate Hybrid=3D=3D1 have a vulnerable core type. Update x86_match_cpu() to also match cpu-type. Also treat hybrid systems as special, and match them to any cpu-type. Suggested-by: Dave Hansen Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/match.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+) diff --git a/arch/x86/kernel/cpu/match.c b/arch/x86/kernel/cpu/match.c index 4f3c65429f82..4b052860b774 100644 --- a/arch/x86/kernel/cpu/match.c +++ b/arch/x86/kernel/cpu/match.c @@ -5,6 +5,34 @@ #include #include =20 +/** + * x86_match_vendor_cpu_type - helper function to match the hardware defin= ed + * cpu-type for a single entry in the x86_cpu_= id + * table. Note, this function does not match t= he + * generic cpu-types TOPO_CPU_TYPE_EFFICIENCY = and + * TOPO_CPU_TYPE_PERFORMANCE. + * @c: Pointer to the cpuinfo_x86 structure of the CPU to match. + * @m: Pointer to the x86_cpu_id entry to match against. + * + * Return: true if the cpu-type matches, false otherwise. + */ +static bool x86_match_vendor_cpu_type(struct cpuinfo_x86 *c, const struct = x86_cpu_id *m) +{ + if (m->cpu_type =3D=3D X86_CPU_TYPE_ANY) + return true; + + /* Hybrid CPUs are special, they are assumed to match all cpu-types */ + if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) + return true; + + if (c->x86_vendor =3D=3D X86_VENDOR_INTEL) + return m->cpu_type =3D=3D c->topo.intel_type; + if (c->x86_vendor =3D=3D X86_VENDOR_AMD) + return m->cpu_type =3D=3D c->topo.amd_type; + + return false; +} + /** * x86_match_cpu - match current CPU against an array of x86_cpu_ids * @match: Pointer to array of x86_cpu_ids. Last entry terminated with @@ -50,6 +78,8 @@ const struct x86_cpu_id *x86_match_cpu(const struct x86_c= pu_id *match) continue; if (m->feature !=3D X86_FEATURE_ANY && !cpu_has(c, m->feature)) continue; + if (!x86_match_vendor_cpu_type(c, m)) + continue; return m; } return NULL; --=20 2.34.1 From nobody Sat Feb 7 05:01:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.18]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CADF81A9B46; Thu, 6 Mar 2025 07:13:38 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.18 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245220; cv=none; b=hkuf4oa88FSuIo0GVVRByY9LF0ohflhpHpb+SV9V6x0PR6iZaDpRc/g/HonE7yIisEXr3YH9wG//fUUXURGULWLqwGBqleGMzgelRKjFdsztSRDENiadQiHBkvYYL8jzXKNpf9CpEuunmJt+a3tawtoaP8cxtd9t4H5DDWc9FRg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245220; c=relaxed/simple; bh=wkRRATqOnJg4W7qQZt+oYerosayasUUpjZqPgwxgbig=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=vA5VSCkclpKCLNlIvEDoNYhscl4vtAQD1WuaVCpFKHqlaPSHXlBl63F1+bc/+z3CO8nVoWfqY6kBkcP47m4IoC1dDbZtdMcs3ESeS7o28/GbfOuKgFvctdgrHJDFHfR3FAwQ8/LaM55++8zDDjcLCGSN/mKY8pI2KeDjM8En/AI= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com; spf=none smtp.mailfrom=linux.intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=mAzjtrME; arc=none smtp.client-ip=198.175.65.18 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; spf=none smtp.mailfrom=linux.intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="mAzjtrME" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1741245219; x=1772781219; h=date:from:to:cc:subject:message-id:references: mime-version:in-reply-to; bh=wkRRATqOnJg4W7qQZt+oYerosayasUUpjZqPgwxgbig=; b=mAzjtrME5AiIZWwRB13l3Jcfm38drGm4XbdArVuInS5QQq1/+1K7Lu83 6b4ULD1pT9vATsq9FTuljZkpCjz5imZhaNvoDzUkzKfEW1ryIlB7YH9cz aK3+p5lLPKlkdDvQiJkOpGW50onMIcBYGzjpuyqrDHlXqMFKhXhYTi91s Q5HC8MfhpQ/tW5Y+i8FYLmbDs56SR72NGpMx/3BkcvgINGW7QMI7PUyby wkldpdCjviH8A+1gvRKCRxJwSsRVcAisUGXcG5Dsl6d6/BtaN7hgx1Bjg 02ZAUn1zYg44zrVYEyjuqhgbLX+vuv5FIIP+Y+DGpY/t0qMoCJeelRRUv Q==; X-CSE-ConnectionGUID: 8T/YuTE2Q+aMXIshBOuzuw== X-CSE-MsgGUID: 3kkVIoKHSPi+ARgjdVKoFw== X-IronPort-AV: E=McAfee;i="6700,10204,11363"; a="42439688" X-IronPort-AV: E=Sophos;i="6.14,225,1736841600"; d="scan'208";a="42439688" Received: from fmviesa007.fm.intel.com ([10.60.135.147]) by orvoesa110.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:13:39 -0800 X-CSE-ConnectionGUID: flU7gdDwQt+E+KtPYXa+kg== X-CSE-MsgGUID: Z0QLe2zpS5y4xGn0ydPE6w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.14,225,1736841600"; d="scan'208";a="118950180" Received: from sho10-mobl1.amr.corp.intel.com (HELO desk) ([10.125.145.178]) by fmviesa007-auth.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:13:35 -0800 Date: Wed, 5 Mar 2025 23:13:36 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v6 4/5] x86/bugs: Declutter vulnerable CPU list Message-ID: <20250305-add-cpu-type-v6-4-4741735bcd75@linux.intel.com> X-Mailer: b4 0.14.1 References: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The affected processor table has a lot of repetition and redundant information that can be omitted for brevity. Like: VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS), can easily be simplified to: VULNBL_INTEL(IVYBRIDGE, SRBDS), Apply this to all the entries in the affected processor table. No functional change. Disassembly of cpu_vuln_blacklist: objdump -j .init.data --disassemble=3Dcpu_vuln_blacklist vmlinux doesn't show any difference before and after the change. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- arch/x86/kernel/cpu/common.c | 143 ++++++++++++++++++++++-----------------= ---- 1 file changed, 73 insertions(+), 70 deletions(-) diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 5f81c553e733..9d41f8f7267a 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1125,7 +1125,7 @@ static void identify_cpu_without_cpuid(struct cpuinfo= _x86 *c) X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, whitelist) =20 #define VULNWL_INTEL(vfm, whitelist) \ - X86_MATCH_VFM(vfm, whitelist) + X86_MATCH_VFM(INTEL_##vfm, whitelist) =20 #define VULNWL_AMD(family, whitelist) \ VULNWL(AMD, family, X86_MODEL_ANY, whitelist) @@ -1142,32 +1142,32 @@ static const __initconst struct x86_cpu_id cpu_vuln= _whitelist[] =3D { VULNWL(VORTEX, 6, X86_MODEL_ANY, NO_SPECULATION), =20 /* Intel Family 6 */ - VULNWL_INTEL(INTEL_TIGERLAKE, NO_MMIO), - VULNWL_INTEL(INTEL_TIGERLAKE_L, NO_MMIO), - VULNWL_INTEL(INTEL_ALDERLAKE, NO_MMIO), - VULNWL_INTEL(INTEL_ALDERLAKE_L, NO_MMIO), + VULNWL_INTEL(TIGERLAKE, NO_MMIO), + VULNWL_INTEL(TIGERLAKE_L, NO_MMIO), + VULNWL_INTEL(ALDERLAKE, NO_MMIO), + VULNWL_INTEL(ALDERLAKE_L, NO_MMIO), =20 - VULNWL_INTEL(INTEL_ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHI= T), - VULNWL_INTEL(INTEL_ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL_TABLET, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SALTWELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_BONNELL, NO_SPECULATION | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_BONNELL_MID, NO_SPECULATION | NO_ITLB_MULTIHIT), =20 - VULNWL_INTEL(INTEL_ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SW= APGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_= SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | N= O_SWAPGS | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPG= S | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPG= S | NO_ITLB_MULTIHIT), - VULNWL_INTEL(INTEL_XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPG= S | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS = | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_D, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPG= S | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_MID, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAP= GS | NO_ITLB_MULTIHIT), + VULNWL_INTEL(ATOM_AIRMONT, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | N= O_ITLB_MULTIHIT), + VULNWL_INTEL(XEON_PHI_KNL, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | N= O_ITLB_MULTIHIT), + VULNWL_INTEL(XEON_PHI_KNM, NO_SSB | NO_L1TF | MSBDS_ONLY | NO_SWAPGS | N= O_ITLB_MULTIHIT), =20 - VULNWL_INTEL(INTEL_CORE_YONAH, NO_SSB), + VULNWL_INTEL(CORE_YONAH, NO_SSB), =20 - VULNWL_INTEL(INTEL_ATOM_SILVERMONT_MID2,NO_SSB | NO_L1TF | NO_SWAPGS | NO= _ITLB_MULTIHIT | MSBDS_ONLY), - VULNWL_INTEL(INTEL_ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITL= B_MULTIHIT), + VULNWL_INTEL(ATOM_SILVERMONT_MID2, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB= _MULTIHIT | MSBDS_ONLY), + VULNWL_INTEL(ATOM_AIRMONT_NP, NO_SSB | NO_L1TF | NO_SWAPGS | NO_ITLB_MUL= TIHIT), =20 - VULNWL_INTEL(INTEL_ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_= MULTIHIT | NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITL= B_MULTIHIT | NO_MMIO), - VULNWL_INTEL(INTEL_ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_= ITLB_MULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_GOLDMONT, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MULTI= HIT | NO_MMIO), + VULNWL_INTEL(ATOM_GOLDMONT_D, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_MUL= TIHIT | NO_MMIO), + VULNWL_INTEL(ATOM_GOLDMONT_PLUS, NO_MDS | NO_L1TF | NO_SWAPGS | NO_ITLB_M= ULTIHIT | NO_MMIO | NO_EIBRS_PBRSB), =20 /* * Technically, swapgs isn't serializing on AMD (despite it previously @@ -1177,9 +1177,9 @@ static const __initconst struct x86_cpu_id cpu_vuln_w= hitelist[] =3D { * good enough for our purposes. */ =20 - VULNWL_INTEL(INTEL_ATOM_TREMONT, NO_EIBRS_PBRSB), - VULNWL_INTEL(INTEL_ATOM_TREMONT_L, NO_EIBRS_PBRSB), - VULNWL_INTEL(INTEL_ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT, NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT_L, NO_EIBRS_PBRSB), + VULNWL_INTEL(ATOM_TREMONT_D, NO_ITLB_MULTIHIT | NO_EIBRS_PBRSB), =20 /* AMD Family 0xf - 0x12 */ VULNWL_AMD(0x0f, NO_MELTDOWN | NO_SSB | NO_L1TF | NO_MDS | NO_SWAPGS | NO= _ITLB_MULTIHIT | NO_MMIO | NO_BHI), @@ -1200,8 +1200,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_= whitelist[] =3D { #define VULNBL(vendor, family, model, blacklist) \ X86_MATCH_VENDOR_FAM_MODEL(vendor, family, model, blacklist) =20 +#define VULNBL_INTEL(vfm, issues) \ + VULNBL_INTEL_STEPS(vfm, X86_STEP_MAX, issues) + #define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \ - X86_MATCH_VFM_STEPS(vfm, X86_STEP_MIN, max_stepping, issues) + X86_MATCH_VFM_STEPS(INTEL_##vfm, X86_STEP_MIN, max_stepping, issues) =20 #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) @@ -1226,50 +1229,50 @@ static const __initconst struct x86_cpu_id cpu_vuln= _whitelist[] =3D { #define RFDS BIT(7) =20 static const struct x86_cpu_id cpu_vuln_blacklist[] __initconst =3D { - VULNBL_INTEL_STEPS(INTEL_IVYBRIDGE, X86_STEP_MAX, SRBDS), - VULNBL_INTEL_STEPS(INTEL_HASWELL, X86_STEP_MAX, SRBDS), - VULNBL_INTEL_STEPS(INTEL_HASWELL_L, X86_STEP_MAX, SRBDS), - VULNBL_INTEL_STEPS(INTEL_HASWELL_G, X86_STEP_MAX, SRBDS), - VULNBL_INTEL_STEPS(INTEL_HASWELL_X, X86_STEP_MAX, MMIO), - VULNBL_INTEL_STEPS(INTEL_BROADWELL_D, X86_STEP_MAX, MMIO), - VULNBL_INTEL_STEPS(INTEL_BROADWELL_G, X86_STEP_MAX, SRBDS), - VULNBL_INTEL_STEPS(INTEL_BROADWELL_X, X86_STEP_MAX, MMIO), - VULNBL_INTEL_STEPS(INTEL_BROADWELL, X86_STEP_MAX, SRBDS), - VULNBL_INTEL_STEPS(INTEL_SKYLAKE_X, X86_STEP_MAX, MMIO | RETBLEED | = GDS), - VULNBL_INTEL_STEPS(INTEL_SKYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED | = GDS | SRBDS), - VULNBL_INTEL_STEPS(INTEL_SKYLAKE, X86_STEP_MAX, MMIO | RETBLEED | GD= S | SRBDS), - VULNBL_INTEL_STEPS(INTEL_KABYLAKE_L, X86_STEP_MAX, MMIO | RETBLEED |= GDS | SRBDS), - VULNBL_INTEL_STEPS(INTEL_KABYLAKE, X86_STEP_MAX, MMIO | RETBLEED | G= DS | SRBDS), - VULNBL_INTEL_STEPS(INTEL_CANNONLAKE_L, X86_STEP_MAX, RETBLEED), - VULNBL_INTEL_STEPS(INTEL_ICELAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS |= RETBLEED | GDS), - VULNBL_INTEL_STEPS(INTEL_ICELAKE_D, X86_STEP_MAX, MMIO | GDS), - VULNBL_INTEL_STEPS(INTEL_ICELAKE_X, X86_STEP_MAX, MMIO | GDS), - VULNBL_INTEL_STEPS(INTEL_COMETLAKE, X86_STEP_MAX, MMIO | MMIO_SBDS |= RETBLEED | GDS), - VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, 0x0, MMIO | RETBLEED), - VULNBL_INTEL_STEPS(INTEL_COMETLAKE_L, X86_STEP_MAX, MMIO | MMIO_SBDS= | RETBLEED | GDS), - VULNBL_INTEL_STEPS(INTEL_TIGERLAKE_L, X86_STEP_MAX, GDS), - VULNBL_INTEL_STEPS(INTEL_TIGERLAKE, X86_STEP_MAX, GDS), - VULNBL_INTEL_STEPS(INTEL_LAKEFIELD, X86_STEP_MAX, MMIO | MMIO_SBDS |= RETBLEED), - VULNBL_INTEL_STEPS(INTEL_ROCKETLAKE, X86_STEP_MAX, MMIO | RETBLEED |= GDS), - VULNBL_INTEL_STEPS(INTEL_ALDERLAKE, X86_STEP_MAX, RFDS), - VULNBL_INTEL_STEPS(INTEL_ALDERLAKE_L, X86_STEP_MAX, RFDS), - VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE, X86_STEP_MAX, RFDS), - VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_P, X86_STEP_MAX, RFDS), - VULNBL_INTEL_STEPS(INTEL_RAPTORLAKE_S, X86_STEP_MAX, RFDS), - VULNBL_INTEL_STEPS(INTEL_ATOM_GRACEMONT, X86_STEP_MAX, RFDS), - VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT, X86_STEP_MAX, MMIO | MMIO_SBD= S | RFDS), - VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_D, X86_STEP_MAX, MMIO | RFDS), - VULNBL_INTEL_STEPS(INTEL_ATOM_TREMONT_L, X86_STEP_MAX, MMIO | MMIO_SB= DS | RFDS), - VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT, X86_STEP_MAX, RFDS), - VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_D, X86_STEP_MAX, RFDS), - VULNBL_INTEL_STEPS(INTEL_ATOM_GOLDMONT_PLUS, X86_STEP_MAX, RFDS), - - VULNBL_AMD(0x15, RETBLEED), - VULNBL_AMD(0x16, RETBLEED), - VULNBL_AMD(0x17, RETBLEED | SMT_RSB | SRSO), - VULNBL_HYGON(0x18, RETBLEED | SMT_RSB | SRSO), - VULNBL_AMD(0x19, SRSO), - VULNBL_AMD(0x1a, SRSO), + VULNBL_INTEL( IVYBRIDGE, SRBDS), + VULNBL_INTEL( HASWELL, SRBDS), + VULNBL_INTEL( HASWELL_L, SRBDS), + VULNBL_INTEL( HASWELL_G, SRBDS), + VULNBL_INTEL( HASWELL_X, MMIO), + VULNBL_INTEL( BROADWELL_D, MMIO), + VULNBL_INTEL( BROADWELL_G, SRBDS), + VULNBL_INTEL( BROADWELL_X, MMIO), + VULNBL_INTEL( BROADWELL, SRBDS), + VULNBL_INTEL( SKYLAKE_X, MMIO | RETBLEED | GDS), + VULNBL_INTEL( SKYLAKE_L, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( SKYLAKE, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( KABYLAKE_L, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( KABYLAKE, MMIO | RETBLEED | GDS | SRBDS), + VULNBL_INTEL( CANNONLAKE_L, RETBLEED), + VULNBL_INTEL( ICELAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL( ICELAKE_D, MMIO | GDS), + VULNBL_INTEL( ICELAKE_X, MMIO | GDS), + VULNBL_INTEL( COMETLAKE, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL_STEPS( COMETLAKE_L, 0x0, MMIO | RETBLEED), + VULNBL_INTEL( COMETLAKE_L, MMIO | MMIO_SBDS | RETBLEED | GDS), + VULNBL_INTEL( TIGERLAKE_L, GDS), + VULNBL_INTEL( TIGERLAKE, GDS), + VULNBL_INTEL( LAKEFIELD, MMIO | MMIO_SBDS | RETBLEED), + VULNBL_INTEL( ROCKETLAKE, MMIO | RETBLEED | GDS), + VULNBL_INTEL( ALDERLAKE, RFDS), + VULNBL_INTEL( ALDERLAKE_L, RFDS), + VULNBL_INTEL( RAPTORLAKE, RFDS), + VULNBL_INTEL( RAPTORLAKE_P, RFDS), + VULNBL_INTEL( RAPTORLAKE_S, RFDS), + VULNBL_INTEL( ATOM_GRACEMONT, RFDS), + VULNBL_INTEL( ATOM_TREMONT, MMIO | MMIO_SBDS | RFDS), + VULNBL_INTEL( ATOM_TREMONT_D, MMIO | RFDS), + VULNBL_INTEL( ATOM_TREMONT_L, MMIO | MMIO_SBDS | RFDS), + VULNBL_INTEL( ATOM_GOLDMONT, RFDS), + VULNBL_INTEL( ATOM_GOLDMONT_D, RFDS), + VULNBL_INTEL( ATOM_GOLDMONT_PLUS, RFDS), + + VULNBL_AMD( 0x15, RETBLEED), + VULNBL_AMD( 0x16, RETBLEED), + VULNBL_AMD( 0x17, RETBLEED | SMT_RSB | SRSO), + VULNBL_HYGON( 0x18, RETBLEED | SMT_RSB | SRSO), + VULNBL_AMD( 0x19, SRSO), + VULNBL_AMD( 0x1a, SRSO), {} }; =20 --=20 2.34.1 From nobody Sat Feb 7 05:01:43 2026 Received: from mgamail.intel.com (mgamail.intel.com [198.175.65.13]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7CB231A9B46; Thu, 6 Mar 2025 07:14:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.175.65.13 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741245243; cv=none; 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a="53225504" X-IronPort-AV: E=Sophos;i="6.14,225,1736841600"; d="scan'208";a="53225504" Received: from fmviesa001.fm.intel.com ([10.60.135.141]) by orvoesa105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:13:55 -0800 X-CSE-ConnectionGUID: a4bHtl76Sr+sDrcuO7l2UA== X-CSE-MsgGUID: 3EgSTkWsTa+LxLjhUh4rJg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.12,224,1728975600"; d="scan'208";a="149869248" Received: from sho10-mobl1.amr.corp.intel.com (HELO desk) ([10.125.145.178]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 05 Mar 2025 23:13:53 -0800 Date: Wed, 5 Mar 2025 23:13:52 -0800 From: Pawan Gupta To: Thomas Gleixner , Ingo Molnar , Borislav Petkov , Dave Hansen , x86@kernel.org Cc: daniel.sneddon@linux.intel.com, tony.luck@intel.com, linux-kernel@vger.kernel.org, linux-pm@vger.kernel.org, linux-perf-users@vger.kernel.org, Josh Poimboeuf , Srinivas Pandruvada , "Rafael J. Wysocki" , Ricardo Neri , "Liang, Kan" , Andrew Cooper , Brice Goglin , Mario Limonciello , Perry Yuan , Dapeng Mi Subject: [PATCH v6 5/5] x86/rfds: Exclude P-only parts from the RFDS affected list Message-ID: <20250305-add-cpu-type-v6-5-4741735bcd75@linux.intel.com> X-Mailer: b4 0.14.1 References: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20250305-add-cpu-type-v6-0-4741735bcd75@linux.intel.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The affected CPU table (cpu_vuln_blacklist) marks Alderlake and Raptorlake P-only parts affected by RFDS. This is not true because only E-cores are affected by RFDS. With the current family/model matching it is not possible to differentiate the unaffected parts, as the affected and unaffected hybrid variants have the same model number. Add a cpu-type match as well for such parts so as to exclude P-only parts being marked as affected. Note, family/model and cpu-type enumeration could be inaccurate in virtualized environments. In a guest affected status is decided by RFDS_NO and RFDS_CLEAR bits exposed by VMMs. Acked-by: Dave Hansen Signed-off-by: Pawan Gupta --- Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst | 8 -------- arch/x86/kernel/cpu/common.c | 9 +++++++-- 2 files changed, 7 insertions(+), 10 deletions(-) diff --git a/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst b= /Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst index 0585d02b9a6c..ad15417d39f9 100644 --- a/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst +++ b/Documentation/admin-guide/hw-vuln/reg-file-data-sampling.rst @@ -29,14 +29,6 @@ Below is the list of affected Intel processors [#f1]_: RAPTORLAKE_S 06_BFH =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D=3D =3D=3D=3D=3D= =3D=3D=3D=3D=3D=3D=3D=3D =20 -As an exception to this table, Intel Xeon E family parts ALDERLAKE(06_97H)= and -RAPTORLAKE(06_B7H) codenamed Catlow are not affected. They are reported as -vulnerable in Linux because they share the same family/model with an affec= ted -part. Unlike their affected counterparts, they do not enumerate RFDS_CLEAR= or -CPUID.HYBRID. This information could be used to distinguish between the -affected and unaffected parts, but it is deemed not worth adding complexit= y as -the reporting is fixed automatically when these parts enumerate RFDS_NO. - Mitigation =3D=3D=3D=3D=3D=3D=3D=3D=3D=3D Intel released a microcode update that enables software to clear sensitive diff --git a/arch/x86/kernel/cpu/common.c b/arch/x86/kernel/cpu/common.c index 9d41f8f7267a..fa9773207175 100644 --- a/arch/x86/kernel/cpu/common.c +++ b/arch/x86/kernel/cpu/common.c @@ -1206,6 +1206,11 @@ static const __initconst struct x86_cpu_id cpu_vuln_= whitelist[] =3D { #define VULNBL_INTEL_STEPS(vfm, max_stepping, issues) \ X86_MATCH_VFM_STEPS(INTEL_##vfm, X86_STEP_MIN, max_stepping, issues) =20 +#define VULNBL_INTEL_TYPE(vfm, cpu_type, issues) \ + X86_MATCH_VFM_CPU_TYPE(INTEL_##vfm, \ + INTEL_CPU_TYPE_##cpu_type, \ + issues) + #define VULNBL_AMD(family, blacklist) \ VULNBL(AMD, family, X86_MODEL_ANY, blacklist) =20 @@ -1254,9 +1259,9 @@ static const struct x86_cpu_id cpu_vuln_blacklist[] _= _initconst =3D { VULNBL_INTEL( TIGERLAKE, GDS), VULNBL_INTEL( LAKEFIELD, MMIO | MMIO_SBDS | RETBLEED), VULNBL_INTEL( ROCKETLAKE, MMIO | RETBLEED | GDS), - VULNBL_INTEL( ALDERLAKE, RFDS), + VULNBL_INTEL_TYPE( ALDERLAKE, ATOM, RFDS), VULNBL_INTEL( ALDERLAKE_L, RFDS), - VULNBL_INTEL( RAPTORLAKE, RFDS), + VULNBL_INTEL_TYPE( RAPTORLAKE, ATOM, RFDS), VULNBL_INTEL( RAPTORLAKE_P, RFDS), VULNBL_INTEL( RAPTORLAKE_S, RFDS), VULNBL_INTEL( ATOM_GRACEMONT, RFDS), --=20 2.34.1