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X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Mar 2025 23:21:13.7566 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9b80158c-01b2-4838-1556-08dd5b7341b2 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[SATLEXMB04.amd.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B070.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7702 Content-Type: text/plain; charset="utf-8" Add pinctrl driver support for AMD SoC with isp41 hw ip block. Signed-off-by: Pratap Nirujogi --- Changelog: - Updated copyright header - Removed noisy success prints - Dropped ifdefs - Cleanup header files drivers/pinctrl/Kconfig | 13 ++ drivers/pinctrl/Makefile | 1 + drivers/pinctrl/pinctrl-amdisp.c | 231 +++++++++++++++++++++++++++++++ drivers/pinctrl/pinctrl-amdisp.h | 95 +++++++++++++ 4 files changed, 340 insertions(+) create mode 100644 drivers/pinctrl/pinctrl-amdisp.c create mode 100644 drivers/pinctrl/pinctrl-amdisp.h diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index 95a8e2b9a614..5819f18b2ddc 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -49,6 +49,19 @@ config PINCTRL_AMD Requires ACPI/FDT device enumeration code to set up a platform device. =20 +config PINCTRL_AMDISP + tristate "AMDISP GPIO pin control" + depends on HAS_IOMEM + select GPIOLIB + select PINCONF + select GENERIC_PINCONF + help + The driver for memory mapped GPIO functionality on AMD platforms + with ISP support. All the pins are output controlled only + + Requires AMDGPU to MFD add device for enumeration to set up as + platform device. + config PINCTRL_APPLE_GPIO tristate "Apple SoC GPIO pin controller driver" depends on ARCH_APPLE diff --git a/drivers/pinctrl/Makefile b/drivers/pinctrl/Makefile index fba1c56624c0..ac27e88677d1 100644 --- a/drivers/pinctrl/Makefile +++ b/drivers/pinctrl/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_GENERIC_PINCONF) +=3D pinconf-generic.o obj-$(CONFIG_OF) +=3D devicetree.o =20 obj-$(CONFIG_PINCTRL_AMD) +=3D pinctrl-amd.o +obj-$(CONFIG_PINCTRL_AMDISP) +=3D pinctrl-amdisp.o obj-$(CONFIG_PINCTRL_APPLE_GPIO) +=3D pinctrl-apple-gpio.o obj-$(CONFIG_PINCTRL_ARTPEC6) +=3D pinctrl-artpec6.o obj-$(CONFIG_PINCTRL_AS3722) +=3D pinctrl-as3722.o diff --git a/drivers/pinctrl/pinctrl-amdisp.c b/drivers/pinctrl/pinctrl-amd= isp.c new file mode 100644 index 000000000000..ce21ed84b929 --- /dev/null +++ b/drivers/pinctrl/pinctrl-amdisp.c @@ -0,0 +1,231 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ISP Pinctrl Driver + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + */ + +#include +#include +#include + +#include "pinctrl-amdisp.h" + +#define DRV_NAME "amdisp-pinctrl" +#define GPIO_CONTROL_PIN 4 +#define GPIO_OFFSET_0 0x0 +#define GPIO_OFFSET_1 0x4 +#define GPIO_OFFSET_2 0x50 + +static const u32 gpio_offset[] =3D { + GPIO_OFFSET_0, + GPIO_OFFSET_1, + GPIO_OFFSET_2 +}; + +struct amdisp_pinctrl_data { + const struct pinctrl_pin_desc *pins; + unsigned int npins; + const struct amdisp_function *functions; + unsigned int nfunctions; + const struct amdisp_pingroup *groups; + unsigned int ngroups; +}; + +static const struct amdisp_pinctrl_data amdisp_pinctrl_data =3D { + .pins =3D amdisp_pins, + .npins =3D ARRAY_SIZE(amdisp_pins), + .functions =3D amdisp_functions, + .nfunctions =3D ARRAY_SIZE(amdisp_functions), + .groups =3D amdisp_groups, + .ngroups =3D ARRAY_SIZE(amdisp_groups), +}; + +struct amdisp_pinctrl { + struct device *dev; + struct pinctrl_dev *pctrl; + struct pinctrl_desc desc; + struct pinctrl_gpio_range gpio_range; + struct gpio_chip gc; + const struct amdisp_pinctrl_data *data; + void __iomem *gpiobase; + raw_spinlock_t lock; +}; + +static int amdisp_get_groups_count(struct pinctrl_dev *pctldev) +{ + struct amdisp_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->ngroups; +} + +static const char *amdisp_get_group_name(struct pinctrl_dev *pctldev, + unsigned int group) +{ + struct amdisp_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + + return pctrl->data->groups[group].name; +} + +static int amdisp_get_group_pins(struct pinctrl_dev *pctldev, + unsigned int group, + const unsigned int **pins, + unsigned int *num_pins) +{ + struct amdisp_pinctrl *pctrl =3D pinctrl_dev_get_drvdata(pctldev); + + *pins =3D pctrl->data->groups[group].pins; + *num_pins =3D pctrl->data->groups[group].npins; + return 0; +} + +const struct pinctrl_ops amdisp_pinctrl_ops =3D { + .get_groups_count =3D amdisp_get_groups_count, + .get_group_name =3D amdisp_get_group_name, + .get_group_pins =3D amdisp_get_group_pins, +}; + +static int amdisp_gpio_get_direction(struct gpio_chip *gc, unsigned int gp= io) +{ + /* amdisp gpio only has output mode */ + return GPIO_LINE_DIRECTION_OUT; +} + +static int amdisp_gpio_direction_input(struct gpio_chip *gc, unsigned int = gpio) +{ + return -EOPNOTSUPP; +} + +static int amdisp_gpio_direction_output(struct gpio_chip *gc, unsigned int= gpio, + int value) +{ + /* Nothing to do, amdisp gpio only has output mode */ + return 0; +} + +static int amdisp_gpio_get(struct gpio_chip *gc, unsigned int gpio) +{ + unsigned long flags; + u32 pin_reg; + struct amdisp_pinctrl *pctrl =3D gpiochip_get_data(gc); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + pin_reg =3D readl(pctrl->gpiobase + gpio_offset[gpio]); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); + + return !!(pin_reg & BIT(GPIO_CONTROL_PIN)); +} + +static void amdisp_gpio_set(struct gpio_chip *gc, unsigned int gpio, int v= alue) +{ + unsigned long flags; + u32 pin_reg; + struct amdisp_pinctrl *pctrl =3D gpiochip_get_data(gc); + + raw_spin_lock_irqsave(&pctrl->lock, flags); + pin_reg =3D readl(pctrl->gpiobase + gpio_offset[gpio]); + if (value) + pin_reg |=3D BIT(GPIO_CONTROL_PIN); + else + pin_reg &=3D ~BIT(GPIO_CONTROL_PIN); + writel(pin_reg, pctrl->gpiobase + gpio_offset[gpio]); + raw_spin_unlock_irqrestore(&pctrl->lock, flags); +} + +static int amdisp_gpiochip_add(struct platform_device *pdev, + struct amdisp_pinctrl *pctrl) +{ + struct gpio_chip *gc =3D &pctrl->gc; + struct pinctrl_gpio_range *grange =3D &pctrl->gpio_range; + int ret; + + gc->label =3D dev_name(pctrl->dev); + gc->parent =3D &pdev->dev; + gc->names =3D amdisp_range_pins_name; + gc->request =3D gpiochip_generic_request; + gc->free =3D gpiochip_generic_free; + gc->get_direction =3D amdisp_gpio_get_direction; + gc->direction_input =3D amdisp_gpio_direction_input; + gc->direction_output =3D amdisp_gpio_direction_output; + gc->get =3D amdisp_gpio_get; + gc->set =3D amdisp_gpio_set; + gc->base =3D -1; + gc->ngpio =3D ARRAY_SIZE(amdisp_range_pins); + + grange->id =3D 0; + grange->pin_base =3D 0; + grange->base =3D 0; + grange->pins =3D amdisp_range_pins; + grange->npins =3D ARRAY_SIZE(amdisp_range_pins); + grange->name =3D gc->label; + grange->gc =3D gc; + + ret =3D devm_gpiochip_add_data(&pdev->dev, gc, pctrl); + if (ret) + return ret; + + pinctrl_add_gpio_range(pctrl->pctrl, grange); + + return 0; +} + +static int amdisp_pinctrl_probe(struct platform_device *pdev) +{ + struct amdisp_pinctrl *pctrl; + struct resource *res; + int ret; + + pctrl =3D devm_kzalloc(&pdev->dev, sizeof(*pctrl), GFP_KERNEL); + if (!pctrl) + return -ENOMEM; + + pdev->dev.init_name =3D DRV_NAME; + + res =3D platform_get_resource(pdev, IORESOURCE_MEM, 0); + if (IS_ERR(res)) + return PTR_ERR(res); + + pctrl->gpiobase =3D devm_ioremap_resource(&pdev->dev, res); + if (IS_ERR(pctrl->gpiobase)) + return PTR_ERR(pctrl->gpiobase); + + platform_set_drvdata(pdev, pctrl); + + pctrl->dev =3D &pdev->dev; + pctrl->data =3D &amdisp_pinctrl_data; + pctrl->desc.owner =3D THIS_MODULE; + pctrl->desc.pctlops =3D &amdisp_pinctrl_ops; + pctrl->desc.pmxops =3D NULL; + pctrl->desc.name =3D dev_name(&pdev->dev); + pctrl->desc.pins =3D pctrl->data->pins; + pctrl->desc.npins =3D pctrl->data->npins; + ret =3D devm_pinctrl_register_and_init(&pdev->dev, &pctrl->desc, + pctrl, &pctrl->pctrl); + if (ret) + return ret; + + ret =3D pinctrl_enable(pctrl->pctrl); + if (ret) + return ret; + + ret =3D amdisp_gpiochip_add(pdev, pctrl); + if (ret) + return ret; + + return 0; +} + +static struct platform_driver amdisp_pinctrl_driver =3D { + .driver =3D { + .name =3D DRV_NAME, + }, + .probe =3D amdisp_pinctrl_probe, +}; +module_platform_driver(amdisp_pinctrl_driver); + +MODULE_AUTHOR("Benjamin Chan "); +MODULE_AUTHOR("Pratap Nirujogi "); +MODULE_DESCRIPTION("AMDISP pinctrl driver"); +MODULE_LICENSE("GPL v2"); +MODULE_ALIAS("platform:" DRV_NAME); diff --git a/drivers/pinctrl/pinctrl-amdisp.h b/drivers/pinctrl/pinctrl-amd= isp.h new file mode 100644 index 000000000000..9e3597a03227 --- /dev/null +++ b/drivers/pinctrl/pinctrl-amdisp.h @@ -0,0 +1,95 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * AMD ISP Pinctrl Driver + * + * Copyright (C) 2025 Advanced Micro Devices, Inc. All rights reserved. + * + */ + +static const struct pinctrl_pin_desc amdisp_pins[] =3D { + PINCTRL_PIN(0, "GPIO_0"), /* sensor0 control */ + PINCTRL_PIN(1, "GPIO_1"), /* sensor1 control */ + PINCTRL_PIN(2, "GPIO_2"), /* sensor2 control */ +}; + +#define AMDISP_GPIO_PINS(pin) \ +static const unsigned int gpio##pin##_pins[] =3D { pin } +AMDISP_GPIO_PINS(0); +AMDISP_GPIO_PINS(1); +AMDISP_GPIO_PINS(2); + +static const unsigned int amdisp_range_pins[] =3D { + 0, 1, 2 +}; + +static const char * const amdisp_range_pins_name[] =3D { + "gpio0", "gpio1", "gpio2" +}; + +enum amdisp_functions { + mux_gpio, + mux_NA +}; + +static const char * const gpio_groups[] =3D { + "gpio0", "gpio1", "gpio2" +}; + +/** + * struct amdisp_function - a pinmux function + * @name: Name of the pinmux function. + * @groups: List of pingroups for this function. + * @ngroups: Number of entries in @groups. + */ +struct amdisp_function { + const char *name; + const char * const *groups; + unsigned int ngroups; +}; + +#define FUNCTION(fname) \ + [mux_##fname] =3D { \ + .name =3D #fname, \ + .groups =3D fname##_groups, \ + .ngroups =3D ARRAY_SIZE(fname##_groups), \ + } + +static const struct amdisp_function amdisp_functions[] =3D { + FUNCTION(gpio), +}; + +/** + * struct amdisp_pingroup - a pinmux group + * @name: Name of the pinmux group. + * @pins: List of pins for this group. + * @npins: Number of entries in @pins. + * @funcs: List of functions belongs to this group. + * @nfuncs: Number of entries in @funcs. + * @offset: Group offset in amdisp pinmux groups. + */ +struct amdisp_pingroup { + const char *name; + const unsigned int *pins; + unsigned int npins; + unsigned int *funcs; + unsigned int nfuncs; + unsigned int offset; +}; + +#define PINGROUP(id, f0) \ + { \ + .name =3D "gpio" #id, \ + .pins =3D gpio##id##_pins, \ + .npins =3D ARRAY_SIZE(gpio##id##_pins), \ + .funcs =3D (int[]){ \ + mux_##f0, \ + }, \ + .nfuncs =3D 1, \ + .offset =3D id, \ + } + +static const struct amdisp_pingroup amdisp_groups[] =3D { + PINGROUP(0, gpio), + PINGROUP(1, gpio), + PINGROUP(2, gpio), +}; --=20 2.43.0