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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7349fe6cfd9sm11492793b3a.76.2025.03.04.15.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 15:05:08 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: [PATCH v3 4/5] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Date: Tue, 4 Mar 2025 15:05:01 -0800 Message-Id: <20250304230502.1470523-5-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> References: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=I/ufRMgg c=1 sm=1 tr=0 ts=67c78728 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=4OMqYXV_ruVW7JoEK48A:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: Oy6pGPpJmKXAVRHcGmE9Sze2VSnajGGI X-Proofpoint-ORIG-GUID: Oy6pGPpJmKXAVRHcGmE9Sze2VSnajGGI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-04_09,2025-03-04_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503040183 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM GEN2 PMIC peripherals with digital major revision 2. This revision utilizes individual temp DAC registers to set the threshold temperature for over-temperature stages 1, 2, and 3 instead of a single register to specify a set of thresholds. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 136 ++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 514772e94a28..efd2b6534127 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -26,6 +26,11 @@ #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 +/* TEMP_DAC_STGx registers are only present for TEMP_GEN2 v2.0 */ +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 + #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 @@ -65,6 +70,25 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { =20 #define TEMP_STAGE_HYSTERESIS 2000 =20 +/* + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the thr= eshold + * for each stage independently. + * TEMP_DAC_STG* =3D 0 --> 80 C + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC= ). + */ +#define TEMP_DAC_MIN 80000 +#define TEMP_DAC_SCALE_NUM 8 +#define TEMP_DAC_SCALE_DEN 5000 + +#define TEMP_DAC_TEMP_TO_REG(temp) \ + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) +#define TEMP_DAC_REG_TO_TEMP(reg) \ + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) + +static const long temp_dac_max[STAGE_COUNT] =3D { + 119375, 159375, 159375 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -73,6 +97,7 @@ struct qpnp_tm_chip; struct spmi_temp_alarm_data { const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*setup)(struct qpnp_tm_chip *chip); int (*get_temp_stage)(struct qpnp_tm_chip *chip); int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; @@ -88,6 +113,7 @@ struct qpnp_tm_chip { unsigned int thresh; unsigned int stage; unsigned int base; + unsigned int ntrips; /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; @@ -305,6 +331,52 @@ static const struct thermal_zone_device_ops qpnp_tm_se= nsor_ops =3D { .set_trip_temp =3D qpnp_tm_set_trip_temp, }; =20 +static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, in= t trip, int temp) +{ + int ret, temp_cfg; + u8 reg; + + if (trip < 0 || trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_DAC trip =3D %d\n", trip); + return -EINVAL; + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { + dev_err(chip->dev, "invalid TEMP_DAC temp =3D %d\n", temp); + return -EINVAL; + } + + reg =3D TEMP_DAC_TEMP_TO_REG(temp); + temp_cfg =3D TEMP_DAC_REG_TO_TEMP(reg); + + ret =3D qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); + if (ret < 0) { + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -329,6 +401,58 @@ static int qpnp_tm_configure_trip_temp(struct qpnp_tm_= chip *chip) return qpnp_tm_update_critical_trip_temp(chip, crit_temp); } =20 +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ +static int qpnp_tm_gen2_rev2_configure_trip_temps_cb(struct thermal_trip *= trip, void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, chip->ntrips, trip->tempe= rature); + chip->ntrips++; + + return ret; +} + +static int qpnp_tm_gen2_rev2_configure_trip_temps(struct qpnp_tm_chip *chi= p) +{ + int ret, i; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, + qpnp_tm_gen2_rev2_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + for (i =3D 1; i < STAGE_COUNT; i++) { + if (chip->temp_thresh_map[i] <=3D chip->temp_thresh_map[i - 1]) { + dev_err(chip->dev, "Threshold %d=3D%ld <=3D threshold %d=3D%ld\n", + i, chip->temp_thresh_map[i], i - 1, + chip->temp_thresh_map[i - 1]); + return -EINVAL; + } + } + + return 0; +} + +/* Read the hardware default TEMP_DAC stage threshold temperatures */ +static int qpnp_tm_gen2_rev2_setup(struct qpnp_tm_chip *chip) +{ + int ret, i; + u8 reg =3D 0; + + for (i =3D 0; i < STAGE_COUNT; i++) { + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); + if (ret < 0) + return ret; + + chip->temp_thresh_map[i] =3D TEMP_DAC_REG_TO_TEMP(reg); + } + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -350,6 +474,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev1_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = =3D { + .ops =3D &qpnp_tm_gen2_rev2_sensor_ops, + .setup =3D qpnp_tm_gen2_rev2_setup, + .configure_trip_temps =3D qpnp_tm_gen2_rev2_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -484,6 +615,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) =20 if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) chip->data =3D &spmi_temp_alarm_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 2) + chip->data =3D &spmi_temp_alarm_gen2_rev2_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 1) chip->data =3D &spmi_temp_alarm_gen2_rev1_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) @@ -491,6 +624,9 @@ static int qpnp_tm_probe(struct platform_device *pdev) else return -ENODEV; =20 + if (chip->data->setup) + chip->data->setup(chip); + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature --=20 2.34.1