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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7349fe6cfd9sm11492793b3a.76.2025.03.04.15.05.03 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 15:05:04 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: [PATCH v3 1/5] thermal: qcom-spmi-temp-alarm: enable stage 2 shutdown when required Date: Tue, 4 Mar 2025 15:04:58 -0800 Message-Id: <20250304230502.1470523-2-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> References: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=HZbuTjE8 c=1 sm=1 tr=0 ts=67c78723 cx=c_pps a=cmESyDAEBpBGqyK7t0alAg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=q_MlTjK-hrb8HEj9cREA:9 a=RVmHIydaz68A:10 a=1OuFwYUASf3TG4hYMiVC:22 X-Proofpoint-GUID: XYbixBUIBPbhxJ9R699RIgWyDiLgkuV6 X-Proofpoint-ORIG-GUID: XYbixBUIBPbhxJ9R699RIgWyDiLgkuV6 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-04_09,2025-03-04_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 adultscore=0 mlxscore=0 spamscore=0 clxscore=1015 phishscore=0 bulkscore=0 priorityscore=1501 impostorscore=0 suspectscore=0 malwarescore=0 mlxlogscore=999 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503040184 Content-Type: text/plain; charset="utf-8" From: David Collins Certain TEMP_ALARM GEN2 PMIC peripherals need over-temperature stage 2 automatic PMIC partial shutdown to be enabled in order to avoid repeated faults in the event of reaching over-temperature stage 3. Modify the stage 2 shutdown control logic to ensure that stage 2 shutdown is enabled on all affected PMICs. Read the digital major and minor revision registers to identify these PMICs. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 32 +++++++++++++++++++-- 1 file changed, 30 insertions(+), 2 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index c2d59cbfaea9..b2077ff9fe73 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,6 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights r= eserved. + * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 #include @@ -16,6 +17,7 @@ =20 #include "../thermal_hwmon.h" =20 +#define QPNP_TM_REG_DIG_MINOR 0x00 #define QPNP_TM_REG_DIG_MAJOR 0x01 #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 @@ -71,6 +73,7 @@ struct qpnp_tm_chip { struct device *dev; struct thermal_zone_device *tz_dev; unsigned int subtype; + unsigned int dig_revision; long temp; unsigned int thresh; unsigned int stage; @@ -78,6 +81,7 @@ struct qpnp_tm_chip { /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; + bool require_s2_shutdown; =20 struct iio_channel *adc; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; @@ -255,7 +259,7 @@ static int qpnp_tm_update_critical_trip_temp(struct qpn= p_tm_chip *chip, =20 skip: reg |=3D chip->thresh; - if (disable_s2_shutdown) + if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |=3D SHUTDOWN_CTRL1_OVERRIDE_S2; =20 return qpnp_tm_write(chip, QPNP_TM_REG_SHUTDOWN_CTRL1, reg); @@ -350,7 +354,7 @@ static int qpnp_tm_probe(struct platform_device *pdev) { struct qpnp_tm_chip *chip; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7349fe6cfd9sm11492793b3a.76.2025.03.04.15.05.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 15:05:06 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: [PATCH v3 2/5] thermal: qcom-spmi-temp-alarm: Add temp alarm data struct based on HW subtype Date: Tue, 4 Mar 2025 15:04:59 -0800 Message-Id: <20250304230502.1470523-3-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> References: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: tWPaqp6CC19lcN2PqOSO4cv6aidY0jVv X-Proofpoint-ORIG-GUID: tWPaqp6CC19lcN2PqOSO4cv6aidY0jVv X-Authority-Analysis: v=2.4 cv=fatXy1QF c=1 sm=1 tr=0 ts=67c78725 cx=c_pps a=JL+w9abYAAE89/QcEU+0QA==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=KKAkSRfTAAAA:8 a=KV_uBXLwT3x28NnhTW4A:9 a=RVmHIydaz68A:10 a=324X-CrmTo6CU4MGRt3R:22 a=cvBusfyB2V15izCimMoJ:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-04_09,2025-03-04_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 clxscore=1015 bulkscore=0 spamscore=0 priorityscore=1501 malwarescore=0 impostorscore=0 lowpriorityscore=0 mlxlogscore=999 mlxscore=0 adultscore=0 suspectscore=0 phishscore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503040184 Content-Type: text/plain; charset="utf-8" Currently multiple if/else statements are used in functions to decipher between SPMI temp alarm Gen 1, Gen 2 and Gen 2 Rev 1 functionality. Instead refactor the driver so that SPMI temp alarm chips will have reference to a spmi_temp_alarm_data struct which defines data and function callbacks based on the HW subtype. Signed-off-by: Anjelique Melendez Reviewed-by: Dmitry Baryshkov --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 107 +++++++++++++------- 1 file changed, 70 insertions(+), 37 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index b2077ff9fe73..1cc9369ca9e1 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -4,6 +4,7 @@ * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. */ =20 +#include #include #include #include @@ -31,7 +32,6 @@ =20 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) -#define STATUS_GEN2_STATE_SHIFT 4 =20 #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) @@ -68,10 +68,18 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_= COUNT] =3D { /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 +struct qpnp_tm_chip; + +struct spmi_temp_alarm_data { + const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*get_temp_stage)(struct qpnp_tm_chip *chip); +}; + struct qpnp_tm_chip { struct regmap *map; struct device *dev; struct thermal_zone_device *tz_dev; + const struct spmi_temp_alarm_data *data; unsigned int subtype; unsigned int dig_revision; long temp; @@ -82,9 +90,9 @@ struct qpnp_tm_chip { struct mutex lock; bool initialized; bool require_s2_shutdown; + long temp_thresh_map[STAGE_COUNT]; =20 struct iio_channel *adc; - const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; }; =20 /* This array maps from GEN2 alarm state to GEN1 alarm stage */ @@ -118,20 +126,19 @@ static int qpnp_tm_write(struct qpnp_tm_chip *chip, u= 16 addr, u8 data) */ static long qpnp_tm_decode_temp(struct qpnp_tm_chip *chip, unsigned int st= age) { - if (!chip->temp_map || chip->thresh >=3D THRESH_COUNT || stage =3D=3D 0 || - stage > STAGE_COUNT) + if (stage =3D=3D 0 || stage > STAGE_COUNT) return 0; =20 - return (*chip->temp_map)[chip->thresh][stage - 1]; + return chip->temp_thresh_map[stage - 1]; } =20 /** - * qpnp_tm_get_temp_stage() - return over-temperature stage + * qpnp_tm_gen1_get_temp_stage() - return over-temperature stage * @chip: Pointer to the qpnp_tm chip * - * Return: stage (GEN1) or state (GEN2) on success, or errno on failure. + * Return: stage on success, or errno on failure. */ -static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip *chip) +static int qpnp_tm_gen1_get_temp_stage(struct qpnp_tm_chip *chip) { int ret; u8 reg =3D 0; @@ -140,12 +147,27 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip= *chip) if (ret < 0) return ret; =20 - if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) - ret =3D reg & STATUS_GEN1_STAGE_MASK; - else - ret =3D (reg & STATUS_GEN2_STATE_MASK) >> STATUS_GEN2_STATE_SHIFT; + return FIELD_GET(STATUS_GEN1_STAGE_MASK, reg); +} =20 - return ret; +/** + * qpnp_tm_gen2_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: stage on success, or errno on failure. + */ +static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg =3D 0; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_STATUS, ®); + if (ret < 0) + return ret; + + ret =3D FIELD_GET(STATUS_GEN2_STATE_MASK, reg); + + return alarm_state_map[ret]; } =20 /* @@ -154,23 +176,16 @@ static int qpnp_tm_get_temp_stage(struct qpnp_tm_chip= *chip) */ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_chip *chip) { - unsigned int stage, stage_new, stage_old; + unsigned int stage_new, stage_old; int ret; =20 WARN_ON(!mutex_is_locked(&chip->lock)); =20 - ret =3D qpnp_tm_get_temp_stage(chip); + ret =3D chip->data->get_temp_stage(chip); if (ret < 0) return ret; - stage =3D ret; - - if (chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) { - stage_new =3D stage; - stage_old =3D chip->stage; - } else { - stage_new =3D alarm_state_map[stage]; - stage_old =3D alarm_state_map[chip->stage]; - } + stage_new =3D ret; + stage_old =3D chip->stage; =20 if (stage_new > stage_old) { /* increasing stage, use lower bound */ @@ -182,7 +197,7 @@ static int qpnp_tm_update_temp_no_adc(struct qpnp_tm_ch= ip *chip) - TEMP_STAGE_HYSTERESIS; } =20 - chip->stage =3D stage; + chip->stage =3D stage_new; =20 return 0; } @@ -222,8 +237,8 @@ static int qpnp_tm_get_temp(struct thermal_zone_device = *tz, int *temp) static int qpnp_tm_update_critical_trip_temp(struct qpnp_tm_chip *chip, int temp) { - long stage2_threshold_min =3D (*chip->temp_map)[THRESH_MIN][1]; - long stage2_threshold_max =3D (*chip->temp_map)[THRESH_MAX][1]; + long stage2_threshold_min =3D (*chip->data->temp_map)[THRESH_MIN][1]; + long stage2_threshold_max =3D (*chip->data->temp_map)[THRESH_MAX][1]; bool disable_s2_shutdown =3D false; u8 reg; =20 @@ -258,6 +273,8 @@ static int qpnp_tm_update_critical_trip_temp(struct qpn= p_tm_chip *chip, } =20 skip: + memcpy(chip->temp_thresh_map, chip->data->temp_map[chip->thresh], + sizeof(chip->temp_thresh_map)); reg |=3D chip->thresh; if (disable_s2_shutdown && !chip->require_s2_shutdown) reg |=3D SHUTDOWN_CTRL1_OVERRIDE_S2; @@ -295,6 +312,21 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .temp_map =3D &temp_map_gen1, + .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .temp_map =3D &temp_map_gen1, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .temp_map =3D &temp_map_gen2_v1, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -302,7 +334,6 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) */ static int qpnp_tm_init(struct qpnp_tm_chip *chip) { - unsigned int stage; int ret; u8 reg =3D 0; int crit_temp; @@ -316,16 +347,13 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) chip->thresh =3D reg & SHUTDOWN_CTRL1_THRESHOLD_MASK; chip->temp =3D DEFAULT_TEMP; =20 - ret =3D qpnp_tm_get_temp_stage(chip); + ret =3D chip->data->get_temp_stage(chip); if (ret < 0) goto out; chip->stage =3D ret; =20 - stage =3D chip->subtype =3D=3D QPNP_TM_SUBTYPE_GEN1 - ? chip->stage : alarm_state_map[chip->stage]; - - if (stage) - chip->temp =3D qpnp_tm_decode_temp(chip, stage); + if (chip->stage) + chip->temp =3D qpnp_tm_decode_temp(chip, chip->stage); =20 mutex_unlock(&chip->lock); =20 @@ -439,10 +467,15 @@ static int qpnp_tm_probe(struct platform_device *pdev) } =20 chip->subtype =3D subtype; - if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 1) - chip->temp_map =3D &temp_map_gen2_v1; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7349fe6cfd9sm11492793b3a.76.2025.03.04.15.05.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 15:05:07 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: [PATCH v3 3/5] thermal: qcom-spmi-temp-alarm: Prepare to support additional Temp Alarm subtypes Date: Tue, 4 Mar 2025 15:05:00 -0800 Message-Id: <20250304230502.1470523-4-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> References: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=EZcyQOmC c=1 sm=1 tr=0 ts=67c78726 cx=c_pps a=IZJwPbhc+fLeJZngyXXI0A==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=7un5503AD7E7R8fKnWkA:9 a=RVmHIydaz68A:10 a=2kiUGkeb1pZ_ou3T1mbW:22 a=uG9DUKGECoFWVXl0Dc02:22 X-Proofpoint-GUID: PQcQpBJIRHcGbP9Pt0RGgcek5lvSIrLQ X-Proofpoint-ORIG-GUID: PQcQpBJIRHcGbP9Pt0RGgcek5lvSIrLQ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-04_09,2025-03-04_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503040184 Content-Type: text/plain; charset="utf-8" In preparation to support newer temp alarm subtypes, add the "ops" and "configure_trip_temps" references to spmi_temp_alarm_data. This will allow for each Temp Alarm subtype to define its own thermal_zone_device_ops and properly configure thermal trip temperature. Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 38 ++++++++++++++------- 1 file changed, 26 insertions(+), 12 deletions(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 1cc9369ca9e1..514772e94a28 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -1,7 +1,7 @@ // SPDX-License-Identifier: GPL-2.0-only /* * Copyright (c) 2011-2015, 2017, 2020, The Linux Foundation. All rights r= eserved. - * Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserve= d. + * Copyright (c) 2024-2025, Qualcomm Innovation Center, Inc. All rights re= served. */ =20 #include @@ -71,8 +71,10 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { struct qpnp_tm_chip; =20 struct spmi_temp_alarm_data { + const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; int (*get_temp_stage)(struct qpnp_tm_chip *chip); + int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; =20 struct qpnp_tm_chip { @@ -312,18 +314,39 @@ static irqreturn_t qpnp_tm_isr(int irq, void *data) return IRQ_HANDLED; } =20 +static int qpnp_tm_configure_trip_temp(struct qpnp_tm_chip *chip) +{ + int crit_temp, ret; + + mutex_unlock(&chip->lock); + + ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); + if (ret) + crit_temp =3D THERMAL_TEMP_INVALID; + + mutex_lock(&chip->lock); + + return qpnp_tm_update_critical_trip_temp(chip, crit_temp); +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen1_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_data =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev1_data = =3D { + .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen2_v1, + .configure_trip_temps =3D qpnp_tm_configure_trip_temp, .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 @@ -336,7 +359,6 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) { int ret; u8 reg =3D 0; - int crit_temp; =20 mutex_lock(&chip->lock); =20 @@ -355,15 +377,7 @@ static int qpnp_tm_init(struct qpnp_tm_chip *chip) if (chip->stage) chip->temp =3D qpnp_tm_decode_temp(chip, chip->stage); =20 - mutex_unlock(&chip->lock); - - ret =3D thermal_zone_get_crit_temp(chip->tz_dev, &crit_temp); - if (ret) - crit_temp =3D THERMAL_TEMP_INVALID; - - mutex_lock(&chip->lock); - - ret =3D qpnp_tm_update_critical_trip_temp(chip, crit_temp); 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7349fe6cfd9sm11492793b3a.76.2025.03.04.15.05.08 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 15:05:08 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: [PATCH v3 4/5] thermal: qcom-spmi-temp-alarm: add support for GEN2 rev 2 PMIC peripherals Date: Tue, 4 Mar 2025 15:05:01 -0800 Message-Id: <20250304230502.1470523-5-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> References: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=I/ufRMgg c=1 sm=1 tr=0 ts=67c78728 cx=c_pps a=MTSHoo12Qbhz2p7MsH1ifg==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=4OMqYXV_ruVW7JoEK48A:9 a=GvdueXVYPmCkWapjIL-Q:22 X-Proofpoint-GUID: Oy6pGPpJmKXAVRHcGmE9Sze2VSnajGGI X-Proofpoint-ORIG-GUID: Oy6pGPpJmKXAVRHcGmE9Sze2VSnajGGI X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-04_09,2025-03-04_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 adultscore=0 mlxscore=0 spamscore=0 bulkscore=0 priorityscore=1501 lowpriorityscore=0 suspectscore=0 phishscore=0 malwarescore=0 mlxlogscore=999 impostorscore=0 clxscore=1015 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503040183 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM GEN2 PMIC peripherals with digital major revision 2. This revision utilizes individual temp DAC registers to set the threshold temperature for over-temperature stages 1, 2, and 3 instead of a single register to specify a set of thresholds. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 136 ++++++++++++++++++++ 1 file changed, 136 insertions(+) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index 514772e94a28..efd2b6534127 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -26,6 +26,11 @@ #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 +/* TEMP_DAC_STGx registers are only present for TEMP_GEN2 v2.0 */ +#define QPNP_TM_REG_TEMP_DAC_STG1 0x47 +#define QPNP_TM_REG_TEMP_DAC_STG2 0x48 +#define QPNP_TM_REG_TEMP_DAC_STG3 0x49 + #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 @@ -65,6 +70,25 @@ static const long temp_map_gen2_v1[THRESH_COUNT][STAGE_C= OUNT] =3D { =20 #define TEMP_STAGE_HYSTERESIS 2000 =20 +/* + * For TEMP_GEN2 v2.0, TEMP_DAC_STG1/2/3 registers are used to set the thr= eshold + * for each stage independently. + * TEMP_DAC_STG* =3D 0 --> 80 C + * Each 8 step increase in TEMP_DAC_STG* value corresponds to 5 C (5000 mC= ). + */ +#define TEMP_DAC_MIN 80000 +#define TEMP_DAC_SCALE_NUM 8 +#define TEMP_DAC_SCALE_DEN 5000 + +#define TEMP_DAC_TEMP_TO_REG(temp) \ + (((temp) - TEMP_DAC_MIN) * TEMP_DAC_SCALE_NUM / TEMP_DAC_SCALE_DEN) +#define TEMP_DAC_REG_TO_TEMP(reg) \ + (TEMP_DAC_MIN + (reg) * TEMP_DAC_SCALE_DEN / TEMP_DAC_SCALE_NUM) + +static const long temp_dac_max[STAGE_COUNT] =3D { + 119375, 159375, 159375 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -73,6 +97,7 @@ struct qpnp_tm_chip; struct spmi_temp_alarm_data { const struct thermal_zone_device_ops *ops; const long (*temp_map)[THRESH_COUNT][STAGE_COUNT]; + int (*setup)(struct qpnp_tm_chip *chip); int (*get_temp_stage)(struct qpnp_tm_chip *chip); int (*configure_trip_temps)(struct qpnp_tm_chip *chip); }; @@ -88,6 +113,7 @@ struct qpnp_tm_chip { unsigned int thresh; unsigned int stage; unsigned int base; + unsigned int ntrips; /* protects .thresh, .stage and chip registers */ struct mutex lock; bool initialized; @@ -305,6 +331,52 @@ static const struct thermal_zone_device_ops qpnp_tm_se= nsor_ops =3D { .set_trip_temp =3D qpnp_tm_set_trip_temp, }; =20 +static int qpnp_tm_gen2_rev2_set_temp_thresh(struct qpnp_tm_chip *chip, in= t trip, int temp) +{ + int ret, temp_cfg; + u8 reg; + + if (trip < 0 || trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_DAC trip =3D %d\n", trip); + return -EINVAL; + } else if (temp < TEMP_DAC_MIN || temp > temp_dac_max[trip]) { + dev_err(chip->dev, "invalid TEMP_DAC temp =3D %d\n", temp); + return -EINVAL; + } + + reg =3D TEMP_DAC_TEMP_TO_REG(temp); + temp_cfg =3D TEMP_DAC_REG_TO_TEMP(reg); + + ret =3D qpnp_tm_write(chip, QPNP_TM_REG_TEMP_DAC_STG1 + trip, reg); + if (ret < 0) { + dev_err(chip->dev, "TEMP_DAC_STG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_gen2_rev2_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_gen2_rev2_sensor_ops = =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -329,6 +401,58 @@ static int qpnp_tm_configure_trip_temp(struct qpnp_tm_= chip *chip) return qpnp_tm_update_critical_trip_temp(chip, crit_temp); } =20 +/* Configure TEMP_DAC registers based on DT thermal_zone trips */ +static int qpnp_tm_gen2_rev2_configure_trip_temps_cb(struct thermal_trip *= trip, void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_gen2_rev2_set_temp_thresh(chip, chip->ntrips, trip->tempe= rature); + chip->ntrips++; + + return ret; +} + +static int qpnp_tm_gen2_rev2_configure_trip_temps(struct qpnp_tm_chip *chi= p) +{ + int ret, i; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, + qpnp_tm_gen2_rev2_configure_trip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + for (i =3D 1; i < STAGE_COUNT; i++) { + if (chip->temp_thresh_map[i] <=3D chip->temp_thresh_map[i - 1]) { + dev_err(chip->dev, "Threshold %d=3D%ld <=3D threshold %d=3D%ld\n", + i, chip->temp_thresh_map[i], i - 1, + chip->temp_thresh_map[i - 1]); + return -EINVAL; + } + } + + return 0; +} + +/* Read the hardware default TEMP_DAC stage threshold temperatures */ +static int qpnp_tm_gen2_rev2_setup(struct qpnp_tm_chip *chip) +{ + int ret, i; + u8 reg =3D 0; + + for (i =3D 0; i < STAGE_COUNT; i++) { + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_TEMP_DAC_STG1 + i, ®); + if (ret < 0) + return ret; + + chip->temp_thresh_map[i] =3D TEMP_DAC_REG_TO_TEMP(reg); + } + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -350,6 +474,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev1_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_gen2_rev2_data = =3D { + .ops =3D &qpnp_tm_gen2_rev2_sensor_ops, + .setup =3D qpnp_tm_gen2_rev2_setup, + .configure_trip_temps =3D qpnp_tm_gen2_rev2_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -484,6 +615,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) =20 if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN1) chip->data =3D &spmi_temp_alarm_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 2) + chip->data =3D &spmi_temp_alarm_gen2_rev2_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2 && dig_major >=3D 1) chip->data =3D &spmi_temp_alarm_gen2_rev1_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) @@ -491,6 +624,9 @@ static int qpnp_tm_probe(struct platform_device *pdev) else return -ENODEV; =20 + if (chip->data->setup) + chip->data->setup(chip); + /* * Register the sensor before initializing the hardware to be able to * read the trip points. get_temp() returns the default temperature --=20 2.34.1 From nobody Mon Feb 9 12:45:54 2026 Received: from mx0b-0031df01.pphosted.com (mx0b-0031df01.pphosted.com [205.220.180.131]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DD5E427C15A for ; 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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7349fe6cfd9sm11492793b3a.76.2025.03.04.15.05.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 04 Mar 2025 15:05:10 -0800 (PST) From: Anjelique Melendez To: amitk@kernel.org, thara.gopinath@gmail.com, rafael@kernel.org, daniel.lezcano@linaro.org Cc: rui.zhang@intel.com, lukasz.luba@arm.com, david.collins@oss.qualcomm.com, linux-arm-msm@vger.kernel.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, dmitry.baryshkov@linaro.org Subject: [PATCH v3 5/5] thermal: qcom-spmi-temp-alarm: add support for LITE PMIC peripherals Date: Tue, 4 Mar 2025 15:05:02 -0800 Message-Id: <20250304230502.1470523-6-anjelique.melendez@oss.qualcomm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> References: <20250304230502.1470523-1-anjelique.melendez@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Authority-Analysis: v=2.4 cv=EZcyQOmC c=1 sm=1 tr=0 ts=67c78729 cx=c_pps a=UNFcQwm+pnOIJct1K4W+Mw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=Vs1iUdzkB0EA:10 a=EUspDBNiAAAA:8 a=47G9NL9pyX4x7Wg37RYA:9 a=uKXjsCUrEbL0IQVhDsJ9:22 X-Proofpoint-GUID: boRnifX8gSQfu1hDq5k9vaKOk8RyzcGh X-Proofpoint-ORIG-GUID: boRnifX8gSQfu1hDq5k9vaKOk8RyzcGh X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1093,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-03-04_09,2025-03-04_02,2024-11-22_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 mlxscore=0 phishscore=0 adultscore=0 lowpriorityscore=0 mlxlogscore=999 suspectscore=0 bulkscore=0 clxscore=1015 priorityscore=1501 spamscore=0 impostorscore=0 malwarescore=0 classifier=spam authscore=0 adjust=0 reason=mlx scancount=1 engine=8.19.0-2502100000 definitions=main-2503040184 Content-Type: text/plain; charset="utf-8" Add support for TEMP_ALARM LITE PMIC peripherals. This subtype utilizes a pair of registers to configure a warning interrupt threshold temperature and an automatic hardware shutdown threshold temperature. Signed-off-by: David Collins Signed-off-by: Anjelique Melendez --- drivers/thermal/qcom/qcom-spmi-temp-alarm.c | 204 +++++++++++++++++++- 1 file changed, 203 insertions(+), 1 deletion(-) diff --git a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c b/drivers/thermal/= qcom/qcom-spmi-temp-alarm.c index efd2b6534127..2547a69dbd07 100644 --- a/drivers/thermal/qcom/qcom-spmi-temp-alarm.c +++ b/drivers/thermal/qcom/qcom-spmi-temp-alarm.c @@ -23,6 +23,7 @@ #define QPNP_TM_REG_TYPE 0x04 #define QPNP_TM_REG_SUBTYPE 0x05 #define QPNP_TM_REG_STATUS 0x08 +#define QPNP_TM_REG_IRQ_STATUS 0x10 #define QPNP_TM_REG_SHUTDOWN_CTRL1 0x40 #define QPNP_TM_REG_ALARM_CTRL 0x46 =20 @@ -30,14 +31,20 @@ #define QPNP_TM_REG_TEMP_DAC_STG1 0x47 #define QPNP_TM_REG_TEMP_DAC_STG2 0x48 #define QPNP_TM_REG_TEMP_DAC_STG3 0x49 +#define QPNP_TM_REG_LITE_TEMP_CFG1 0x50 +#define QPNP_TM_REG_LITE_TEMP_CFG2 0x51 =20 #define QPNP_TM_TYPE 0x09 #define QPNP_TM_SUBTYPE_GEN1 0x08 #define QPNP_TM_SUBTYPE_GEN2 0x09 +#define QPNP_TM_SUBTYPE_LITE 0xC0 =20 #define STATUS_GEN1_STAGE_MASK GENMASK(1, 0) #define STATUS_GEN2_STATE_MASK GENMASK(6, 4) =20 +/* IRQ status only needed for TEMP_ALARM_LITE */ +#define IRQ_STATUS_MASK BIT(0) + #define SHUTDOWN_CTRL1_OVERRIDE_S2 BIT(6) #define SHUTDOWN_CTRL1_THRESHOLD_MASK GENMASK(1, 0) =20 @@ -45,6 +52,8 @@ =20 #define ALARM_CTRL_FORCE_ENABLE BIT(7) =20 +#define LITE_TEMP_CFG_THRESHOLD_MASK GENMASK(3, 2) + #define THRESH_COUNT 4 #define STAGE_COUNT 3 =20 @@ -89,6 +98,19 @@ static const long temp_dac_max[STAGE_COUNT] =3D { 119375, 159375, 159375 }; =20 +/* + * TEMP_ALARM_LITE has two stages: warning and shutdown with independently + * configured threshold temperatures. + */ + +static const long temp_lite_warning_map[THRESH_COUNT] =3D { + 115000, 125000, 135000, 145000 +}; + +static const long temp_lite_shutdown_map[THRESH_COUNT] =3D { + 135000, 145000, 160000, 175000 +}; + /* Temperature in Milli Celsius reported during stage 0 if no ADC is prese= nt */ #define DEFAULT_TEMP 37000 =20 @@ -198,6 +220,24 @@ static int qpnp_tm_gen2_get_temp_stage(struct qpnp_tm_= chip *chip) return alarm_state_map[ret]; } =20 +/** + * qpnp_tm_lite_get_temp_stage() - return over-temperature stage + * @chip: Pointer to the qpnp_tm chip + * + * Return: alarm interrupt state on success, or errno on failure. + */ +static int qpnp_tm_lite_get_temp_stage(struct qpnp_tm_chip *chip) +{ + u8 reg =3D 0; + int ret; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_IRQ_STATUS, ®); + if (ret < 0) + return ret; + + return reg & IRQ_STATUS_MASK; +} + /* * This function updates the internal temp value based on the * current thermal stage and threshold as well as the previous stage @@ -377,6 +417,96 @@ static const struct thermal_zone_device_ops qpnp_tm_ge= n2_rev2_sensor_ops =3D { .set_trip_temp =3D qpnp_tm_gen2_rev2_set_trip_temp, }; =20 +static int qpnp_tm_lite_set_temp_thresh(struct qpnp_tm_chip *chip, int tri= p, int temp) +{ + int ret, temp_cfg, i; + const long *temp_map; + u16 addr; + u8 reg, thresh; + + if (trip < 0 || trip >=3D STAGE_COUNT) { + dev_err(chip->dev, "invalid TEMP_LITE trip =3D %d\n", trip); + return -EINVAL; + } + + switch (trip) { + case 0: + temp_map =3D temp_lite_warning_map; + addr =3D QPNP_TM_REG_LITE_TEMP_CFG1; + break; + case 1: + /* + * The second trip point is purely in software to facilitate + * a controlled shutdown after the warning threshold is crossed + * but before the automatic hardware shutdown threshold is + * crossed. + */ + return 0; + case 2: + temp_map =3D temp_lite_shutdown_map; + addr =3D QPNP_TM_REG_LITE_TEMP_CFG2; + break; + default: + return 0; + } + + if (temp < temp_map[THRESH_MIN] || temp > temp_map[THRESH_MAX]) { + dev_err(chip->dev, "invalid TEMP_LITE temp =3D %d\n", temp); + return -EINVAL; + } + + thresh =3D 0; + temp_cfg =3D temp_map[thresh]; + for (i =3D THRESH_MAX; i >=3D THRESH_MIN; i--) { + if (temp >=3D temp_map[i]) { + thresh =3D i; + temp_cfg =3D temp_map[i]; + break; + } + } + + if (temp_cfg =3D=3D chip->temp_thresh_map[trip]) + return 0; + + ret =3D qpnp_tm_read(chip, addr, ®); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG read failed, ret=3D%d\n", ret); + return ret; + } + + reg &=3D ~LITE_TEMP_CFG_THRESHOLD_MASK; + reg |=3D FIELD_PREP(LITE_TEMP_CFG_THRESHOLD_MASK, thresh); + + ret =3D qpnp_tm_write(chip, addr, reg); + if (ret < 0) { + dev_err(chip->dev, "LITE_TEMP_CFG write failed, ret=3D%d\n", ret); + return ret; + } + + chip->temp_thresh_map[trip] =3D temp_cfg; + + return 0; +} + +static int qpnp_tm_lite_set_trip_temp(struct thermal_zone_device *tz, + const struct thermal_trip *trip, int temp) +{ + unsigned int trip_index =3D THERMAL_TRIP_PRIV_TO_INT(trip->priv); + struct qpnp_tm_chip *chip =3D thermal_zone_device_priv(tz); + int ret; + + mutex_lock(&chip->lock); + ret =3D qpnp_tm_lite_set_temp_thresh(chip, trip_index, temp); + mutex_unlock(&chip->lock); + + return ret; +} + +static const struct thermal_zone_device_ops qpnp_tm_lite_sensor_ops =3D { + .get_temp =3D qpnp_tm_get_temp, + .set_trip_temp =3D qpnp_tm_lite_set_trip_temp, +}; + static irqreturn_t qpnp_tm_isr(int irq, void *data) { struct qpnp_tm_chip *chip =3D data; @@ -453,6 +583,68 @@ static int qpnp_tm_gen2_rev2_setup(struct qpnp_tm_chip= *chip) return 0; } =20 +/* Configure TEMP_LITE registers based on DT thermal_zone trips */ +static int qpnp_tm_lite_configure_trip_temps_cb(struct thermal_trip *trip,= void *data) +{ + struct qpnp_tm_chip *chip =3D data; + int ret; + + trip->priv =3D THERMAL_INT_TO_TRIP_PRIV(chip->ntrips); + ret =3D qpnp_tm_lite_set_temp_thresh(chip, chip->ntrips, trip->temperatur= e); + chip->ntrips++; + + return ret; +} + +static int qpnp_tm_lite_configure_trip_temps(struct qpnp_tm_chip *chip) +{ + int ret; + + ret =3D thermal_zone_for_each_trip(chip->tz_dev, qpnp_tm_lite_configure_t= rip_temps_cb, chip); + if (ret < 0) + return ret; + + /* Verify that trips are strictly increasing. */ + if (chip->temp_thresh_map[2] <=3D chip->temp_thresh_map[0]) { + dev_err(chip->dev, "Threshold 2=3D%ld <=3D threshold 0=3D%ld\n", + chip->temp_thresh_map[2], chip->temp_thresh_map[0]); + return -EINVAL; + } + + return 0; +} + +/* Read the hardware default TEMP_LITE stage threshold temperatures */ +static int qpnp_tm_lite_setup(struct qpnp_tm_chip *chip) +{ + int ret, thresh; + u8 reg =3D 0; + + /* + * Store the warning trip temp in temp_thresh_map[0] and the shutdown trip + * temp in temp_thresh_map[2]. The second trip point is purely in softwa= re + * to facilitate a controlled shutdown after the warning threshold is + * crossed but before the automatic hardware shutdown threshold is + * crossed. Thus, there is no register to read for the second trip + * point. + */ + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG1, ®); + if (ret < 0) + return ret; + + thresh =3D FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[0] =3D temp_lite_warning_map[thresh]; + + ret =3D qpnp_tm_read(chip, QPNP_TM_REG_LITE_TEMP_CFG2, ®); + if (ret < 0) + return ret; + + thresh =3D FIELD_GET(LITE_TEMP_CFG_THRESHOLD_MASK, reg); + chip->temp_thresh_map[2] =3D temp_lite_shutdown_map[thresh]; + + return 0; +} + static const struct spmi_temp_alarm_data spmi_temp_alarm_data =3D { .ops =3D &qpnp_tm_sensor_ops, .temp_map =3D &temp_map_gen1, @@ -481,6 +673,13 @@ static const struct spmi_temp_alarm_data spmi_temp_ala= rm_gen2_rev2_data =3D { .get_temp_stage =3D qpnp_tm_gen2_get_temp_stage, }; =20 +static const struct spmi_temp_alarm_data spmi_temp_alarm_lite_data =3D { + .ops =3D &qpnp_tm_lite_sensor_ops, + .setup =3D qpnp_tm_lite_setup, + .configure_trip_temps =3D qpnp_tm_lite_configure_trip_temps, + .get_temp_stage =3D qpnp_tm_lite_get_temp_stage, +}; + /* * This function initializes the internal temp value based on only the * current thermal stage and threshold. Setup threshold control and @@ -605,7 +804,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) } =20 if (type !=3D QPNP_TM_TYPE || (subtype !=3D QPNP_TM_SUBTYPE_GEN1 - && subtype !=3D QPNP_TM_SUBTYPE_GEN2)) { + && subtype !=3D QPNP_TM_SUBTYPE_GEN2 + && subtype !=3D QPNP_TM_SUBTYPE_LITE)) { dev_err(&pdev->dev, "invalid type 0x%02x or subtype 0x%02x\n", type, subtype); return -ENODEV; @@ -621,6 +821,8 @@ static int qpnp_tm_probe(struct platform_device *pdev) chip->data =3D &spmi_temp_alarm_gen2_rev1_data; else if (subtype =3D=3D QPNP_TM_SUBTYPE_GEN2) chip->data =3D &spmi_temp_alarm_gen2_data; + else if (subtype =3D=3D QPNP_TM_SUBTYPE_LITE) + chip->data =3D &spmi_temp_alarm_lite_data; else return -ENODEV; =20 --=20 2.34.1