From nobody Mon Dec 15 22:02:23 2025 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id 2A22F202F71; Tue, 4 Mar 2025 11:13:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741086786; cv=none; b=NxUze4AEjKUxxTxDUtY6ijEBkaOgf6Oq/kj/n6RVVZ2sxQ6rZ5FnkcC7HDfJNuqN9SKd5riVAXOUCqTQzXNfFThMEyIq67hMYkPpPjEdV33dYcJKArthYI+ko0ESkPTvsEEQ0Vp/+mNAf7cfRVJTRobT1Lmtts8ha3VpTcb3BFY= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741086786; c=relaxed/simple; bh=TVAgVWIrfQ1KOg00YRqRR9K4C90nDm9ySx02QQq7TSU=; h=From:To:Cc:Subject:Date:Message-Id:In-Reply-To:References: MIME-Version; b=GFJ4h+VVghCTySffNEnnDoIin6YR/9lh6EFnK2Tl9s6hSlqqxrnLGubvSgZsD2d2ocHXoW38oepWUMKi3l5CdcnWEe1Hvtcez+c4cmDqv4ZfSTeejNt5AByZo6fw+duZ7IbkgffpfcKIiD5a6ABIGhzIEdIS8kK6jO0X7Cw2j1Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 88D961007; Tue, 4 Mar 2025 03:13:18 -0800 (PST) Received: from e132581.cambridge.arm.com (e132581.arm.com [10.2.76.71]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPA id 8E55B3F5A1; Tue, 4 Mar 2025 03:13:02 -0800 (PST) From: Leo Yan To: Arnaldo Carvalho de Melo , Namhyung Kim , Ian Rogers , James Clark , Adrian Hunter , Jiri Olsa , "Liang, Kan" , Mark Rutland , Will Deacon , Mike Leach , Graham Woodward , Paschalis.Mpeis@arm.com, linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Cc: Leo Yan Subject: [PATCH v4 06/12] perf arm-spe: Fix load-store operation checking Date: Tue, 4 Mar 2025 11:12:34 +0000 Message-Id: <20250304111240.3378214-7-leo.yan@arm.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304111240.3378214-1-leo.yan@arm.com> References: <20250304111240.3378214-1-leo.yan@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" The ARM_SPE_OP_LD and ARM_SPE_OP_ST operations are secondary operation type, they are overlapping with other second level's operation types belonging to SVE and branch operations. As a result, a non load-store operation can be parsed for data source and memory sample. To fix the issue, this commit introduces a is_ldst_op() macro for checking LDST operation, and apply the checking when synthesize data source and memory samples. Fixes: a89dbc9b988f ("perf arm-spe: Set sample's data source field") Signed-off-by: Leo Yan Reviewed-by: James Clark --- tools/perf/util/arm-spe.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-) diff --git a/tools/perf/util/arm-spe.c b/tools/perf/util/arm-spe.c index 251d214adf7f..0e8e05c87fd7 100644 --- a/tools/perf/util/arm-spe.c +++ b/tools/perf/util/arm-spe.c @@ -37,6 +37,8 @@ #include "../../arch/arm64/include/asm/cputype.h" #define MAX_TIMESTAMP (~0ULL) =20 +#define is_ldst_op(op) (!!((op) & ARM_SPE_OP_LDST)) + struct arm_spe { struct auxtrace auxtrace; struct auxtrace_queues queues; @@ -681,6 +683,10 @@ static u64 arm_spe__synth_data_source(struct arm_spe_q= ueue *speq, { union perf_mem_data_src data_src =3D { .mem_op =3D PERF_MEM_OP_NA }; =20 + /* Only synthesize data source for LDST operations */ + if (!is_ldst_op(record->op)) + return 0; + if (record->op & ARM_SPE_OP_LD) data_src.mem_op =3D PERF_MEM_OP_LOAD; else if (record->op & ARM_SPE_OP_ST) @@ -779,7 +785,7 @@ static int arm_spe_sample(struct arm_spe_queue *speq) * When data_src is zero it means the record is not a memory operation, * skip to synthesize memory sample for this case. */ - if (spe->sample_memory && data_src) { + if (spe->sample_memory && is_ldst_op(record->op)) { err =3D arm_spe__synth_mem_sample(speq, spe->memory_id, data_src); if (err) return err; --=20 2.34.1