From nobody Sun Feb 8 07:14:40 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C34DB1FECBA; Tue, 4 Mar 2025 10:23:19 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741083801; cv=none; b=KRLd5nwqf2x8p+e7W+K7FvC2szOfqSRWxQd30RABGtvXoAc+1JYmp30/nl1RT4aTSXctC1+QA+8mPBrTU4Clg/3AC15xyIP9swgYs51NJbDYYWl5n1x6ziJe9xmHAdxmanePLg2bNmdaXwEaJwHrCSIJEceapzHoWiCm/BzEUko= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741083801; c=relaxed/simple; bh=PxSXHz3lpuMQTovHxgzpLW7oclyaT77hfGzT3uAd88s=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=cjzz/pVrdUqn/WmCsSrzw+gfbj133lOeYlhdUoK5vOY6sNIn28BhF3IZf1f0YQmYrxDf/djjIdY9zZpdM+WDu3LY5Q9cq1gzcV1Dpb/0GLcwuSmaNwD63cCChvdUR4LqTInaLAw8ECilpkSx3gI3mnXNan6mUhn/vZQxSOtfxj0= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=pMz6roM/; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="pMz6roM/" Received: from fllv0035.itg.ti.com ([10.64.41.0]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 524ANBHr3620567 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Mar 2025 04:23:11 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1741083791; bh=t8w9NsJ6B7JwHvl7/jsLYPToyhpWTMcif2X3wj+SSs8=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=pMz6roM/V4iSBkrgznzSIvWKqyB0FeMIEllea6XK8qxhRQOdDsFUCb0gBZZVa1MZa 5l1jM8w+MgY3gsG/jQRUjcG9eFFiblGl8s8/HBs/eFUJM2lO6Pnx/x7djresFkHv01 Q7Iexg4W2iFcWj48j/rwOYe7gDOyJ9ptGlPJYr+k= Received: from DLEE104.ent.ti.com (dlee104.ent.ti.com [157.170.170.34]) by fllv0035.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 524ANBMr092601 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Mar 2025 04:23:11 -0600 Received: from DLEE100.ent.ti.com (157.170.170.30) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 4 Mar 2025 04:23:10 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DLEE100.ent.ti.com (157.170.170.30) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 4 Mar 2025 04:23:11 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 524ANAVD061957; Tue, 4 Mar 2025 04:23:10 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Peter Rosin CC: , , , , Chintan Vankar Subject: [RFC PATCH v2 1/2] devicetree: bindings: mux: reg-mux: Update bindings for reg-mux for new property Date: Tue, 4 Mar 2025 15:53:05 +0530 Message-ID: <20250304102306.2977836-2-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304102306.2977836-1-c-vankar@ti.com> References: <20250304102306.2977836-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" DT-binding of reg-mux is defined in such a way that one need to provide register offset and mask in a "mux-reg-masks" property and corresponding register value in "idle-states" property. This constraint forces to define these values in such a way that "mux-reg-masks" and "idle-states" must be in sync with each other. This implementation would be more complex if specific register or set of registers need to be configured which has large memory space. Introduce a new property "mux-reg-masks-state" which allow to specify offset, mask and value as a tuple in a single property. Signed-off-by: Chintan Vankar --- Link to v1: https://lore.kernel.org/r/20250227202206.2551305-2-c-vankar@ti.com/ Changes from v1 to v2: - Updated dt-bindings for the required conditions as suggested by Conor Dooley and Andrew Davis. .../devicetree/bindings/mux/reg-mux.yaml | 28 +++++++++++++++---- 1 file changed, 23 insertions(+), 5 deletions(-) diff --git a/Documentation/devicetree/bindings/mux/reg-mux.yaml b/Documenta= tion/devicetree/bindings/mux/reg-mux.yaml index dc4be092fc2f..5255e4a06920 100644 --- a/Documentation/devicetree/bindings/mux/reg-mux.yaml +++ b/Documentation/devicetree/bindings/mux/reg-mux.yaml @@ -32,12 +32,30 @@ properties: - description: pre-shifted bitfield mask description: Each entry pair describes a single mux control. =20 - idle-states: true + idle-states: + description: Each entry describes mux register state. =20 -required: - - compatible - - mux-reg-masks - - '#mux-control-cells' + mux-reg-masks-state: + $ref: /schemas/types.yaml#/definitions/uint32-matrix + items: + items: + - description: register offset + - description: pre-shifted bitfield mask + - description: register value to be set + description: This property is an extension of mux-reg-masks which + allows specifying register offset, mask and register + value to be set in a single property. + +allOf: + - not: + required: [mux-reg-masks, mux-reg-masks-state] + + - if: + required: + - mux-reg-masks-state + then: + properties: + idle-states: false =20 additionalProperties: false =20 --=20 2.34.1 From nobody Sun Feb 8 07:14:40 2026 Received: from fllvem-ot04.ext.ti.com (fllvem-ot04.ext.ti.com [198.47.19.246]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F4F41FFC48; Tue, 4 Mar 2025 10:23:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.19.246 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741083804; cv=none; b=tNk/8DUCQ9YKWeHJbUF9hAOr/aqXElzHBSpasN4qhJ/y2U280r1FcCbXJ4lSrZ6gUMu8012KRqq0G5hLDMZFV/LIGAvvbJ1huJJwpgepQWq65wxd52q/oc3/Vy6/hlHpMrdJ3I6ORwZMAbdahFo3WPHWNGGLRJdOqbCsidz3k/Q= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741083804; c=relaxed/simple; bh=tWESoQmUKjqJatR0UQ7XkYBJbE1qLLYMOf3E9UUsLdg=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=t6RHi2quUJMSREQdwijyRjQzafntm8INZLDkmWvcd82AhPLPZGoKwx6mRHim4ahXMUb9IVHX61aDezpEax6Yfh5JHthZWO1zeoZinnfuE2XXs4VHv+VsvTVNDqS3MP5l0ES++Lcn5VN8byEYex8b4LXba3gCSSQRMlMo5psZMAY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=iehOss9Y; arc=none smtp.client-ip=198.47.19.246 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="iehOss9Y" Received: from fllv0034.itg.ti.com ([10.64.40.246]) by fllvem-ot04.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 524ANCOf3566948 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Tue, 4 Mar 2025 04:23:13 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1741083793; bh=FQjjI3qiDDpnex1JzGR5pZ/NsK/GrJhAy79gC5a5LLM=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=iehOss9Y3jTbtoj8w6Zdup68n//OZezJrSSzBey4+RKXqzhlMs3G33JNp+7I+eXxr LhcbLFCQPJaOsBdItomVANts0Ae8Sa8jQKJgWVnaSQzUkH5rr3wOVe2CvB2T4U5UTj aVP/+s5wLOtba85lcNfg6+SZLbgrWKmaEZkf0QPs= Received: from DFLE104.ent.ti.com (dfle104.ent.ti.com [10.64.6.25]) by fllv0034.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 524ANChE016109 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Tue, 4 Mar 2025 04:23:12 -0600 Received: from DFLE100.ent.ti.com (10.64.6.21) by DFLE104.ent.ti.com (10.64.6.25) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Tue, 4 Mar 2025 04:23:12 -0600 Received: from lelvsmtp6.itg.ti.com (10.180.75.249) by DFLE100.ent.ti.com (10.64.6.21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Tue, 4 Mar 2025 04:23:12 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp6.itg.ti.com (8.15.2/8.15.2) with ESMTP id 524ANBFH061987; Tue, 4 Mar 2025 04:23:12 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Peter Rosin CC: , , , , Chintan Vankar Subject: [RFC PATCH v2 2/2] mux: mmio: Extend mmio-mux driver to configure mux with new DT property Date: Tue, 4 Mar 2025 15:53:06 +0530 Message-ID: <20250304102306.2977836-3-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250304102306.2977836-1-c-vankar@ti.com> References: <20250304102306.2977836-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" MMIO mux driver is designed to parse "mux-reg-masks" and "idle-states" property independently to configure mux registers. Drawback of this approach is, while configuring mux-controller one need to specify every register of memory space with offset and mask in "mux-reg-masks" and register state to "idle-states", that would be more complex for devices with large memory space. Add support to extend the mmio mux driver to configure a specific register or set of register in memory space. Signed-off-by: Chintan Vankar --- Link to v1: https://lore.kernel.org/r/20250227202206.2551305-3-c-vankar@ti.com/ Changes from v1 to v2: - Modified driver changes as pointed out by Andrew Davis. drivers/mux/mmio.c | 144 +++++++++++++++++++++++++++++++++++++-------- 1 file changed, 118 insertions(+), 26 deletions(-) diff --git a/drivers/mux/mmio.c b/drivers/mux/mmio.c index 30a952c34365..7253e6305ab8 100644 --- a/drivers/mux/mmio.c +++ b/drivers/mux/mmio.c @@ -2,7 +2,7 @@ /* * MMIO register bitfield-controlled multiplexer driver * - * Copyright (C) 2017 Pengutronix, Philipp Zabel + * Copyright (C) 2017-2025 Pengutronix, Philipp Zabel */ =20 #include @@ -33,10 +33,83 @@ static const struct of_device_id mux_mmio_dt_ids[] =3D { }; MODULE_DEVICE_TABLE(of, mux_mmio_dt_ids); =20 +static int reg_mux_get_controllers(const struct device_node *np, char *pro= p_name) +{ + int ret; + + ret =3D of_property_count_u32_elems(np, prop_name); + if (ret =3D=3D 0 || ret % 2) + ret =3D -EINVAL; + + return ret; +} + +static int reg_mux_get_controllers_extended(const struct device_node *np, = char *prop_name) +{ + int ret; + + ret =3D of_property_count_u32_elems(np, prop_name); + if (ret =3D=3D 0 || ret % 3) + ret =3D -EINVAL; + + return ret; +} + +static int reg_mux_parse_dt(const struct device_node *np, bool *mux_reg_ma= sks_state, + int *num_fields) +{ + int ret; + + if (of_property_present(np, "mux-reg-masks-state")) { + *mux_reg_masks_state =3D true; + ret =3D reg_mux_get_controllers_extended(np, "mux-reg-masks-state"); + if (ret < 0) + return ret; + *num_fields =3D ret / 3; + } else { + ret =3D reg_mux_get_controllers(np, "mux-reg-masks"); + if (ret < 0) + return ret; + *num_fields =3D ret / 2; + } + return ret; +} + +static int mux_reg_set_parameters(const struct device_node *np, char *prop= _name, u32 *reg, + u32 *mask, int index) +{ + int ret; + + ret =3D of_property_read_u32_index(np, prop_name, 2 * index, reg); + if (!ret) + ret =3D of_property_read_u32_index(np, prop_name, 2 * index + 1, mask); + + return ret; +} + +static int mux_reg_set_parameters_extended(const struct device_node *np, c= har *prop_name, u32 *reg, + u32 *mask, u32 *state, int index) +{ + int ret; + + ret =3D of_property_read_u32_index(np, prop_name, 3 * index, reg); + if (ret < 0) + return ret; + + ret =3D of_property_read_u32_index(np, prop_name, 3 * index + 1, mask); + if (ret < 0) + return ret; + + ret =3D of_property_read_u32_index(np, prop_name, 3 * index + 2, state); + + return ret; +} + static int mux_mmio_probe(struct platform_device *pdev) { struct device *dev =3D &pdev->dev; struct device_node *np =3D dev->of_node; + bool mux_reg_masks_state =3D false; struct regmap_field **fields; struct mux_chip *mux_chip; struct regmap *regmap; @@ -59,15 +132,16 @@ static int mux_mmio_probe(struct platform_device *pdev) return dev_err_probe(dev, PTR_ERR(regmap), "failed to get regmap\n"); =20 - ret =3D of_property_count_u32_elems(np, "mux-reg-masks"); - if (ret =3D=3D 0 || ret % 2) - ret =3D -EINVAL; + ret =3D reg_mux_parse_dt(np, &mux_reg_masks_state, &num_fields); if (ret < 0) { - dev_err(dev, "mux-reg-masks property missing or invalid: %d\n", - ret); + if (mux_reg_masks_state) + dev_err(dev, "mux-reg-masks-state property missing or invalid: %d\n", + ret); + else + dev_err(dev, "mux-reg-masks property missing or invalid: %d\n", + ret); return ret; } - num_fields =3D ret / 2; =20 mux_chip =3D devm_mux_chip_alloc(dev, num_fields, num_fields * sizeof(*fields)); @@ -79,19 +153,25 @@ static int mux_mmio_probe(struct platform_device *pdev) for (i =3D 0; i < num_fields; i++) { struct mux_control *mux =3D &mux_chip->mux[i]; struct reg_field field; - s32 idle_state =3D MUX_IDLE_AS_IS; + s32 state, idle_state =3D MUX_IDLE_AS_IS; u32 reg, mask; int bits; =20 - ret =3D of_property_read_u32_index(np, "mux-reg-masks", - 2 * i, ®); - if (!ret) - ret =3D of_property_read_u32_index(np, "mux-reg-masks", - 2 * i + 1, &mask); - if (ret < 0) { - dev_err(dev, "bitfield %d: failed to read mux-reg-masks property: %d\n", - i, ret); - return ret; + if (!mux_reg_masks_state) { + ret =3D mux_reg_set_parameters(np, "mux-reg-masks", ®, &mask, i); + if (ret < 0) { + dev_err(dev, "bitfield %d: failed to read mux-reg-masks property: %d\n= ", + i, ret); + return ret; + } + } else { + ret =3D mux_reg_set_parameters_extended(np, "mux-reg-masks-state", ®, + &mask, &state, i); + if (ret < 0) { + dev_err(dev, "bitfield %d: failed to read custom-states property: %d\n= ", + i, ret); + return ret; + } } =20 field.reg =3D reg; @@ -115,16 +195,28 @@ static int mux_mmio_probe(struct platform_device *pde= v) bits =3D 1 + field.msb - field.lsb; mux->states =3D 1 << bits; =20 - of_property_read_u32_index(np, "idle-states", i, - (u32 *)&idle_state); - if (idle_state !=3D MUX_IDLE_AS_IS) { - if (idle_state < 0 || idle_state >=3D mux->states) { - dev_err(dev, "bitfield: %d: out of range idle state %d\n", - i, idle_state); - return -EINVAL; + if (!mux_reg_masks_state) { + of_property_read_u32_index(np, "idle-states", i, + (u32 *)&idle_state); + if (idle_state !=3D MUX_IDLE_AS_IS) { + if (idle_state < 0 || idle_state >=3D mux->states) { + dev_err(dev, "bitfield: %d: out of range idle state %d\n", + i, idle_state); + return -EINVAL; + } + + mux->idle_state =3D idle_state; + } + } else { + if (state !=3D MUX_IDLE_AS_IS) { + if (state < 0 || state >=3D mux->states) { + dev_err(dev, "bitfield: %d: out of range idle state %d\n", + i, state); + return -EINVAL; + } + + mux->idle_state =3D state; } - - mux->idle_state =3D idle_state; } } =20 --=20 2.34.1