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Peter Anvin" , Andrew Cooper , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 39/40] x86/cacheinfo: Introduce amd_hygon_cpu_has_l3_cache() Date: Tue, 4 Mar 2025 09:51:50 +0100 Message-ID: <20250304085152.51092-40-darwi@linutronix.de> In-Reply-To: <20250304085152.51092-1-darwi@linutronix.de> References: <20250304085152.51092-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Multiple code paths at cacheinfo.c and amd_nb.c check for AMD/Hygon CPUs L3 cache presensce by directly checking leaf 0x80000006 EDX output. Extract that logic into its own function. While at it, rework the AMD/Hygon LLC topology ID caclculation comments for clarity. Signed-off-by: Ahmed S. Darwish --- arch/x86/include/asm/cpuid/types.h | 9 +++++++++ arch/x86/kernel/amd_nb.c | 7 +++---- arch/x86/kernel/cpu/cacheinfo.c | 32 +++++++++++++----------------- 3 files changed, 26 insertions(+), 22 deletions(-) diff --git a/arch/x86/include/asm/cpuid/types.h b/arch/x86/include/asm/cpui= d/types.h index 4d4ab8fc4758..a01cea960ea0 100644 --- a/arch/x86/include/asm/cpuid/types.h +++ b/arch/x86/include/asm/cpuid/types.h @@ -161,4 +161,13 @@ extern const struct leaf_0x2_table cpuid_0x2_table[256= ]; */ #define TLB_0x63_2M_4M_ENTRIES 32 =20 +/* + * CPUID(0x80000006) parsing helpers + */ + +static inline bool amd_hygon_cpu_has_l3_cache(void) +{ + return cpuid_edx(0x80000006); +} + #endif /* _ASM_X86_CPUID_TYPES_H */ diff --git a/arch/x86/kernel/amd_nb.c b/arch/x86/kernel/amd_nb.c index bac8d3b6f12b..e73697cefa16 100644 --- a/arch/x86/kernel/amd_nb.c +++ b/arch/x86/kernel/amd_nb.c @@ -13,7 +13,9 @@ #include #include #include + #include +#include =20 static u32 *flush_words; =20 @@ -92,10 +94,7 @@ static int amd_cache_northbridges(void) if (amd_gart_present()) amd_northbridges.flags |=3D AMD_NB_GART; =20 - /* - * Check for L3 cache presence. - */ - if (!cpuid_edx(0x80000006)) + if (!amd_hygon_cpu_has_l3_cache()) return 0; =20 /* diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index bb934f81dcd1..f85a3ddfc3cc 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -278,29 +278,29 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *= c) return i; } =20 +/* + * AMD/Hygon CPUs may have multiple LLCs if L3 caches exist. + */ + void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c, u16 die_id) { - /* - * We may have multiple LLCs if L3 caches exist, so check if we - * have an L3 cache by looking at the L3 cache CPUID leaf. - */ - if (!cpuid_edx(0x80000006)) + if (!amd_hygon_cpu_has_l3_cache()) return; =20 if (c->x86 < 0x17) { - /* LLC is at the node level. */ + /* Pre-Zen: LLC is at the node level */ c->topo.llc_id =3D die_id; } else if (c->x86 =3D=3D 0x17 && c->x86_model <=3D 0x1F) { /* - * LLC is at the core complex level. - * Core complex ID is ApicId[3] for these processors. + * Family 17h up to 1F models: LLC is at the core + * complex level. Core complex ID is ApicId[3]. */ c->topo.llc_id =3D c->topo.apicid >> 3; } else { /* - * LLC ID is calculated from the number of threads sharing the - * cache. - * */ + * Newer families: LLC ID is calculated from the number + * of threads sharing the L3 cache. + */ u32 eax, ebx, ecx, edx, num_sharing_cache =3D 0; u32 llc_index =3D find_num_cache_leaves(c) - 1; =20 @@ -318,16 +318,12 @@ void cacheinfo_amd_init_llc_id(struct cpuinfo_x86 *c,= u16 die_id) =20 void cacheinfo_hygon_init_llc_id(struct cpuinfo_x86 *c) { - /* - * We may have multiple LLCs if L3 caches exist, so check if we - * have an L3 cache by looking at the L3 cache CPUID leaf. - */ - if (!cpuid_edx(0x80000006)) + if (!amd_hygon_cpu_has_l3_cache()) return; =20 /* - * LLC is at the core complex level. - * Core complex ID is ApicId[3] for these processors. + * Hygons are similar to AMD Family 17h up to 1F models: LLC is + * at the core complex level. Core complex ID is ApicId[3]. */ c->topo.llc_id =3D c->topo.apicid >> 3; } --=20 2.48.1