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Peter Anvin" , Andrew Cooper , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 26/40] x86/cacheinfo: Rename _cpuid4_info_regs to _cpuid4_info Date: Tue, 4 Mar 2025 09:51:37 +0100 Message-ID: <20250304085152.51092-27-darwi@linutronix.de> In-Reply-To: <20250304085152.51092-1-darwi@linutronix.de> References: <20250304085152.51092-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Parent commits decoupled amd_northbridge from _cpuid4_info_regs, moved AMD L3 northbridge cache_disable_0/1 sysfs code to its own file, and splitted AMD vs. Intel leaf 0x4 handling into: amd_fill_cpuid4_info() intel_fill_cpuid4_info() fill_cpuid4_info() After doing all that, the "_cpuid4_info_regs" name becomes a mouthful. It is also not totally accurate, as the structure holds cpuid4 derived information like cache node ID and size -- not just regs. Rename struct _cpuid4_info_regs to _cpuid4_info. That new name also better matches the AMD/Intel leaf 0x4 functions mentioned above. Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 22 +++++++++++----------- 1 file changed, 11 insertions(+), 11 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index cc320817cfc3..2d4180b961f4 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -159,7 +159,7 @@ union _cpuid4_leaf_ecx { u32 full; }; =20 -struct _cpuid4_info_regs { +struct _cpuid4_info { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; union _cpuid4_leaf_ecx ecx; @@ -295,7 +295,7 @@ static void legacy_amd_cpuid4(int index, union _cpuid4_= leaf_eax *eax, (ebx->split.ways_of_associativity + 1) - 1; } =20 -static int cpuid4_info_fill_done(struct _cpuid4_info_regs *id4, union _cpu= id4_leaf_eax eax, +static int cpuid4_info_fill_done(struct _cpuid4_info *id4, union _cpuid4_l= eaf_eax eax, union _cpuid4_leaf_ebx ebx, union _cpuid4_leaf_ecx ecx) { if (eax.split.type =3D=3D CTYPE_NULL) @@ -312,7 +312,7 @@ static int cpuid4_info_fill_done(struct _cpuid4_info_re= gs *id4, union _cpuid4_le return 0; } =20 -static int amd_fill_cpuid4_info(int index, struct _cpuid4_info_regs *id4) +static int amd_fill_cpuid4_info(int index, struct _cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; @@ -327,7 +327,7 @@ static int amd_fill_cpuid4_info(int index, struct _cpui= d4_info_regs *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int intel_fill_cpuid4_info(int index, struct _cpuid4_info_regs *id4) +static int intel_fill_cpuid4_info(int index, struct _cpuid4_info *id4) { union _cpuid4_leaf_eax eax; union _cpuid4_leaf_ebx ebx; @@ -339,7 +339,7 @@ static int intel_fill_cpuid4_info(int index, struct _cp= uid4_info_regs *id4) return cpuid4_info_fill_done(id4, eax, ebx, ecx); } =20 -static int fill_cpuid4_info(int index, struct _cpuid4_info_regs *id4) +static int fill_cpuid4_info(int index, struct _cpuid4_info *id4) { return x86_vendor_amd_or_hygon(boot_cpu_data.x86_vendor) ? amd_fill_cpuid4_info(index, id4) : @@ -473,7 +473,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) * parameters cpuid leaf to find the cache details */ for (i =3D 0; i < ci->num_leaves; i++) { - struct _cpuid4_info_regs id4 =3D {}; + struct _cpuid4_info id4 =3D {}; int retval; =20 retval =3D intel_fill_cpuid4_info(i, &id4); @@ -560,7 +560,7 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) } =20 static int __cache_amd_cpumap_setup(unsigned int cpu, int index, - const struct _cpuid4_info_regs *id4) + const struct _cpuid4_info *id4) { struct cpu_cacheinfo *this_cpu_ci; struct cacheinfo *ci; @@ -617,7 +617,7 @@ static int __cache_amd_cpumap_setup(unsigned int cpu, i= nt index, } =20 static void __cache_cpumap_setup(unsigned int cpu, int index, - const struct _cpuid4_info_regs *id4) + const struct _cpuid4_info *id4) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); struct cacheinfo *ci, *sibling_ci; @@ -650,7 +650,7 @@ static void __cache_cpumap_setup(unsigned int cpu, int = index, } } =20 -static void ci_info_init(struct cacheinfo *ci, const struct _cpuid4_info_r= egs *id4, +static void ci_info_init(struct cacheinfo *ci, const struct _cpuid4_info *= id4, struct amd_northbridge *nb) { ci->id =3D id4->id; @@ -681,7 +681,7 @@ int init_cache_level(unsigned int cpu) * ECX as cache index. Then right shift apicid by the number's order to get * cache id for this cache node. */ -static void get_cache_id(int cpu, struct _cpuid4_info_regs *id4) +static void get_cache_id(int cpu, struct _cpuid4_info *id4) { struct cpuinfo_x86 *c =3D &cpu_data(cpu); unsigned long num_threads_sharing; @@ -696,8 +696,8 @@ int populate_cache_leaves(unsigned int cpu) { struct cpu_cacheinfo *this_cpu_ci =3D get_cpu_cacheinfo(cpu); struct cacheinfo *ci =3D this_cpu_ci->info_list; - struct _cpuid4_info_regs id4 =3D {}; struct amd_northbridge *nb =3D NULL; + struct _cpuid4_info id4 =3D {}; int idx, ret; =20 for (idx =3D 0; idx < this_cpu_ci->num_leaves; idx++) { --=20 2.48.1