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Peter Anvin" , Andrew Cooper , x86@kernel.org, x86-cpuid@lists.linux.dev, LKML , "Ahmed S. Darwish" Subject: [PATCH v1 14/40] x86/cacheinfo: Refactor leaf 0x2 cache descriptor lookup Date: Tue, 4 Mar 2025 09:51:25 +0100 Message-ID: <20250304085152.51092-15-darwi@linutronix.de> In-Reply-To: <20250304085152.51092-1-darwi@linutronix.de> References: <20250304085152.51092-1-darwi@linutronix.de> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Thomas Gleixner Extract the cache descriptor lookup logic out of the leaf 0x2 parsing code and into a dedicated function. This disentangles such lookup from the deeply nested leaf 0x2 parsing loop. Remove the cache table termination entry, as it is no longer needed after the ARRAY_SIZE()-based lookup. [darwi: Move refactoring logic into this separate commit + commit log. Remove the cache table termination entry.] Signed-off-by: Thomas Gleixner Signed-off-by: Ahmed S. Darwish --- arch/x86/kernel/cpu/cacheinfo.c | 45 +++++++++++++++------------------ 1 file changed, 20 insertions(+), 25 deletions(-) diff --git a/arch/x86/kernel/cpu/cacheinfo.c b/arch/x86/kernel/cpu/cacheinf= o.c index ebd72016e7a2..3be7ea8444ec 100644 --- a/arch/x86/kernel/cpu/cacheinfo.c +++ b/arch/x86/kernel/cpu/cacheinfo.c @@ -123,7 +123,6 @@ static const struct _cache_table cache_table[] =3D { 0xea, LVL_3, MB(12) }, /* 24-way set assoc, 64 byte line size */ { 0xeb, LVL_3, MB(18) }, /* 24-way set assoc, 64 byte line size */ { 0xec, LVL_3, MB(24) }, /* 24-way set assoc, 64 byte line size */ - { 0x00, 0, 0} }; =20 =20 @@ -728,6 +727,16 @@ void init_hygon_cacheinfo(struct cpuinfo_x86 *c) ci->num_leaves =3D find_num_cache_leaves(c); } =20 +static const struct _cache_table *cache_table_get(u8 desc) +{ + for (int i =3D 0; i < ARRAY_SIZE(cache_table); i++) { + if (cache_table[i].descriptor =3D=3D desc) + return &cache_table[i]; + } + + return NULL; +} + void init_intel_cacheinfo(struct cpuinfo_x86 *c) { /* Cache sizes */ @@ -784,35 +793,21 @@ void init_intel_cacheinfo(struct cpuinfo_x86 *c) =20 /* Don't use CPUID(2) if CPUID(4) is supported. */ if (!ci->num_leaves && c->cpuid_level > 1) { + const struct _cache_table *entry; union leaf_0x2_regs regs; u8 *desc; =20 get_leaf_0x2_regs(®s); for_each_leaf_0x2_desc(regs, desc) { - unsigned char k =3D 0; - - /* look up this descriptor in the table */ - while (cache_table[k].descriptor !=3D 0) { - if (cache_table[k].descriptor =3D=3D *desc) { - switch (cache_table[k].cache_type) { - case LVL_1_INST: - l1i +=3D cache_table[k].size; - break; - case LVL_1_DATA: - l1d +=3D cache_table[k].size; - break; - case LVL_2: - l2 +=3D cache_table[k].size; - break; - case LVL_3: - l3 +=3D cache_table[k].size; - break; - } - - break; - } - - k++; + entry =3D cache_table_get(*desc); + if (!entry) + continue; + + switch (entry->cache_type) { + case LVL_1_INST: l1i +=3D entry->size; break; + case LVL_1_DATA: l1d +=3D entry->size; break; + case LVL_2: l2 +=3D entry->size; break; + case LVL_3: l3 +=3D entry->size; break; } } } --=20 2.48.1