From nobody Mon Feb 9 03:45:47 2026 Received: from foss.arm.com (foss.arm.com [217.140.110.172]) by smtp.subspace.kernel.org (Postfix) with ESMTP id B08231F4720; Tue, 4 Mar 2025 01:31:03 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=217.140.110.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741051865; cv=none; b=gq82FJQWAuPTZ3DtmKU6IQVp19GxNnU8JQNY/OAZaEAiy9e35HHHaZX2RkZdIQn2KmSSMdQTS7+UayUHWs0A1+QRsuwVaxwrJ8hYO9l6QZIJANgWTBcyJbpcr54KXAWL9qjD2IPWugKrvbHR22XAzZQc61Ozh4Alb95q5cISsoI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741051865; c=relaxed/simple; bh=JU9dcV6U51gzrsCqd2hp3HXL7DS+uvkGIHdqLqYOgvQ=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=dL61dtHll1PAMpwOpy2rDOS3TAk/YEVJ4VivERZXwe++r2htx62bvSboMCA/5TNvy8nGztWLYkXPE46uBbKHCLGvZ75UYAO3gWkdIHebSiyw69aOEN/9kvDSCwloKp2H8vlJfYWuLMsvh/jcLesbNra4VwyPEjwKu8N3sLdrvtQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com; spf=pass smtp.mailfrom=arm.com; arc=none smtp.client-ip=217.140.110.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=arm.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=arm.com Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 04E31FEC; Mon, 3 Mar 2025 17:31:17 -0800 (PST) Received: from localhost.localdomain (usa-sjc-mx-foss1.foss.arm.com [172.31.20.19]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 455873F673; Mon, 3 Mar 2025 17:31:01 -0800 (PST) From: Andre Przywara To: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen-Yu Tsai , Jernej Skrabec , Samuel Holland Cc: Philipp Zabel , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-sunxi@lists.linux.dev, linux-kernel@vger.kernel.org Subject: [PATCH v3 14/15] clk: sunxi-ng: a523: add reset lines Date: Tue, 4 Mar 2025 01:28:04 +0000 Message-ID: <20250304012805.28594-15-andre.przywara@arm.com> X-Mailer: git-send-email 2.46.3 In-Reply-To: <20250304012805.28594-1-andre.przywara@arm.com> References: <20250304012805.28594-1-andre.przywara@arm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Allwinner SoCs do not contain a separate reset controller, instead the reset lines for the various devices are integrated into the "BGR" (Bus Gate / Reset) registers, for each device group: one for all UARTs, one for all SPI interfaces, and so on. The Allwinner CCU driver also doubles as a reset provider, and since the reset lines are indeed just single bits in those BGR register, we can represent them easily in an array of structs, just containing the register offset and the bit number. Add the location of the reset bits for all devices in the A523/T527 SoCs, using the existing sunxi CCU infrastructure. Signed-off-by: Andre Przywara --- drivers/clk/sunxi-ng/ccu-sun55i-a523.c | 84 ++++++++++++++++++++++++++ 1 file changed, 84 insertions(+) diff --git a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c b/drivers/clk/sunxi-ng/= ccu-sun55i-a523.c index 7d46a5ccbb051..7b2ac2705773f 100644 --- a/drivers/clk/sunxi-ng/ccu-sun55i-a523.c +++ b/drivers/clk/sunxi-ng/ccu-sun55i-a523.c @@ -1526,11 +1526,95 @@ static struct clk_hw_onecell_data sun55i_a523_hw_cl= ks =3D { }, }; =20 +static struct ccu_reset_map sun55i_a523_ccu_resets[] =3D { + [RST_MBUS] =3D { 0x540, BIT(30) }, + [RST_BUS_NSI] =3D { 0x54c, BIT(16) }, + [RST_BUS_DE] =3D { 0x60c, BIT(16) }, + [RST_BUS_DI] =3D { 0x62c, BIT(16) }, + [RST_BUS_G2D] =3D { 0x63c, BIT(16) }, + [RST_BUS_SYS] =3D { 0x64c, BIT(16) }, + [RST_BUS_GPU] =3D { 0x67c, BIT(16) }, + [RST_BUS_CE] =3D { 0x68c, BIT(16) }, + [RST_BUS_SYS_CE] =3D { 0x68c, BIT(17) }, + [RST_BUS_VE] =3D { 0x69c, BIT(16) }, + [RST_BUS_DMA] =3D { 0x70c, BIT(16) }, + [RST_BUS_MSGBOX] =3D { 0x71c, BIT(16) }, + [RST_BUS_SPINLOCK] =3D { 0x72c, BIT(16) }, + [RST_BUS_CPUXTIMER] =3D { 0x74c, BIT(16) }, + [RST_BUS_DBG] =3D { 0x78c, BIT(16) }, + [RST_BUS_PWM0] =3D { 0x7ac, BIT(16) }, + [RST_BUS_PWM1] =3D { 0x7ac, BIT(17) }, + [RST_BUS_DRAM] =3D { 0x80c, BIT(16) }, + [RST_BUS_NAND] =3D { 0x82c, BIT(16) }, + [RST_BUS_MMC0] =3D { 0x84c, BIT(16) }, + [RST_BUS_MMC1] =3D { 0x84c, BIT(17) }, + [RST_BUS_MMC2] =3D { 0x84c, BIT(18) }, + [RST_BUS_SYSDAP] =3D { 0x88c, BIT(16) }, + [RST_BUS_UART0] =3D { 0x90c, BIT(16) }, + [RST_BUS_UART1] =3D { 0x90c, BIT(17) }, + [RST_BUS_UART2] =3D { 0x90c, BIT(18) }, + [RST_BUS_UART3] =3D { 0x90c, BIT(19) }, + [RST_BUS_UART4] =3D { 0x90c, BIT(20) }, + [RST_BUS_UART5] =3D { 0x90c, BIT(21) }, + [RST_BUS_UART6] =3D { 0x90c, BIT(22) }, + [RST_BUS_UART7] =3D { 0x90c, BIT(23) }, + [RST_BUS_I2C0] =3D { 0x91c, BIT(16) }, + [RST_BUS_I2C1] =3D { 0x91c, BIT(17) }, + [RST_BUS_I2C2] =3D { 0x91c, BIT(18) }, + [RST_BUS_I2C3] =3D { 0x91c, BIT(19) }, + [RST_BUS_I2C4] =3D { 0x91c, BIT(20) }, + [RST_BUS_I2C5] =3D { 0x91c, BIT(21) }, + [RST_BUS_CAN] =3D { 0x92c, BIT(16) }, + [RST_BUS_SPI0] =3D { 0x96c, BIT(16) }, + [RST_BUS_SPI1] =3D { 0x96c, BIT(17) }, + [RST_BUS_SPI2] =3D { 0x96c, BIT(18) }, + [RST_BUS_SPIFC] =3D { 0x96c, BIT(19) }, + [RST_BUS_EMAC0] =3D { 0x97c, BIT(16) }, + [RST_BUS_EMAC1] =3D { 0x98c, BIT(16) | BIT(17) }, /* GMAC1-AXI */ + [RST_BUS_IR_RX] =3D { 0x99c, BIT(16) }, + [RST_BUS_IR_TX] =3D { 0x9cc, BIT(16) }, + [RST_BUS_GPADC0] =3D { 0x9ec, BIT(16) }, + [RST_BUS_GPADC1] =3D { 0x9ec, BIT(17) }, + [RST_BUS_THS] =3D { 0x9fc, BIT(16) }, + [RST_USB_PHY0] =3D { 0xa70, BIT(30) }, + [RST_USB_PHY1] =3D { 0xa74, BIT(30) }, + [RST_BUS_OHCI0] =3D { 0xa8c, BIT(16) }, + [RST_BUS_OHCI1] =3D { 0xa8c, BIT(17) }, + [RST_BUS_EHCI0] =3D { 0xa8c, BIT(20) }, + [RST_BUS_EHCI1] =3D { 0xa8c, BIT(21) }, + [RST_BUS_OTG] =3D { 0xa8c, BIT(24) }, + [RST_BUS_3] =3D { 0xa8c, BIT(25) }, /* BSP + register */ + [RST_BUS_LRADC] =3D { 0xa9c, BIT(16) }, + [RST_BUS_PCIE_USB3] =3D { 0xaac, BIT(16) }, + [RST_BUS_DISPLAY0_TOP] =3D { 0xabc, BIT(16) }, + [RST_BUS_DISPLAY1_TOP] =3D { 0xacc, BIT(16) }, + [RST_BUS_HDMI_MAIN] =3D { 0xb1c, BIT(16) }, + [RST_BUS_HDMI_SUB] =3D { 0xb1c, BIT(17) }, + [RST_BUS_MIPI_DSI0] =3D { 0xb4c, BIT(16) }, + [RST_BUS_MIPI_DSI1] =3D { 0xb4c, BIT(17) }, + [RST_BUS_TCON_LCD0] =3D { 0xb7c, BIT(16) }, + [RST_BUS_TCON_LCD1] =3D { 0xb7c, BIT(17) }, + [RST_BUS_TCON_LCD2] =3D { 0xb7c, BIT(18) }, + [RST_BUS_TCON_TV0] =3D { 0xb9c, BIT(16) }, + [RST_BUS_TCON_TV1] =3D { 0xb9c, BIT(17) }, + [RST_BUS_LVDS0] =3D { 0xbac, BIT(16) }, + [RST_BUS_LVDS1] =3D { 0xbac, BIT(17) }, + [RST_BUS_EDP] =3D { 0xbbc, BIT(16) }, + [RST_BUS_VIDEO_OUT0] =3D { 0xbcc, BIT(16) }, + [RST_BUS_VIDEO_OUT1] =3D { 0xbcc, BIT(17) }, + [RST_BUS_LEDC] =3D { 0xbfc, BIT(16) }, + [RST_BUS_CSI] =3D { 0xc1c, BIT(16) }, + [RST_BUS_ISP] =3D { 0xc2c, BIT(16) }, /* BSP + register */ +}; + static const struct sunxi_ccu_desc sun55i_a523_ccu_desc =3D { .ccu_clks =3D sun55i_a523_ccu_clks, .num_ccu_clks =3D ARRAY_SIZE(sun55i_a523_ccu_clks), =20 .hw_clks =3D &sun55i_a523_hw_clks, + + .resets =3D sun55i_a523_ccu_resets, + .num_resets =3D ARRAY_SIZE(sun55i_a523_ccu_resets), }; =20 static const u32 pll_regs[] =3D { --=20 2.46.3