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Tue, 04 Mar 2025 02:58:07 -0800 (PST) From: Abel Vesa Date: Tue, 04 Mar 2025 12:57:46 +0200 Subject: [PATCH v6 1/4] arm64: dts: qcom: x1e80100-crd: Describe the Parade PS8830 retimers Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-x1e80100-dts-crd-t14s-enable-typec-retimers-v6-1-e5a49fae4e94@linaro.org> References: <20250304-x1e80100-dts-crd-t14s-enable-typec-retimers-v6-0-e5a49fae4e94@linaro.org> In-Reply-To: <20250304-x1e80100-dts-crd-t14s-enable-typec-retimers-v6-0-e5a49fae4e94@linaro.org> To: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley Cc: Johan Hovold , Dmitry Baryshkov , Rajendra Nayak , Sibi Sankar , Christophe JAILLET , Trilok Soni , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Abel Vesa , Johan Hovold X-Mailer: b4 0.15-dev-dedf8 X-Developer-Signature: v=1; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The X Elite CRD board comes with 3 Parade PS8830 retimers, one for each Type-C port. These handle the orientation and altmode switching and are controlled over I2C. In the connection chain, they sit between the USB/DisplayPort combo PHY and the Type-C connector. Describe the retimers and all gpio controlled voltage regulators used by each retimer. Also, modify the pmic glink graph to include the retimers in between the SuperSpeed/Sideband in endpoints and the QMP PHY out endpoints. Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 449 +++++++++++++++++++++++++++++++= +++- 1 file changed, 443 insertions(+), 6 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qco= m/x1-crd.dtsi index 296b41409ad1797d1da837c2674d6048932ff8ee..34e203fb7a4bfd781cf268429b3= e4174e8d19bf9 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -97,7 +97,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss0_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + remote-endpoint =3D <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss0_con_sbu_out>; }; }; }; @@ -126,7 +134,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss1_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + remote-endpoint =3D <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss1_con_sbu_out>; }; }; }; @@ -155,7 +171,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss2_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss2_qmpphy_out>; + remote-endpoint =3D <&retimer_ss2_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss2_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss2_con_sbu_out>; }; }; }; @@ -308,6 +332,150 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; =20 + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p15: regulator-rtmr2-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 189 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb2_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_1p8: regulator-rtmr2-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 126 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb2_pwr_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr2_3p3: regulator-rtmr2-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR2_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 187 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb2_pwr_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible =3D "regulator-fixed"; =20 @@ -728,6 +896,177 @@ keyboard@3a { }; }; =20 +&i2c1 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x08>; + + clocks =3D <&rpmhcc RPMH_RF_CLK5>; + + vdd-supply =3D <&vreg_rtmr2_1p15>; + vdd33-supply =3D <&vreg_rtmr2_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr2_3p3>; + vddar-supply =3D <&vreg_rtmr2_1p15>; + vddat-supply =3D <&vreg_rtmr2_1p15>; + vddio-supply =3D <&vreg_rtmr2_1p8>; + + reset-gpios =3D <&tlmm 185 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr2_default>; + pinctrl-names =3D "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss2_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss2_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss2_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss2_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss2_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss2_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c3 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x08>; + + clocks =3D <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply =3D <&vreg_rtmr0_1p15>; + vdd33-supply =3D <&vreg_rtmr0_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr0_3p3>; + vddar-supply =3D <&vreg_rtmr0_1p15>; + vddat-supply =3D <&vreg_rtmr0_1p15>; + vddio-supply =3D <&vreg_rtmr0_1p8>; + + reset-gpios =3D <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr0_default>; + pinctrl-names =3D "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + +&i2c7 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + clocks =3D <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply =3D <&vreg_rtmr1_1p15>; + vdd33-supply =3D <&vreg_rtmr1_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr1_3p3>; + vddar-supply =3D <&vreg_rtmr1_1p15>; + vddat-supply =3D <&vreg_rtmr1_1p15>; + vddio-supply =3D <&vreg_rtmr1_1p8>; + + reset-gpios =3D <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr1_default>; + pinctrl-names =3D "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + &i2c8 { clock-frequency =3D <400000>; =20 @@ -876,6 +1215,26 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins =3D "gpio10"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins =3D "gpio11"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pm8550ve_8_gpios { misc_3p3_reg_en: misc-3p3-reg-en-state { pins =3D "gpio6"; @@ -889,6 +1248,17 @@ misc_3p3_reg_en: misc-3p3-reg-en-state { }; }; =20 +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins =3D "gpio4"; @@ -899,6 +1269,17 @@ edp_bl_en: edp-bl-en-state { }; }; =20 +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &qupv3_0 { status =3D "okay"; }; @@ -1136,6 +1517,20 @@ wake-n-pins { }; }; =20 + rtmr1_default: rtmr1-reset-n-active-state { + pins =3D "gpio176"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + rtmr2_default: rtmr2-reset-n-active-state { + pins =3D "gpio185"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + tpad_default: tpad-default-state { pins =3D "gpio3"; function =3D "gpio"; @@ -1157,6 +1552,48 @@ reset-n-pins { }; }; =20 + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins =3D "gpio188"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb1_pwr_1p8_reg_en: usb1-pwr-1p8-reg-en-state { + pins =3D "gpio175"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb1_pwr_3p3_reg_en: usb1-pwr-3p3-reg-en-state { + pins =3D "gpio186"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb2_pwr_1p15_reg_en: usb2-pwr-1p15-reg-en-state { + pins =3D "gpio189"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb2_pwr_1p8_reg_en: usb2-pwr-1p8-reg-en-state { + pins =3D "gpio126"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb2_pwr_3p3_reg_en: usb2-pwr-3p3-reg-en-state { + pins =3D "gpio187"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + wcd_default: wcd-reset-n-active-state { pins =3D "gpio191"; function =3D "gpio"; @@ -1207,7 +1644,7 @@ &usb_1_ss0_dwc3_hs { }; =20 &usb_1_ss0_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + remote-endpoint =3D <&retimer_ss0_ss_in>; }; =20 &usb_1_ss1_hsphy { @@ -1239,7 +1676,7 @@ &usb_1_ss1_dwc3_hs { }; =20 &usb_1_ss1_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + remote-endpoint =3D <&retimer_ss1_ss_in>; }; =20 &usb_1_ss2_hsphy { @@ -1271,5 +1708,5 @@ &usb_1_ss2_dwc3_hs { }; =20 &usb_1_ss2_qmpphy_out { - remote-endpoint =3D <&pmic_glink_ss2_ss_in>; + remote-endpoint =3D <&retimer_ss2_ss_in>; }; --=20 2.34.1 From nobody Tue Dec 16 23:45:16 2025 Received: from mail-ej1-f41.google.com (mail-ej1-f41.google.com [209.85.218.41]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E67F1FF1A7 for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The X Elite CRD provides external DisplayPort on all 3 USB Type-C ports. Each one of this ports is connected to a dedicated DisplayPort controller. Due to support missing in the USB/DisplayPort combo PHY driver, the external DisplayPort is limited to 2 lanes. So enable all 3 remaining DisplayPort controllers and limit their data lanes number to 2. Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Abel Vesa --- arch/arm64/boot/dts/qcom/x1-crd.dtsi | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1-crd.dtsi b/arch/arm64/boot/dts/qco= m/x1-crd.dtsi index 34e203fb7a4bfd781cf268429b3e4174e8d19bf9..53f329c320190afa263fb8d8028= 828022464fd99 100644 --- a/arch/arm64/boot/dts/qcom/x1-crd.dtsi +++ b/arch/arm64/boot/dts/qcom/x1-crd.dtsi @@ -1117,6 +1117,30 @@ &mdss { status =3D "okay"; }; =20 +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1>; +}; + +&mdss_dp1 { + status =3D "okay"; +}; + +&mdss_dp1_out { + data-lanes =3D <0 1>; +}; + +&mdss_dp2 { + status =3D "okay"; +}; + +&mdss_dp2_out { + data-lanes =3D <0 1>; +}; + &mdss_dp3 { compatible =3D "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; --=20 2.34.1 From nobody Tue Dec 16 23:45:16 2025 Received: from mail-ej1-f49.google.com (mail-ej1-f49.google.com [209.85.218.49]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DC58820297F for ; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Lenovo ThinkPad T14s Gen6 laptop comes with 3 Parade PS8830 retimers, one for each Type-C port. These handle the orientation and altmode switching and are controlled over I2C. In the connection chain, they sit between the USB/DisplayPort combo PHY and the Type-C connector. Describe the retimers and all gpio controlled voltage regulators used by each retimer. Also, modify the pmic glink graph to include the retimers in between the SuperSpeed/Sideband in endpoints and the QMP PHY out endpoints. Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Abel Vesa --- .../dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts | 304 +++++++++++++++++= +++- 1 file changed, 300 insertions(+), 4 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/a= rch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts index b2c2347f54fa65f9355f0d7c008119e95bb64fb2..9c0903b8436396b2fe6e17ee3bc= 4d454cb5a0f8b 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts @@ -92,7 +92,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss0_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + remote-endpoint =3D <&retimer_ss0_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss0_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss0_con_sbu_out>; }; }; }; @@ -121,7 +129,15 @@ port@1 { reg =3D <1>; =20 pmic_glink_ss1_ss_in: endpoint { - remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + remote-endpoint =3D <&retimer_ss1_ss_out>; + }; + }; + + port@2 { + reg =3D <2>; + + pmic_glink_ss1_con_sbu_in: endpoint { + remote-endpoint =3D <&retimer_ss1_con_sbu_out>; }; }; }; @@ -169,6 +185,102 @@ vreg_nvme: regulator-nvme { regulator-boot-on; }; =20 + vreg_rtmr0_1p15: regulator-rtmr0-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&pmc8380_5_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_1p8: regulator-rtmr0-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&pm8550ve_9_gpios 8 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr0_3p3: regulator-rtmr0-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR0_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&pm8550_gpios 11 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb0_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p15: regulator-rtmr1-1p15 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P15"; + regulator-min-microvolt =3D <1150000>; + regulator-max-microvolt =3D <1150000>; + + gpio =3D <&tlmm 188 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_1p15_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_1p8: regulator-rtmr1-1p8 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_1P8"; + regulator-min-microvolt =3D <1800000>; + regulator-max-microvolt =3D <1800000>; + + gpio =3D <&tlmm 175 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_1p8_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + + vreg_rtmr1_3p3: regulator-rtmr1-3p3 { + compatible =3D "regulator-fixed"; + + regulator-name =3D "VREG_RTMR1_3P3"; + regulator-min-microvolt =3D <3300000>; + regulator-max-microvolt =3D <3300000>; + + gpio =3D <&tlmm 186 GPIO_ACTIVE_HIGH>; + enable-active-high; + + pinctrl-0 =3D <&usb1_pwr_3p3_reg_en>; + pinctrl-names =3D "default"; + + regulator-boot-on; + }; + vph_pwr: regulator-vph-pwr { compatible =3D "regulator-fixed"; =20 @@ -607,6 +719,63 @@ keyboard@3a { }; }; =20 +&i2c3 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x08>; + + clocks =3D <&rpmhcc RPMH_RF_CLK3>; + + vdd-supply =3D <&vreg_rtmr0_1p15>; + vdd33-supply =3D <&vreg_rtmr0_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr0_3p3>; + vddar-supply =3D <&vreg_rtmr0_1p15>; + vddat-supply =3D <&vreg_rtmr0_1p15>; + vddio-supply =3D <&vreg_rtmr0_1p8>; + + reset-gpios =3D <&pm8550_gpios 10 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr0_default>; + pinctrl-names =3D "default"; + + orientation-switch; + retimer-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss0_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss0_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss0_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss0_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss0_con_sbu_in>; + }; + }; + }; + }; +}; + &i2c5 { clock-frequency =3D <400000>; =20 @@ -655,6 +824,63 @@ eusb6_repeater: redriver@4f { }; }; =20 +&i2c7 { + clock-frequency =3D <400000>; + + status =3D "okay"; + + typec-mux@8 { + compatible =3D "parade,ps8830"; + reg =3D <0x8>; + + clocks =3D <&rpmhcc RPMH_RF_CLK4>; + + vdd-supply =3D <&vreg_rtmr1_1p15>; + vdd33-supply =3D <&vreg_rtmr1_3p3>; + vdd33-cap-supply =3D <&vreg_rtmr1_3p3>; + vddar-supply =3D <&vreg_rtmr1_1p15>; + vddat-supply =3D <&vreg_rtmr1_1p15>; + vddio-supply =3D <&vreg_rtmr1_1p8>; + + reset-gpios =3D <&tlmm 176 GPIO_ACTIVE_LOW>; + + pinctrl-0 =3D <&rtmr1_default>; + pinctrl-names =3D "default"; + + retimer-switch; + orientation-switch; + + ports { + #address-cells =3D <1>; + #size-cells =3D <0>; + + port@0 { + reg =3D <0>; + + retimer_ss1_ss_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_ss_in>; + }; + }; + + port@1 { + reg =3D <1>; + + retimer_ss1_ss_in: endpoint { + remote-endpoint =3D <&usb_1_ss1_qmpphy_out>; + }; + }; + + port@2 { + reg =3D <2>; + + retimer_ss1_con_sbu_out: endpoint { + remote-endpoint =3D <&pmic_glink_ss1_con_sbu_in>; + }; + }; + }; + }; +}; + &i2c8 { clock-frequency =3D <400000>; =20 @@ -777,6 +1003,37 @@ &pcie6a_phy { status =3D "okay"; }; =20 +&pm8550_gpios { + rtmr0_default: rtmr0-reset-n-active-state { + pins =3D "gpio10"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; + + usb0_3p3_reg_en: usb0-3p3-reg-en-state { + pins =3D "gpio11"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + +&pm8550ve_9_gpios { + usb0_1p8_reg_en: usb0-1p8-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &pmc8380_3_gpios { edp_bl_en: edp-bl-en-state { pins =3D "gpio4"; @@ -787,6 +1044,17 @@ edp_bl_en: edp-bl-en-state { }; }; =20 +&pmc8380_5_gpios { + usb0_pwr_1p15_reg_en: usb0-pwr-1p15-reg-en-state { + pins =3D "gpio8"; + function =3D "normal"; + power-source =3D <1>; /* 1.8V */ + bias-disable; + input-disable; + output-enable; + }; +}; + &qupv3_0 { status =3D "okay"; }; @@ -1007,6 +1275,34 @@ wake-n-pins { }; }; =20 + rtmr1_default: rtmr1-reset-n-active-state { + pins =3D "gpio176"; + function =3D "gpio"; + drive-strength =3D <2>; + bias-disable; + }; + + usb1_pwr_1p15_reg_en: usb1-pwr-1p15-reg-en-state { + pins =3D "gpio188"; + function =3D "gpio"; + drive-strength =3D <2>; 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a=openpgp; fpr=6AFF162D57F4223A8770EF5AF7BF214136F41FAE The Lenovo ThinkPad T14s Gen6 provides external DisplayPort on all 2 USB Type-C ports. Each one of this ports is connected to a dedicated DisplayPort controller. Due to support missing in the USB/DisplayPort combo PHY driver, the external DisplayPort is limited to 2 lanes. So enable the first and second DisplayPort controllers and limit their data lanes number to 2. Reviewed-by: Konrad Dybcio Reviewed-by: Johan Hovold Tested-by: Johan Hovold Signed-off-by: Abel Vesa --- .../boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts | 16 ++++++++++++= ++++ 1 file changed, 16 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts b/a= rch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts index 9c0903b8436396b2fe6e17ee3bc4d454cb5a0f8b..05b2f3bf1fc81c1b10e375b5335= 377c9ce39be95 100644 --- a/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts +++ b/arch/arm64/boot/dts/qcom/x1e78100-lenovo-thinkpad-t14s.dts @@ -923,6 +923,22 @@ &mdss { status =3D "okay"; }; =20 +&mdss_dp0 { + status =3D "okay"; +}; + +&mdss_dp0_out { + data-lanes =3D <0 1>; +}; + +&mdss_dp1 { + status =3D "okay"; +}; + +&mdss_dp1_out { + data-lanes =3D <0 1>; +}; + &mdss_dp3 { compatible =3D "qcom,x1e80100-dp"; /delete-property/ #sound-dai-cells; --=20 2.34.1