From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 0B185136347 for ; Tue, 4 Mar 2025 01:44:25 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052668; cv=none; b=WQ5GrAoSn4n9EXOh2Z7yWkYoJz4n9YSmoBUNsjtXbXtZlDVnhUkiUsAu77xUrmkLBEClXQ0QVGbM+rzYDwQ0PlAKPpgz1773uzKQTfBc5xcmiXbP655SHFb27clHpJCmfoPRJtQAtdTLPI3jAH9F4q3pfur7R/Fw48EQvypk3DI= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052668; c=relaxed/simple; bh=iDVPebVtBVKbo8sc+q34EtLBvJPNOV2/Slk4+XhkzX8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=U+u52eN2D9p5/7eftULdfQP38wJpIpTpFOyf+nYEb0jbs9RqkbPiJUym0XoO0AIk3ljheJXjeW09fsjpvDkEe/CDSAxVW8iBMM7GoMNIwdw2JcXgnkv+pnA4xWGrWHtDGKHjden1NfqwP3jTI8E3Vc255w/Tm4/JesqMgQaSOUY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=Dg2DSGE1; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="Dg2DSGE1" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741052658; bh=iDVPebVtBVKbo8sc+q34EtLBvJPNOV2/Slk4+XhkzX8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=Dg2DSGE1mIWJMt5NqyrYikQxOSRhJbtg2lLdUOIBBbtbioR5Cws1qIsqEuBhUm7kK a46shU/FL112y3h0HqvfS/psfgPryIV1oWpUNqNbo+2pHQZTOhDo1CIbHz6wZSQB/q zaxPgTctZOgsS7VVmKz2pmjYNRP4xMDdBWZ2VA6FNjeojD6NdmOvns2Y34lBQb7UJH s6WK+u9KZvkqEVFIyQt7nLbg8XTk3hyMz7UJJVYtUqzE8LVnKckHIQg5EJ94FhGhQ8 WGzS0qbCF2iDSHpH/IThdERfe4LUJ2wGaB6F/UAPECMzmB5vjPz8FfaA5c7jruCUPM y9+2urszhPIMg== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 2DBB817E0E8D; Tue, 4 Mar 2025 02:44:18 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:00 +0200 Subject: [PATCH v4 01/12] phy: Add HDMI configuration options Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-1-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 From: Sandor Yu Allow HDMI PHYs to be configured through the generic functions through a custom structure added to the generic union. The parameters added here are based on HDMI PHY implementation practices. The current set of parameters should cover the potential users. Signed-off-by: Sandor Yu Reviewed-by: Dmitry Baryshkov Reviewed-by: Maxime Ripard Acked-by: Vinod Koul Link: https://lore.kernel.org/r/d1cff6c03ec3732d2244022029245ab2d954d997.17= 34340233.git.Sandor.yu@nxp.com Signed-off-by: Cristian Ciocaltea --- include/linux/phy/phy-hdmi.h | 19 +++++++++++++++++++ include/linux/phy/phy.h | 7 ++++++- 2 files changed, 25 insertions(+), 1 deletion(-) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h new file mode 100644 index 0000000000000000000000000000000000000000..6a696922bc7f29af63d88646701= b2c0fcee5c885 --- /dev/null +++ b/include/linux/phy/phy-hdmi.h @@ -0,0 +1,19 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2022,2024 NXP + */ + +#ifndef __PHY_HDMI_H_ +#define __PHY_HDMI_H_ + +/** + * struct phy_configure_opts_hdmi - HDMI configuration set + * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * + * This structure is used to represent the configuration state of a HDMI p= hy. + */ +struct phy_configure_opts_hdmi { + unsigned long long tmds_char_rate; +}; + +#endif /* __PHY_HDMI_H_ */ diff --git a/include/linux/phy/phy.h b/include/linux/phy/phy.h index 03cd5bae92d3f189d739c453fe4c160dd2a5063e..4ac486b101fe4023b8f2a84e907= e65a0ff0a5ede 100644 --- a/include/linux/phy/phy.h +++ b/include/linux/phy/phy.h @@ -17,6 +17,7 @@ #include =20 #include +#include #include #include =20 @@ -42,7 +43,8 @@ enum phy_mode { PHY_MODE_MIPI_DPHY, PHY_MODE_SATA, PHY_MODE_LVDS, - PHY_MODE_DP + PHY_MODE_DP, + PHY_MODE_HDMI, }; =20 enum phy_media { @@ -60,11 +62,14 @@ enum phy_media { * the DisplayPort protocol. * @lvds: Configuration set applicable for phys supporting * the LVDS phy mode. + * @hdmi: Configuration set applicable for phys supporting + * the HDMI phy mode. */ union phy_configure_opts { struct phy_configure_opts_mipi_dphy mipi_dphy; struct phy_configure_opts_dp dp; struct phy_configure_opts_lvds lvds; + struct phy_configure_opts_hdmi hdmi; }; =20 /** --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B978A13AA27 for ; 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Tue, 4 Mar 2025 02:44:18 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:01 +0200 Subject: [PATCH v4 02/12] phy: hdmi: Add color depth configuration Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-2-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Extend the HDMI configuration options to allow managing bits per color channel. This is required by some PHY drivers such as rockchip-samsung-hdptx. Signed-off-by: Cristian Ciocaltea --- include/linux/phy/phy-hdmi.h | 2 ++ 1 file changed, 2 insertions(+) diff --git a/include/linux/phy/phy-hdmi.h b/include/linux/phy/phy-hdmi.h index 6a696922bc7f29af63d88646701b2c0fcee5c885..f0ec963c6e84f1b7728acafc824= dff191c6b873d 100644 --- a/include/linux/phy/phy-hdmi.h +++ b/include/linux/phy/phy-hdmi.h @@ -9,11 +9,13 @@ /** * struct phy_configure_opts_hdmi - HDMI configuration set * @tmds_char_rate: HDMI TMDS Character Rate in Hertz. + * @bpc: Bits per color channel. * * This structure is used to represent the configuration state of a HDMI p= hy. */ struct phy_configure_opts_hdmi { unsigned long long tmds_char_rate; + unsigned int bpc; }; =20 #endif /* __PHY_HDMI_H_ */ --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id E481613C8E2 for ; Tue, 4 Mar 2025 01:44:27 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052669; cv=none; b=SW+0NhHgdugXDK3EjYobDTxhaFFzY65tmOvSLGsC4qWz7V/pTCpmhcSBpVh1csSJbqHytmMN6AFA21OKA9ff6gtS1xDcfcfH/y+bALs1s12/vACY0N47uerioG7m0T+EnHoQEMB597zqdow7TMMJ1e6PULWnG0dZ6szafLkrrsQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052669; c=relaxed/simple; bh=JVO6B5huh7eGDo+k3A1fG3SKCxGyB11XeWKMxuuZ+rw=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bEDBCX36OOozwrN/l59yEGdOO+nzANE/aX0t08XFnUmQANAL46ftNk3FY8oDX+o5CDdKb71BOYptVagDPu+OWpprp4ZGLrNo0PWR7HdirbvXZA2jhoE6K0ncOZdpCLQLa8tWWRDaPzwFGquFfqK9KOqi1mA3yuW25BNNwXFeNw4= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=qvKZ515N; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="qvKZ515N" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741052660; bh=JVO6B5huh7eGDo+k3A1fG3SKCxGyB11XeWKMxuuZ+rw=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=qvKZ515NVdudG5/INUpwF68Tb5cdYb37WTMmQAaQs7oDwMfuxnf292TUulUtMR6tB xr1OeuVrmBfAaJyTiIf47CFveoq9ATnHEhjexNaflUkOtpC3/cnEf0fIWJ0/GnWRQK VH6s/axpAiBD412eAjjfVCVxeCa9OED/MXWDm7fLqqvtsxdT6lHI+2BChJYnlhNqb4 Lgz6ygplXtbqCDLXRIoByF7Wa7Lx0z+3YqRbXdFG+fQsfvJqSHZrdEDNHQ8uwhD5Zv USjmJBjdd7CDyL2QtGLA2fsz9W0hZABcQP6/TAk84kjnrU7z3zSOuql7q6buI83nx1 ehopYz/8WkOoQ== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id CEB6B17E0FA7; Tue, 4 Mar 2025 02:44:19 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:02 +0200 Subject: [PATCH v4 03/12] phy: rockchip: samsung-hdptx: Fix clock ratio setup Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-3-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The switch from 1/10 to 1/40 clock ratio must happen when exceeding the 340 MHz rate limit of HDMI 1.4, i.e. when entering the HDMI 2.0 domain, and not before. While at it, introduce a define for this rate limit constant. Fixes: 553be2830c5f ("phy: rockchip: Add Samsung HDMI/eDP Combo PHY driver") Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index f88369864c50e4563834ccbb26f1f9f440e99271..cf2c3a46604cb9d8c26fe5ec834= 6904e0b62848f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -320,6 +320,7 @@ #define LN3_TX_SER_RATE_SEL_HBR2_MASK BIT(3) #define LN3_TX_SER_RATE_SEL_HBR3_MASK BIT(2) =20 +#define HDMI14_MAX_RATE 340000000 #define HDMI20_MAX_RATE 600000000 =20 enum dp_link_rate { @@ -1072,7 +1073,7 @@ static int rk_hdptx_ropll_tmds_mode_config(struct rk_= hdptx_phy *hdptx, =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 - if (rate >=3D 3400000) { + if (rate > HDMI14_MAX_RATE / 100) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 71982147C9B for ; Tue, 4 Mar 2025 01:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052670; cv=none; b=UBNQ8Z3N8uHh/ZQufQdIu73KGexaBso6uRTr5MHLRMFNMY0glM2DYNrm6KcwjeVnP+PDwmX8gaP4CCNULBw8lXJbO91DXEPgVV6ikoSWDjykMLJywUeUM6pAbZ1AgqDcIUSeFl3c4/wVRgBJvcd8jdA/vmI0R7wqLvThGIjx+kw= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052670; c=relaxed/simple; bh=XP3rwzkTa1mXnGdnUHFUWqLPHJxazgMc4cL1Dqwrxk8=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=V+J0nb+ku46yXQ+MZY4s98wsQGFVwyyc19EI79zZ8xwuXpIuwqiR7pZzgDfnZ6HmYLbnYcGGfkhx/OEbrbeZnjFpK5yLGvVpuV1Q1A4kzQyJQMS9RHETSPXL6PtNlcn8ju2H1WerNURHFgrxyhuW725Hh3Y9B/ahlMvRRTklf0w= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=NLY3E68D; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="NLY3E68D" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741052660; bh=XP3rwzkTa1mXnGdnUHFUWqLPHJxazgMc4cL1Dqwrxk8=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=NLY3E68DYDkzVvAkCnu5VDpYvpn0xoEudpCXALBbfaiQT5f/rtb9Zmv3NXOqbxhGc qdFzoXkH76VoYcLBaFtPqDQYM/MnetZFz817LDvf2hwzaqHjXTxHms9vw/OqGH+6Ic T3qMqUrZ5Czeea6MobKuohAB+gvJXJQbklJEwacwomyXO+OhPpgXazTOT6ZIi5pZuz 0ePEsUgElXEisUlqex5CtEqpiHJ97rUcrXXy1FqJSrdLrTNkfis/WIlwqewRaC77Z6 m5T0p0JaKYpbtOrXr9mmCVMfr8MgyQaDCgVKlUFM5NrmFrOXXJ3PRXwKKMR4C3L5vf fW7VxK7rVOkXA== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id B13CF17E0FD1; Tue, 4 Mar 2025 02:44:20 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:03 +0200 Subject: [PATCH v4 04/12] phy: rockchip: samsung-hdptx: Drop unused struct lcpll_config Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-4-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 This is just a leftover from downstream support for HDMI 2.1. Remove the unused struct for now. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 31 -------------------= ---- 1 file changed, 31 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index cf2c3a46604cb9d8c26fe5ec8346904e0b62848f..f9b5c96d6c789e435657e224032= d35b5a6950945 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -329,37 +329,6 @@ enum dp_link_rate { DP_BW_HBR2, }; =20 -struct lcpll_config { - u32 bit_rate; - u8 lcvco_mode_en; - u8 pi_en; - u8 clk_en_100m; - u8 pms_mdiv; - u8 pms_mdiv_afc; - u8 pms_pdiv; - u8 pms_refdiv; - u8 pms_sdiv; - u8 pi_cdiv_rstn; - u8 pi_cdiv_sel; - u8 sdm_en; - u8 sdm_rstn; - u8 sdc_frac_en; - u8 sdc_rstn; - u8 sdm_deno; - u8 sdm_num_sign; - u8 sdm_num; - u8 sdc_n; - u8 sdc_n2; - u8 sdc_num; - u8 sdc_deno; - u8 sdc_ndiv_rstn; - u8 ssc_en; - u8 ssc_fm_dev; - u8 ssc_fm_freq; - u8 ssc_clk_div_sel; - u8 cd_tx_ser_rate_sel; -}; - struct ropll_config { u32 bit_rate; u8 pms_mdiv; --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5939E143759 for ; Tue, 4 Mar 2025 01:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052670; cv=none; b=O4wai+0N+qi3FJQNVqWRW9g/56kZdXCldrCDd3L4DIKyzqEUeXUcmFWMf5nyNZDpwiqwRUc7C9ozuM5LiMnMcHX0G0Spi7g+kcxf/sddrH4oQ4T+6ksiOlQbu56TnAMN2GWFxQgnMART1s01DYEvCt0V/wZ/GETEqxHkC7YdYpQ= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052670; c=relaxed/simple; bh=H52on9OF9VHErJX/F0Xzfni4+/Tw4ZDeMorcaCchiac=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=bLj8SzG2XRTtinyzATgPULap/O3Vn1nwCPkFna10um8FWhJAI/D7sqzkBxCL8wwAEvyv3sOaka9Hv0gn0ONzFY1pgjx3yetlRUWlkgYPIdlcIKRr/FrhRGNNIFGUh9ax527Et8ErLY/ffEafC9tOGYfNJ29PThBXw4cPFTJT+/Y= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=QYmfu+AW; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="QYmfu+AW" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741052661; bh=H52on9OF9VHErJX/F0Xzfni4+/Tw4ZDeMorcaCchiac=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=QYmfu+AWVA0I9gARdMIhIblPwsKGPekxWE6sUE2o+lgcdl2KQogWTJ1tvMLNaeQ7X DHl6a2mwQvMTZYbUNkzHOhGlLaleNp1IZqn5XW8HFOufkMDa0JcH3LaXh42Z2rYX/D TfAndEAQ1hDyM4WSNJcSOK0M+qoIH7Bnky5dgRouAm3fl3ufaztanDXwKro1Yoo8ps 4QzDqkICQsCzaB57g5m1TP4HBC9iYJkbcxmTF5xWteYZYaRfPFQ1RnnDZBH/qcpqeD gwqq9pBlBgxteMnpQCJTaZc+7XYwuStUdimhOka6R7RfCWYBBu+ReqUjrroKdbDt6T SOedM8N5yrYcQ== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 9552E17E1010; Tue, 4 Mar 2025 02:44:21 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:04 +0200 Subject: [PATCH v4 05/12] phy: rockchip: samsung-hdptx: Drop unused phy_cfg driver data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-5-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 There is no usage of phy_cfg in the upstream driver data, nor in the downstream one, hence remove it. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 1 - 1 file changed, 1 deletion(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index f9b5c96d6c789e435657e224032d35b5a6950945..06644c3d98d3f8b697fc704704d= f5acdd3c85bad 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -397,7 +397,6 @@ struct rk_hdptx_phy { int phy_id; =20 struct phy *phy; - struct phy_config *phy_cfg; struct clk_bulk_data *clks; int nr_clks; struct reset_control_bulk_data rsts[RST_MAX]; --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 93DAC14900B for ; Tue, 4 Mar 2025 01:44:28 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052670; cv=none; b=Ayp7IHPKILiNT9+IxizjYPsh4Tx3dE9m91IOGjZo55c5ryHF2VHpHc3i8yyiE06ttsOsaD68nGGw+1G1ymNGUk3S5saD4L9pMSNB842lhPYR8In97vxaDeWnjBA4bE2SoOedodx8dCUKT1rHvEGnY7IO7wjUIUSN4knGu55piCs= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052670; c=relaxed/simple; bh=MrgqgIZ157jsElaeg3dFAoESeyFXV9vNfZmK9cHxL2A=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=RnRgvwwcPu9cUAOmVj0lTh7j8L8L8Ni7upIlv2zZs6WZp0ZmG29HzmNm1qefnd/4IfPD8Kd0ifjwNIJWLgITp8L1263BOwWDaeZjo6YNSrc1P4HmDz6J2arJ54XJT8cyNuIHgsNPXD1yFJXRYYpGsYgkaP2ytd+HO+AbanZc2fk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=gr18z2ak; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="gr18z2ak" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1741052662; bh=MrgqgIZ157jsElaeg3dFAoESeyFXV9vNfZmK9cHxL2A=; h=From:Date:Subject:References:In-Reply-To:To:Cc:From; b=gr18z2akC5QqEA8/nx/lgtd8EIXDSnfG18I2aWVHmKMAu2lyj1uFiqgYS/QDGlg0q BrIvwe6XjarK2xyHiAyEA6tDcnlEDkofwmrWASsLqDGPORaZYGxHh7fn6u201rhBdT fgBQYRPXDZDf7L49jvhX64PA2SfkhZKVl0plq7iW4VNs4Km7Zh/mwUOJ0IN4MmebOF rBw99m649HdFxnCwqrMRjzC76ugXu563LUwTz57oD3jMH1+gxSHp3ye7t8WvE+5RBv PxCLAk8BxtjCiZyxVIxW8taIz4RlLs3YrLJ4jFsIeJTs4BaUO8gMEQq6Cv4c8gYKCm 6hUxT98KMsKdw== Received: from localhost (unknown [188.27.58.83]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: cristicc) by bali.collaboradmins.com (Postfix) with UTF8SMTPSA id 8F23717E1016; Tue, 4 Mar 2025 02:44:22 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:05 +0200 Subject: [PATCH v4 06/12] phy: rockchip: samsung-hdptx: Drop superfluous cfgs driver data Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-6-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The ->cfgs member has been introduced via commit f08d1c085638 ("phy: phy-rockchip-samsung-hdptx: Don't use dt aliases to determine phy-id"), but it is only used during probe() in order to setup ->phy_id. Use a probe() local variable to store device match data and remove the now unnecessary member from struct rk_hdptx_phy. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 12 +++++------- 1 file changed, 5 insertions(+), 7 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 06644c3d98d3f8b697fc704704df5acdd3c85bad..2bf525514c1991a1299265d12e1= e85f66333c604 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -392,10 +392,7 @@ struct rk_hdptx_phy { struct regmap *regmap; struct regmap *grf; =20 - /* PHY const config */ - const struct rk_hdptx_phy_cfg *cfgs; int phy_id; - struct phy *phy; struct clk_bulk_data *clks; int nr_clks; @@ -1892,6 +1889,7 @@ static int rk_hdptx_phy_runtime_resume(struct device = *dev) =20 static int rk_hdptx_phy_probe(struct platform_device *pdev) { + const struct rk_hdptx_phy_cfg *cfgs; struct phy_provider *phy_provider; struct device *dev =3D &pdev->dev; struct rk_hdptx_phy *hdptx; @@ -1910,14 +1908,14 @@ static int rk_hdptx_phy_probe(struct platform_devic= e *pdev) return dev_err_probe(dev, PTR_ERR(regs), "Failed to ioremap resource\n"); =20 - hdptx->cfgs =3D device_get_match_data(dev); - if (!hdptx->cfgs) + cfgs =3D device_get_match_data(dev); + if (!cfgs) return dev_err_probe(dev, -EINVAL, "missing match data\n"); =20 /* find the phy-id from the io address */ hdptx->phy_id =3D -ENODEV; - for (id =3D 0; id < hdptx->cfgs->num_phys; id++) { - if (res->start =3D=3D hdptx->cfgs->phy_ids[id]) { + for (id =3D 0; id < cfgs->num_phys; id++) { + if (res->start =3D=3D cfgs->phy_ids[id]) { hdptx->phy_id =3D id; break; } --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A400E156C76 for ; Tue, 4 Mar 2025 01:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052671; cv=none; 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Tue, 4 Mar 2025 02:44:23 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:06 +0200 Subject: [PATCH v4 07/12] phy: rockchip: samsung-hdptx: Setup TMDS char rate via phy_configure_opts_hdmi Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-7-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The current workaround to setup the TMDS character rate relies on the unconventional usage of phy_set_bus_width(). Make use of the recently introduced HDMI PHY configuration API to properly handle the setup. The workaround will be dropped as soon as the switch has been completed on both ends. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 54 ++++++++++++++++---= ---- 1 file changed, 38 insertions(+), 16 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 2bf525514c1991a1299265d12e1e85f66333c604..7e1d1c10758249aa5bbddbdaae0= 108bba04f30df 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -394,6 +394,7 @@ struct rk_hdptx_phy { =20 int phy_id; struct phy *phy; + struct phy_configure_opts_hdmi hdmi_cfg; struct clk_bulk_data *clks; int nr_clks; struct reset_control_bulk_data rsts[RST_MAX]; @@ -1409,19 +1410,25 @@ static int rk_hdptx_dp_aux_init(struct rk_hdptx_phy= *hdptx) static int rk_hdptx_phy_power_on(struct phy *phy) { struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); - int bus_width =3D phy_get_bus_width(hdptx->phy); enum phy_mode mode =3D phy_get_mode(phy); + unsigned int rate =3D 0; int ret, lane; =20 - /* - * FIXME: Temporary workaround to pass pixel_clk_rate - * from the HDMI bridge driver until phy_configure_opts_hdmi - * becomes available in the PHY API. - */ - unsigned int rate =3D bus_width & 0xfffffff; - - dev_dbg(hdptx->dev, "%s bus_width=3D%x rate=3D%u\n", - __func__, bus_width, rate); + if (mode !=3D PHY_MODE_DP) { + if (!hdptx->hdmi_cfg.tmds_char_rate) { + /* + * FIXME: Temporary workaround to setup TMDS char rate + * from the RK DW HDMI QP bridge driver. + * Will be removed as soon the switch to the HDMI PHY + * configuration API has been completed on both ends. + */ + rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; + hdptx->hdmi_cfg.tmds_char_rate =3D rate * 100; + } else { + rate =3D hdptx->hdmi_cfg.tmds_char_rate / 100; + } + dev_dbg(hdptx->dev, "%s rate=3D%u\n", __func__, rate); + } =20 ret =3D rk_hdptx_phy_consumer_get(hdptx, rate); if (ret) @@ -1469,8 +1476,17 @@ static int rk_hdptx_phy_power_off(struct phy *phy) return rk_hdptx_phy_consumer_put(hdptx, false); } =20 -static int rk_hdptx_phy_verify_config(struct rk_hdptx_phy *hdptx, - struct phy_configure_opts_dp *dp) +static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, + struct phy_configure_opts_hdmi *hdmi) +{ + if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) + return -EINVAL; + + return 0; +} + +static int rk_hdptx_phy_verify_dp_config(struct rk_hdptx_phy *hdptx, + struct phy_configure_opts_dp *dp) { int i; =20 @@ -1730,12 +1746,18 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt enum phy_mode mode =3D phy_get_mode(phy); int ret; =20 - if (mode !=3D PHY_MODE_DP) - return 0; + if (mode !=3D PHY_MODE_DP) { + ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); + if (ret) + dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); + else + hdptx->hdmi_cfg =3D opts->hdmi; + return ret; + } =20 - ret =3D rk_hdptx_phy_verify_config(hdptx, &opts->dp); + ret =3D rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); if (ret) { - dev_err(hdptx->dev, "invalid params for phy configure\n"); + dev_err(hdptx->dev, "invalid dp params for phy configure\n"); return ret; } =20 --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A3FC714A4CC for ; Tue, 4 Mar 2025 01:44:29 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052671; cv=none; b=EYdk+J6ds2DIM7NrmKEWi6SrdU7jBlqr5Hv2W7C8rAhIG0ytH6au6CZKMuYaSVBhNwRuTQD7XluH4KbhdejY0JeVZ9M3JhmLzO86drw+x2gXnqnzW1+njpQRnllzl18HuVLj0fRSgnoZpE9c6Vo2k8P+viyEutyXZc8lNZHlmQg= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052671; c=relaxed/simple; bh=sVknEgGNvct3p8aN+CRi6/k6aF+awKULL5O/9DK0SkA=; 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charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-8-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Implement the phy_ops.validate() callback to allow checking the PHY configuration parameters without actually applying them. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 23 +++++++++++++++++++= ++++ 1 file changed, 23 insertions(+) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 7e1d1c10758249aa5bbddbdaae0108bba04f30df..47db1395051f5d900197871694b= ab90ca4d6e38e 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1482,6 +1482,17 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) return -EINVAL; =20 + u32 bit_rate =3D hdmi->tmds_char_rate / 100; + int i; + + for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) + if (bit_rate =3D=3D ropll_tmds_cfg[i].bit_rate) + break; + + if (i =3D=3D ARRAY_SIZE(ropll_tmds_cfg) && + !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) + return -EINVAL; + return 0; } =20 @@ -1789,10 +1800,22 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt return 0; } =20 +static int rk_hdptx_phy_validate(struct phy *phy, enum phy_mode mode, + int submode, union phy_configure_opts *opts) +{ + struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); + + if (mode !=3D PHY_MODE_DP) + return rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); + + return rk_hdptx_phy_verify_dp_config(hdptx, &opts->dp); +} + static const struct phy_ops rk_hdptx_phy_ops =3D { .power_on =3D rk_hdptx_phy_power_on, .power_off =3D rk_hdptx_phy_power_off, .configure =3D rk_hdptx_phy_configure, + .validate =3D rk_hdptx_phy_validate, .owner =3D THIS_MODULE, }; =20 --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 07DF015CD46 for ; Tue, 4 Mar 2025 01:44:30 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; 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Tue, 4 Mar 2025 02:44:25 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:08 +0200 Subject: [PATCH v4 09/12] phy: rockchip: samsung-hdptx: Restrict altering TMDS char rate via CCF Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-9-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Although, in theory, the clock provider functionality could be enabled as a standalone driver feature, in practice it is unlikely that it would be ever needed separately from the common PHY related features, i.e. making use of the PHY PLL as an alternative and more accurate clock source for display modes handling. Which means the PLL will be always programmed according to the TMDS char rate set via the HDMI PHY configuration API. Currently it's possible to freely adjust the rate via the clock API as well, that is through clk_set_rate(). Making the clock read-only is not feasible since we need to ensure any rate update done via the PHY configuration API has been actually programmed into the hardware before CCF accesses it. This would be normally done during phy_ops.power_on() or clk_ops.prepare() callbacks, but it might happen that the former gets fired too late and the latter only once, hence we need to keep handle it via clk_ops.set_rate() as a fallback approach. Prevent changing the TMDS character rate via CCF by letting rk_hdptx_phy_clk_round_rate() always return the value set via phy_configure(). To avoid breaking existing users, i.e. RK DW HDMI QP bridge driver, until the switch to the HDMI PHY config based approach is completed, introduce a temporary exception to the rule, toggled via the new ->restrict_rate_change flag, which indicates whether phy_configure() has been called or not. Additionally, revert any unlikely rate change that might have occurred between the calls to ->round_rate() and ->set_rate(). Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 53 +++++++++++++++++--= ---- 1 file changed, 40 insertions(+), 13 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 47db1395051f5d900197871694bab90ca4d6e38e..b4d2f04842b5c5b425c5b73a8b2= 7fabecbbbd6bb 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -402,6 +402,7 @@ struct rk_hdptx_phy { /* clk provider */ struct clk_hw hw; unsigned long rate; + bool restrict_rate_change; =20 atomic_t usage_count; =20 @@ -1759,10 +1760,12 @@ static int rk_hdptx_phy_configure(struct phy *phy, = union phy_configure_opts *opt =20 if (mode !=3D PHY_MODE_DP) { ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &opts->hdmi); - if (ret) + if (ret) { dev_err(hdptx->dev, "invalid hdmi params for phy configure\n"); - else + } else { hdptx->hdmi_cfg =3D opts->hdmi; + hdptx->restrict_rate_change =3D true; + } return ret; } =20 @@ -1849,21 +1852,31 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(s= truct clk_hw *hw, static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, unsigned long *parent_rate) { - u32 bit_rate =3D rate / 100; - int i; + struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 - if (rate > HDMI20_MAX_RATE) - return rate; + /* + * FIXME: Temporarily allow altering TMDS char rate via CCF. + * To be dropped as soon as the RK DW HDMI QP bridge driver + * switches to make use of phy_configure(). + */ + if (!hdptx->restrict_rate_change && rate !=3D hdptx->hdmi_cfg.tmds_char_r= ate) { + struct phy_configure_opts_hdmi hdmi =3D { + .tmds_char_rate =3D rate, + }; + int ret =3D rk_hdptx_phy_verify_hdmi_config(hdptx, &hdmi); =20 - for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (bit_rate =3D=3D ropll_tmds_cfg[i].bit_rate) - break; + if (ret) + return ret; =20 - if (i =3D=3D ARRAY_SIZE(ropll_tmds_cfg) && - !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) - return -EINVAL; + hdptx->hdmi_cfg =3D hdmi; + } =20 - return rate; + /* + * The TMDS char rate shall be adjusted via phy_configure() only, + * hence ensure rk_hdptx_phy_clk_set_rate() won't be invoked with + * a different rate argument. + */ + return hdptx->hdmi_cfg.tmds_char_rate; } =20 static int rk_hdptx_phy_clk_set_rate(struct clk_hw *hw, unsigned long rate, @@ -1871,6 +1884,20 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *= hw, unsigned long rate, { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 + /* Revert any unlikely TMDS char rate change since round_rate() */ + if (hdptx->hdmi_cfg.tmds_char_rate !=3D rate) { + dev_warn(hdptx->dev, "Reverting unexpected rate change from %lu to %llu\= n", + rate, hdptx->hdmi_cfg.tmds_char_rate); + hdptx->hdmi_cfg.tmds_char_rate =3D rate; + } + + /* + * The TMDS char rate would be normally programmed in HW during + * phy_ops.power_on() or clk_ops.prepare() callbacks, but it might + * happen that the former gets fired too late, i.e. after this call, + * while the latter being executed only once, i.e. when clock remains + * in the prepared state during rate changes. + */ return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); 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Tue, 4 Mar 2025 02:44:25 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:09 +0200 Subject: [PATCH v4 10/12] phy: rockchip: samsung-hdptx: Add high color depth management Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-10-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Add support for 8-bit, 10-bit, 12-bit and 16-bit color depth setup. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 29 +++++++++++++++++++= ---- 1 file changed, 25 insertions(+), 4 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index b4d2f04842b5c5b425c5b73a8b27fabecbbbd6bb..c2ad1cb94614711bea13b7259a6= b66dbd72d663d 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -1027,6 +1027,9 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_h= dptx_phy *hdptx, regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_POSTDIV_SEL_MASK, FIELD_PREP(PLL_PCG_POSTDIV_SEL_MASK, cfg->pms_sdiv)); =20 + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_SEL_MASK, + FIELD_PREP(PLL_PCG_CLK_SEL_MASK, (hdptx->hdmi_cfg.bpc - 8) >> 1)); + regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); =20 @@ -1428,7 +1431,8 @@ static int rk_hdptx_phy_power_on(struct phy *phy) } else { rate =3D hdptx->hdmi_cfg.tmds_char_rate / 100; } - dev_dbg(hdptx->dev, "%s rate=3D%u\n", __func__, rate); + dev_dbg(hdptx->dev, "%s rate=3D%u bpc=3D%u\n", + __func__, rate, hdptx->hdmi_cfg.bpc); } =20 ret =3D rk_hdptx_phy_consumer_get(hdptx, rate); @@ -1480,12 +1484,12 @@ static int rk_hdptx_phy_power_off(struct phy *phy) static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, struct phy_configure_opts_hdmi *hdmi) { - if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) - return -EINVAL; - u32 bit_rate =3D hdmi->tmds_char_rate / 100; int i; =20 + if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) + return -EINVAL; + for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) if (bit_rate =3D=3D ropll_tmds_cfg[i].bit_rate) break; @@ -1494,6 +1498,19 @@ static int rk_hdptx_phy_verify_hdmi_config(struct rk= _hdptx_phy *hdptx, !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) return -EINVAL; =20 + if (!hdmi->bpc) + hdmi->bpc =3D 8; + + switch (hdmi->bpc) { + case 8: + case 10: + case 12: + case 16: + break; + default: + return -EINVAL; + }; + return 0; } =20 @@ -1766,6 +1783,9 @@ static int rk_hdptx_phy_configure(struct phy *phy, un= ion phy_configure_opts *opt hdptx->hdmi_cfg =3D opts->hdmi; hdptx->restrict_rate_change =3D true; } + + dev_dbg(hdptx->dev, "%s tmds_rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); return ret; } =20 @@ -1974,6 +1994,7 @@ static int rk_hdptx_phy_probe(struct platform_device = *pdev) return -ENOMEM; =20 hdptx->dev =3D dev; + hdptx->hdmi_cfg.bpc =3D 8; =20 regs =3D devm_platform_get_and_ioremap_resource(pdev, 0, &res); if (IS_ERR(regs)) --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CA821ACED1 for ; Tue, 4 Mar 2025 01:44:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; 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Tue, 4 Mar 2025 02:44:26 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:10 +0200 Subject: [PATCH v4 11/12] phy: rockchip: samsung-hdptx: Optimize internal rate handling Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-11-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 Drop the rate parameter from a bunch of internal helpers and, instead, make better use of the newly introduced ->hdmi_cfg.tmds_char_rate driver data. Additionally, rename the rather ambiguous ->rate member of struct rk_hdptx_phy to ->hw_rate and ensure rk_hdptx_ropll_tmds_cmn_config() updates it only after all the other operations have been successful. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 59 +++++++++++--------= ---- 1 file changed, 29 insertions(+), 30 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index c2ad1cb94614711bea13b7259a6b66dbd72d663d..54210eaec0c0923b3e8eb8e2076= 32983982bcd2f 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -401,9 +401,8 @@ struct rk_hdptx_phy { =20 /* clk provider */ struct clk_hw hw; - unsigned long rate; + unsigned long hw_rate; bool restrict_rate_change; - atomic_t usage_count; =20 /* used for dp mode */ @@ -968,14 +967,15 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int da= ta_rate, return true; } =20 -static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) +static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx) { + unsigned int rate =3D hdptx->hdmi_cfg.tmds_char_rate / 100; const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; - int i; + int ret, i; =20 - hdptx->rate =3D rate * 100; + if (!rate) + return 0; =20 for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) if (rate =3D=3D ropll_tmds_cfg[i].bit_rate) { @@ -987,7 +987,8 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdp= tx_phy *hdptx, if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) { cfg =3D &rc; } else { - dev_err(hdptx->dev, "%s cannot find pll cfg\n", __func__); + dev_err(hdptx->dev, "%s cannot find pll cfg for rate=3D%u\n", + __func__, rate); return -EINVAL; } } @@ -1033,17 +1034,20 @@ static int rk_hdptx_ropll_tmds_cmn_config(struct rk= _hdptx_phy *hdptx, regmap_update_bits(hdptx->regmap, CMN_REG(0086), PLL_PCG_CLK_EN_MASK, FIELD_PREP(PLL_PCG_CLK_EN_MASK, 0x1)); =20 - return rk_hdptx_post_enable_pll(hdptx); + ret =3D rk_hdptx_post_enable_pll(hdptx); + if (!ret) + hdptx->hw_rate =3D hdptx->hdmi_cfg.tmds_char_rate; + + return ret; } =20 -static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx, - unsigned int rate) +static int rk_hdptx_ropll_tmds_mode_config(struct rk_hdptx_phy *hdptx) { rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_common_sb_init_seq); =20 regmap_write(hdptx->regmap, LNTOP_REG(0200), 0x06); =20 - if (rate > HDMI14_MAX_RATE / 100) { + if (hdptx->hdmi_cfg.tmds_char_rate > HDMI14_MAX_RATE) { /* For 1/40 bitrate clk */ rk_hdptx_multi_reg_write(hdptx, rk_hdtpx_tmds_lntop_highbr_seq); } else { @@ -1095,8 +1099,7 @@ static void rk_hdptx_dp_reset(struct rk_hdptx_phy *hd= ptx) HDPTX_I_BGR_EN << 16 | FIELD_PREP(HDPTX_I_BGR_EN, 0x0)); } =20 -static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx, - unsigned int rate) +static int rk_hdptx_phy_consumer_get(struct rk_hdptx_phy *hdptx) { enum phy_mode mode =3D phy_get_mode(hdptx->phy); u32 status; @@ -1115,11 +1118,9 @@ static int rk_hdptx_phy_consumer_get(struct rk_hdptx= _phy *hdptx, if (mode =3D=3D PHY_MODE_DP) { rk_hdptx_dp_reset(hdptx); } else { - if (rate) { - ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx, rate); - if (ret) - goto dec_usage; - } + ret =3D rk_hdptx_ropll_tmds_cmn_config(hdptx); + if (ret) + goto dec_usage; } =20 return 0; @@ -1415,7 +1416,6 @@ static int rk_hdptx_phy_power_on(struct phy *phy) { struct rk_hdptx_phy *hdptx =3D phy_get_drvdata(phy); enum phy_mode mode =3D phy_get_mode(phy); - unsigned int rate =3D 0; int ret, lane; =20 if (mode !=3D PHY_MODE_DP) { @@ -1426,16 +1426,15 @@ static int rk_hdptx_phy_power_on(struct phy *phy) * Will be removed as soon the switch to the HDMI PHY * configuration API has been completed on both ends. */ - rate =3D phy_get_bus_width(hdptx->phy) & 0xfffffff; - hdptx->hdmi_cfg.tmds_char_rate =3D rate * 100; - } else { - rate =3D hdptx->hdmi_cfg.tmds_char_rate / 100; + hdptx->hdmi_cfg.tmds_char_rate =3D phy_get_bus_width(hdptx->phy) & 0xff= fffff; + hdptx->hdmi_cfg.tmds_char_rate *=3D 100; } - dev_dbg(hdptx->dev, "%s rate=3D%u bpc=3D%u\n", - __func__, rate, hdptx->hdmi_cfg.bpc); + + dev_dbg(hdptx->dev, "%s tmds_rate=3D%llu bpc=3D%u\n", __func__, + hdptx->hdmi_cfg.tmds_char_rate, hdptx->hdmi_cfg.bpc); } =20 - ret =3D rk_hdptx_phy_consumer_get(hdptx, rate); + ret =3D rk_hdptx_phy_consumer_get(hdptx); if (ret) return ret; =20 @@ -1466,7 +1465,7 @@ static int rk_hdptx_phy_power_on(struct phy *phy) regmap_write(hdptx->grf, GRF_HDPTX_CON0, HDPTX_MODE_SEL << 16 | FIELD_PREP(HDPTX_MODE_SEL, 0x0)); =20 - ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx, rate); + ret =3D rk_hdptx_ropll_tmds_mode_config(hdptx); if (ret) rk_hdptx_phy_consumer_put(hdptx, true); } @@ -1851,7 +1850,7 @@ static int rk_hdptx_phy_clk_prepare(struct clk_hw *hw) { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 - return rk_hdptx_phy_consumer_get(hdptx, hdptx->rate / 100); + return rk_hdptx_phy_consumer_get(hdptx); } =20 static void rk_hdptx_phy_clk_unprepare(struct clk_hw *hw) @@ -1866,7 +1865,7 @@ static unsigned long rk_hdptx_phy_clk_recalc_rate(str= uct clk_hw *hw, { struct rk_hdptx_phy *hdptx =3D to_rk_hdptx_phy(hw); =20 - return hdptx->rate; + return hdptx->hw_rate; } =20 static long rk_hdptx_phy_clk_round_rate(struct clk_hw *hw, unsigned long r= ate, @@ -1918,7 +1917,7 @@ static int rk_hdptx_phy_clk_set_rate(struct clk_hw *h= w, unsigned long rate, * while the latter being executed only once, i.e. when clock remains * in the prepared state during rate changes. */ - return rk_hdptx_ropll_tmds_cmn_config(hdptx, rate / 100); + return rk_hdptx_ropll_tmds_cmn_config(hdptx); } =20 static const struct clk_ops hdptx_phy_clk_ops =3D { --=20 2.48.1 From nobody Sun Feb 8 21:12:14 2026 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6CB0D1ACEDC for ; Tue, 4 Mar 2025 01:44:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052674; cv=none; b=NrqqYBU9rnrus0+EkW84TZ4n9L0N3+kuURcfIy72vYTdOWbjVhYXM/UL9Of1xoY6A+V76R6qW8gxVxcT+SLI7Zzcxkyvtq1OrYefHDnGW0inPAxl1RWPUgju8Jhq6wqScCCd4Ili8yheqiZ1gMYBviAb4qi4qnNTAoAHbCdAebo= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741052674; c=relaxed/simple; bh=DUfex9XJcgf138j9NIpzgjYvH+XwkmmguCNRyICKDXs=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; 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Tue, 4 Mar 2025 02:44:27 +0100 (CET) From: Cristian Ciocaltea Date: Tue, 04 Mar 2025 03:44:11 +0200 Subject: [PATCH v4 12/12] phy: rockchip: samsung-hdptx: Avoid Hz-hHz unit conversion overhead Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250304-phy-sam-hdptx-bpc-v4-12-8657847c13f7@collabora.com> References: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> In-Reply-To: <20250304-phy-sam-hdptx-bpc-v4-0-8657847c13f7@collabora.com> To: Vinod Koul , Kishon Vijay Abraham I , Heiko Stuebner Cc: Algea Cao , Sandor Yu , Dmitry Baryshkov , Maxime Ripard , kernel@collabora.com, linux-kernel@vger.kernel.org, linux-phy@lists.infradead.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org X-Mailer: b4 0.14.2 The ropll_tmds_cfg table used to identify the configuration params for the supported rates expects the search keys - bit_rate field - to be provided in hHz rather than Hz (1 hHz =3D 100 Hz). This requires multiple conversions between these units being performed at runtime. Improve implementation clarity and efficiency by consistently using the Hz unit throughout driver's internal data structures and functions. Signed-off-by: Cristian Ciocaltea --- drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c | 68 +++++++++++--------= ---- 1 file changed, 33 insertions(+), 35 deletions(-) diff --git a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c b/drivers/ph= y/rockchip/phy-rockchip-samsung-hdptx.c index 54210eaec0c0923b3e8eb8e207632983982bcd2f..8a835f8a5dc82a6d7ce5bdf79ed= 2773b9a7fa7c5 100644 --- a/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c +++ b/drivers/phy/rockchip/phy-rockchip-samsung-hdptx.c @@ -330,7 +330,7 @@ enum dp_link_rate { }; =20 struct ropll_config { - u32 bit_rate; + u32 rate; u8 pms_mdiv; u8 pms_mdiv_afc; u8 pms_pdiv; @@ -411,45 +411,45 @@ struct rk_hdptx_phy { }; =20 static const struct ropll_config ropll_tmds_cfg[] =3D { - { 5940000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 594000000, 124, 124, 1, 1, 0, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 3712500, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 371250000, 155, 155, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 2970000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 297000000, 124, 124, 1, 1, 1, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1620000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, + { 162000000, 135, 135, 1, 1, 3, 1, 1, 0, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1856250, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 185625000, 155, 155, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1540000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, + { 154000000, 193, 193, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 193, 1, 32, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1485000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, + { 148500000, 0x7b, 0x7b, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 4, 0, 3, 5, 5, 0x10, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1462500, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, + { 146250000, 122, 122, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 244, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1190000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, + { 119000000, 149, 149, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 149, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1065000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, + { 106500000, 89, 89, 1, 1, 3, 1, 1, 1, 1, 1, 1, 1, 89, 1, 16, 1, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 1080000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 108000000, 135, 135, 1, 1, 5, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 855000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, + { 85500000, 214, 214, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 214, 1, 16, 2, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 835000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, + { 83500000, 105, 105, 1, 1, 5, 1, 1, 1, 1, 1, 1, 1, 42, 1, 16, 1, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 928125, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 92812500, 155, 155, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 742500, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, + { 74250000, 124, 124, 1, 1, 7, 1, 1, 1, 1, 1, 1, 1, 62, 1, 16, 5, 0, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 650000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, + { 65000000, 162, 162, 1, 1, 11, 1, 1, 1, 1, 1, 1, 1, 54, 0, 16, 4, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 337500, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, + { 33750000, 0x70, 0x70, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 0x2, 0, 0x01, 5, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 400000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 40000000, 100, 100, 1, 1, 11, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 270000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, + { 27000000, 0x5a, 0x5a, 1, 1, 0xf, 1, 1, 0, 1, 0, 1, 1, 0x9, 0, 0x05, 0, 0x14, 0x18, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, - { 251750, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, + { 25175000, 84, 84, 1, 1, 0xf, 1, 1, 1, 1, 1, 1, 1, 168, 1, 16, 4, 1, 1, 1, 0, 0x20, 0x0c, 1, 0x0e, 0, 0, }, }; =20 @@ -895,10 +895,10 @@ static void rk_hdptx_phy_disable(struct rk_hdptx_phy = *hdptx) regmap_write(hdptx->grf, GRF_HDPTX_CON0, val); } =20 -static bool rk_hdptx_phy_clk_pll_calc(unsigned int data_rate, +static bool rk_hdptx_phy_clk_pll_calc(unsigned long rate, struct ropll_config *cfg) { - const unsigned int fout =3D data_rate / 2, fref =3D 24000; + const unsigned int fout =3D rate / 200, fref =3D 24000; unsigned long k =3D 0, lc, k_sub, lc_sub; unsigned int fvco, sdc; u32 mdiv, sdiv, n =3D 8; @@ -969,33 +969,32 @@ static bool rk_hdptx_phy_clk_pll_calc(unsigned int da= ta_rate, =20 static int rk_hdptx_ropll_tmds_cmn_config(struct rk_hdptx_phy *hdptx) { - unsigned int rate =3D hdptx->hdmi_cfg.tmds_char_rate / 100; const struct ropll_config *cfg =3D NULL; struct ropll_config rc =3D {0}; int ret, i; =20 - if (!rate) + if (!hdptx->hdmi_cfg.tmds_char_rate) return 0; =20 for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (rate =3D=3D ropll_tmds_cfg[i].bit_rate) { + if (hdptx->hdmi_cfg.tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) { cfg =3D &ropll_tmds_cfg[i]; break; } =20 if (!cfg) { - if (rk_hdptx_phy_clk_pll_calc(rate, &rc)) { + if (rk_hdptx_phy_clk_pll_calc(hdptx->hdmi_cfg.tmds_char_rate, &rc)) { cfg =3D &rc; } else { - dev_err(hdptx->dev, "%s cannot find pll cfg for rate=3D%u\n", - __func__, rate); + dev_err(hdptx->dev, "%s cannot find pll cfg for rate=3D%llu\n", + __func__, hdptx->hdmi_cfg.tmds_char_rate); return -EINVAL; } } =20 - dev_dbg(hdptx->dev, "mdiv=3D%u, sdiv=3D%u, sdm_en=3D%u, k_sign=3D%u, k=3D= %u, lc=3D%u\n", - cfg->pms_mdiv, cfg->pms_sdiv + 1, cfg->sdm_en, - cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); + dev_dbg(hdptx->dev, "%s rate=3D%llu mdiv=3D%u sdiv=3D%u sdm_en=3D%u k_sig= n=3D%u k=3D%u lc=3D%u\n", + __func__, hdptx->hdmi_cfg.tmds_char_rate, cfg->pms_mdiv, cfg->pms_sdiv += 1, + cfg->sdm_en, cfg->sdm_num_sign, cfg->sdm_num, cfg->sdm_deno); =20 rk_hdptx_pre_power_up(hdptx); =20 @@ -1483,18 +1482,17 @@ static int rk_hdptx_phy_power_off(struct phy *phy) static int rk_hdptx_phy_verify_hdmi_config(struct rk_hdptx_phy *hdptx, struct phy_configure_opts_hdmi *hdmi) { - u32 bit_rate =3D hdmi->tmds_char_rate / 100; int i; =20 if (!hdmi->tmds_char_rate || hdmi->tmds_char_rate > HDMI20_MAX_RATE) return -EINVAL; =20 for (i =3D 0; i < ARRAY_SIZE(ropll_tmds_cfg); i++) - if (bit_rate =3D=3D ropll_tmds_cfg[i].bit_rate) + if (hdmi->tmds_char_rate =3D=3D ropll_tmds_cfg[i].rate) break; =20 if (i =3D=3D ARRAY_SIZE(ropll_tmds_cfg) && - !rk_hdptx_phy_clk_pll_calc(bit_rate, NULL)) + !rk_hdptx_phy_clk_pll_calc(hdmi->tmds_char_rate, NULL)) return -EINVAL; =20 if (!hdmi->bpc) --=20 2.48.1