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Mon, 3 Mar 2025 15:25:21 +0000 (GMT) X-AuditID: cbfec7f4-c39fa70000004fb9-b6-67c5c9e15fb0 Received: from eusmtip1.samsung.com ( [203.254.199.221]) by eusmgms2.samsung.com (EUCPMTA) with SMTP id 7D.E0.19654.1E9C5C76; Mon, 3 Mar 2025 15:25:21 +0000 (GMT) Received: from AMDC4942.home (unknown [106.210.136.40]) by eusmtip1.samsung.com (KnoxPortal) with ESMTPA id 20250303152521eusmtip1bab26c8c74d66ee7cf334e80346130f7~pVGRl100Z0673406734eusmtip1T; Mon, 3 Mar 2025 15:25:21 +0000 (GMT) From: Michal Wilczynski To: robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, drew@pdp7.com, guoren@kernel.org, wefu@redhat.com, p.zabel@pengutronix.de, m.szyprowski@samsung.com Cc: devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Michal Wilczynski Subject: [PATCH v1 2/2] reset: thead: Add TH1520 reset controller driver Date: Mon, 3 Mar 2025 16:25:11 +0100 Message-Id: <20250303152511.494405-3-m.wilczynski@samsung.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250303152511.494405-1-m.wilczynski@samsung.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Brightmail-Tracker: H4sIAAAAAAAAA01Se1BMcRTud+/t7m3N6loNh6JpxQxNS8m4BmGEK8zEMIZpsJNra+xWdm3U KKlE2eTNVoRBWlZma5PViq2s7bHNUMYkW5PHsBiPEEJsN4//vvN93/l955z5Ubi41HM0FRe/ lVPFyxQSUkhU3vnaEtxtr5dP6dQj5rLFgTHFdQ5PxnmvAmNeWHYRzMsCJ8ncNxeRjKHusYAp +1SMMY+ddwmmv7pKwGTVHCHmDmGN+hySzTLcwdj8H1PYtzfbSHZ/hR6xPcaxUeRa4ayNnCIu iVNNDt8gjLWnVwkSe0O2G8p6UTrKnJSLKAroMHj3c1kuElJi+iKCTFMhzhcfETT3XxDwRQ+C OscxLBd5DXSY+nQYL5QgaGrIIPniNYKG+mOk20XSodBVUuzpFnzo8wg6c77hbgGnFWB+Y0Bu PJxmwZR9fYAn6PHQdyJngBfR4XDf/ALxcf5Qc7t5wONFzwHT836S9wwDu+4pwb/p/3dwoLso eNJnEPDNEVCmbyR5PBxctopB3g8aD2sJHidAl+kDzuMdcF1rG8QzocPxjXRfCacnQpl5Mk/P A1tmEeKPNxQevhnGjzAUDlUex3laBHuzxbx7AhzV5v0NdVysHDwiC86TRcQBFFDw3zIF/y1T 8C/3NML1aCSnUSvlnDo0ntsmVcuUak28XBqToDSi37+p8aftYxUqcb2XWhFGISsCCpf4iNr3 1MvFoo2y5BROlbBepVFwaivypQjJSNHZmt1yMS2XbeU2c1wip/qjYpTX6HTMw3Y4e+X8fMuq juPfvxAt0UlvYwNHcUE+qH3Wtt3Ke87YgBWJ3U06S3CoWbs6esZ0X1d4TO/OhZ7Gh9KEUakb 6j7DiFtRdFykIGjx7Wt5hRfm9/uliDMfZVz1uWENwV1pqZsUYZ19M86k2PWBC2OSr7Q05p3r CbC1nlbu9z5YvsBulOp6vZ3IcKrp3LoKDTttfHWeszRCsLOyyffBLUtXw7Pw6EulzX5zHxAh cVNrw+YtLVzTrknVudq0Y2ZrgjMaPim27GP905LNh1oDgiNeLXeNyz81e+KTg0n2rKiiV8Vb Xi/quNS91xptFO+pOhtZy9YIy9OqPW5+b0u3LmmF2gMSQh0rC5mEq9SyX32RH9y8AwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprJIsWRmVeSWpSXmKPExsVy+t/xu7oPTx5NN9h5SdNizd5zTBbzj5xj tbh3aQuTxYu9jSwWL2fdY7O4vGsOm8XaI3fZLdZ/nc9kcffeCRaL/3t2sFu07J/C4sDtsWlV J5tHy9pjTB79fw083u+7yubRt2UVo8fnTXIBbFF6NkX5pSWpChn5xSW2StGGFkZ6hpYWekYm lnqGxuaxVkamSvp2NimpOZllqUX6dgl6GScbdrAXfDesWLv+O2MDY7NWFyMnh4SAicTW3zOZ uhi5OIQEljJKvFzyhBkiISNxrfslC4QtLPHnWhcbRNErRom50x6DFbEJGEk8WD6fFSQhIrCe UaLz6iYmkASzQJ7E6w3d7CC2sICHxNa2nWANLAKqEr9ndDKC2LwCdhKXd71ghNggL7H/4Fmw Gk4Be4mtz/6zgdhCQDX3Ts9ghagXlDg58wkLxHx5ieats5knMArMQpKahSS1gJFpFaNIamlx bnpusZFecWJucWleul5yfu4mRmAcbTv2c8sOxpWvPuodYmTiYDzEKMHBrCTCe6v9aLoQb0pi ZVVqUX58UWlOavEhRlOguycyS4km5wMjOa8k3tDMwNTQxMzSwNTSzFhJnJftyvk0IYH0xJLU 7NTUgtQimD4mDk6pBqZdlSIzJp1/23xY5H39Ks2FE+8ccoy+/WDGlQdmH7o3TLtdesI9557E 1XtqDccu6LRZTWox+FG5PHBebm3Kj61XPJUFvx5ikSlsWV/y33njsY+LvdLvT+u480Kw4Kta kcBSzcLy+U6crX1nAxXsY7dGX7RiWRzN3Jk54/ijObKbX9qezNjYukwqVF5F6Nb0iQxqds9E i+ZPUz1n/FzH6cbL91t0+AW+/mW3mGe/05HjJaOiy2VlKXGHeXNOFi2ZPoNT3pYl50SqIGOJ nfXnszJr5R7rTfjJw6z9b0paYPABMynLC+aRLW9dzY/5P5r5Ls952bEJLzm/lvFYGx24mbPm mU/vHovvkhfdWEQm9rkosRRnJBpqMRcVJwIATz68DiwDAAA= X-CMS-MailID: 20250303152521eucas1p20128508eb79e20c1e124155beaf8fb4d X-Msg-Generator: CA Content-Type: text/plain; charset="utf-8" X-RootMTR: 20250303152521eucas1p20128508eb79e20c1e124155beaf8fb4d X-EPHeader: CA CMS-TYPE: 201P X-CMS-RootMailID: 20250303152521eucas1p20128508eb79e20c1e124155beaf8fb4d References: <20250303152511.494405-1-m.wilczynski@samsung.com> Add reset controller driver for the T-HEAD TH1520 SoC that manages hardware reset lines for various subsystems. The driver currently implements support for GPU reset control, with infrastructure in place to extend support for NPU and Watchdog Timer resets in future updates. Reviewed-by: Philipp Zabel Signed-off-by: Michal Wilczynski --- MAINTAINERS | 1 + drivers/reset/Kconfig | 10 +++ drivers/reset/Makefile | 1 + drivers/reset/reset-th1520.c | 135 +++++++++++++++++++++++++++++++++++ 4 files changed, 147 insertions(+) create mode 100644 drivers/reset/reset-th1520.c diff --git a/MAINTAINERS b/MAINTAINERS index 819686e98214..e4a0a83b4c11 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -20425,6 +20425,7 @@ F: drivers/mailbox/mailbox-th1520.c F: drivers/net/ethernet/stmicro/stmmac/dwmac-thead.c F: drivers/pinctrl/pinctrl-th1520.c F: drivers/pmdomain/thead/ +F: drivers/reset/reset-th1520.c F: include/dt-bindings/clock/thead,th1520-clk-ap.h F: include/dt-bindings/power/thead,th1520-power.h F: include/dt-bindings/reset/thead,th1520-reset.h diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 5b3abb6db248..fa0943c3d1de 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -272,6 +272,16 @@ config RESET_SUNXI help This enables the reset driver for Allwinner SoCs. =20 +config RESET_TH1520 + tristate "T-HEAD 1520 reset controller" + depends on ARCH_THEAD || COMPILE_TEST + select REGMAP_MMIO + help + This driver provides support for the T-HEAD TH1520 SoC reset controller, + which manages hardware reset lines for SoC components such as the GPU. + Enable this option if you need to control hardware resets on TH1520-bas= ed + systems. + config RESET_TI_SCI tristate "TI System Control Interface (TI-SCI) reset driver" depends on TI_SCI_PROTOCOL || (COMPILE_TEST && TI_SCI_PROTOCOL=3Dn) diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 677c4d1e2632..d6c2774407ae 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_RESET_SIMPLE) +=3D reset-simple.o obj-$(CONFIG_RESET_SOCFPGA) +=3D reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) +=3D reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) +=3D reset-sunxi.o +obj-$(CONFIG_RESET_TH1520) +=3D reset-th1520.o obj-$(CONFIG_RESET_TI_SCI) +=3D reset-ti-sci.o obj-$(CONFIG_RESET_TI_SYSCON) +=3D reset-ti-syscon.o obj-$(CONFIG_RESET_TI_TPS380X) +=3D reset-tps380x.o diff --git a/drivers/reset/reset-th1520.c b/drivers/reset/reset-th1520.c new file mode 100644 index 000000000000..7874f0693e1b --- /dev/null +++ b/drivers/reset/reset-th1520.c @@ -0,0 +1,135 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (c) 2024 Samsung Electronics Co., Ltd. + * Author: Michal Wilczynski + */ + +#include +#include +#include +#include + +#include + + /* register offset in VOSYS_REGMAP */ +#define TH1520_GPU_RST_CFG 0x0 +#define TH1520_GPU_RST_CFG_MASK GENMASK(1, 0) + +/* register values */ +#define TH1520_GPU_SW_GPU_RST BIT(0) +#define TH1520_GPU_SW_CLKGEN_RST BIT(1) + +struct th1520_reset_priv { + struct reset_controller_dev rcdev; + struct regmap *map; +}; + +struct th1520_reset_map { + u32 bit; + u32 reg; +}; + +static const struct th1520_reset_map th1520_resets[] =3D { + [TH1520_RESET_ID_GPU] =3D { + .bit =3D TH1520_GPU_SW_GPU_RST, + .reg =3D TH1520_GPU_RST_CFG, + }, + [TH1520_RESET_ID_GPU_CLKGEN] =3D { + .bit =3D TH1520_GPU_SW_CLKGEN_RST, + .reg =3D TH1520_GPU_RST_CFG, + } +}; + +static inline struct th1520_reset_priv * +to_th1520_reset(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct th1520_reset_priv, rcdev); +} + +static int th1520_reset_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct th1520_reset_priv *priv =3D to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + + reset =3D &th1520_resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, 0); +} + +static int th1520_reset_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct th1520_reset_priv *priv =3D to_th1520_reset(rcdev); + const struct th1520_reset_map *reset; + + reset =3D &th1520_resets[id]; + + return regmap_update_bits(priv->map, reset->reg, reset->bit, + reset->bit); +} + +static const struct reset_control_ops th1520_reset_ops =3D { + .assert =3D th1520_reset_assert, + .deassert =3D th1520_reset_deassert, +}; + +static const struct regmap_config th1520_reset_regmap_config =3D { + .reg_bits =3D 32, + .val_bits =3D 32, + .reg_stride =3D 4, + .fast_io =3D true, +}; + +static int th1520_reset_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + struct th1520_reset_priv *priv; + void __iomem *base; + int ret; + + priv =3D devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + base =3D devm_platform_ioremap_resource(pdev, 0); + if (IS_ERR(base)) + return PTR_ERR(base); + + priv->map =3D devm_regmap_init_mmio(dev, base, + &th1520_reset_regmap_config); + if (IS_ERR(priv->map)) + return PTR_ERR(priv->map); + + /* Initialize GPU resets to asserted state */ + ret =3D regmap_update_bits(priv->map, TH1520_GPU_RST_CFG, + TH1520_GPU_RST_CFG_MASK, 0); + if (ret) + return ret; + + priv->rcdev.owner =3D THIS_MODULE; + priv->rcdev.nr_resets =3D ARRAY_SIZE(th1520_resets); + priv->rcdev.ops =3D &th1520_reset_ops; + priv->rcdev.of_node =3D dev->of_node; + + return devm_reset_controller_register(dev, &priv->rcdev); +} + +static const struct of_device_id th1520_reset_match[] =3D { + { .compatible =3D "thead,th1520-reset" }, + { /* sentinel */ } +}; +MODULE_DEVICE_TABLE(of, th1520_reset_match); + +static struct platform_driver th1520_reset_driver =3D { + .driver =3D { + .name =3D "th1520-reset", + .of_match_table =3D th1520_reset_match, + }, + .probe =3D th1520_reset_probe, +}; +module_platform_driver(th1520_reset_driver); + +MODULE_AUTHOR("Michal Wilczynski "); +MODULE_DESCRIPTION("T-HEAD TH1520 SoC reset controller"); +MODULE_LICENSE("GPL"); --=20 2.34.1