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Mon, 03 Mar 2025 03:17:19 -0800 (PST) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH 1/2] dt-bindings: interrupt-controller: Add Sophgo SG2044 MSI controller Date: Mon, 3 Mar 2025 19:16:46 +0800 Message-ID: <20250303111648.1337543-2-inochiama@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250303111648.1337543-1-inochiama@gmail.com> References: <20250303111648.1337543-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Like SG2042, SG2044 uses a similar msi controller to provide MSI interrupt for PCIe controllers. Add support for the SG2044 msi controller Signed-off-by: Inochi Amaoto Acked-by: Conor Dooley --- .../bindings/interrupt-controller/sophgo,sg2042-msi.yaml | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/Documentation/devicetree/bindings/interrupt-controller/sophgo,= sg2042-msi.yaml b/Documentation/devicetree/bindings/interrupt-controller/so= phgo,sg2042-msi.yaml index e1ffd55fa7bf..f6b8b1d92f79 100644 --- a/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-= msi.yaml +++ b/Documentation/devicetree/bindings/interrupt-controller/sophgo,sg2042-= msi.yaml @@ -18,7 +18,9 @@ allOf: =20 properties: compatible: - const: sophgo,sg2042-msi + enum: + - sophgo,sg2042-msi + - sophgo,sg2044-msi =20 reg: items: --=20 2.48.1 From nobody Sun Feb 8 07:21:42 2026 Received: from mail-qv1-f54.google.com (mail-qv1-f54.google.com [209.85.219.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B6EF11F9406; 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Mon, 03 Mar 2025 03:17:22 -0800 (PST) Received: from localhost ([2001:da8:7001:11::cb]) by smtp.gmail.com with UTF8SMTPSA id 6a1803df08f44-6e8a1aba663sm39485296d6.50.2025.03.03.03.17.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 03:17:22 -0800 (PST) From: Inochi Amaoto To: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, Yixun Lan , Longbin Li Subject: [PATCH 2/2] irqchip/sg2042-msi: Add the Sophgo SG2044 MSI interrupt controller Date: Mon, 3 Mar 2025 19:16:47 +0800 Message-ID: <20250303111648.1337543-3-inochiama@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250303111648.1337543-1-inochiama@gmail.com> References: <20250303111648.1337543-1-inochiama@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add support for Sophgo SG2044 MSI interrupt controller. Signed-off-by: Inochi Amaoto --- drivers/irqchip/irq-sg2042-msi.c | 86 ++++++++++++++++++++++++++++++-- 1 file changed, 82 insertions(+), 4 deletions(-) diff --git a/drivers/irqchip/irq-sg2042-msi.c b/drivers/irqchip/irq-sg2042-= msi.c index 9c0a5f2777a4..4b3992821797 100644 --- a/drivers/irqchip/irq-sg2042-msi.c +++ b/drivers/irqchip/irq-sg2042-msi.c @@ -21,6 +21,11 @@ =20 #define SG2042_MAX_MSI_VECTOR 32 =20 +struct sg2042_msi_of_data { + const struct irq_chip *irqchip; + const struct msi_parent_ops *parent_ops; +}; + struct sg2042_msi_chipdata { void __iomem *reg_clr; // clear reg, see TRM, 10.1.33, GP_INTR0_CLR =20 @@ -29,8 +34,10 @@ struct sg2042_msi_chipdata { u32 irq_first; // The vector number that MSIs starts u32 num_irqs; // The number of vectors for MSIs =20 - DECLARE_BITMAP(msi_map, SG2042_MAX_MSI_VECTOR); + unsigned long *msi_map; struct mutex msi_map_lock; // lock for msi_map + + const struct sg2042_msi_of_data *data; }; =20 static int sg2042_msi_allocate_hwirq(struct sg2042_msi_chipdata *data, int= num_req) @@ -81,6 +88,37 @@ static const struct irq_chip sg2042_msi_middle_irq_chip = =3D { .irq_compose_msi_msg =3D sg2042_msi_irq_compose_msi_msg, }; =20 +static void sg2044_msi_irq_ack(struct irq_data *d) +{ + struct sg2042_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + + writel(0, (unsigned int *)data->reg_clr + d->hwirq); + + irq_chip_ack_parent(d); +} + +static void sg2044_msi_irq_compose_msi_msg(struct irq_data *d, + struct msi_msg *msg) +{ + struct sg2042_msi_chipdata *data =3D irq_data_get_irq_chip_data(d); + phys_addr_t doorbell =3D data->doorbell_addr + 4 * (d->hwirq / 32); + + msg->address_lo =3D lower_32_bits(doorbell); + msg->address_hi =3D upper_32_bits(doorbell); + msg->data =3D d->hwirq % 32; +} + +static struct irq_chip sg2044_msi_middle_irq_chip =3D { + .name =3D "SG2044 MSI", + .irq_ack =3D sg2044_msi_irq_ack, + .irq_mask =3D irq_chip_mask_parent, + .irq_unmask =3D irq_chip_unmask_parent, +#ifdef CONFIG_SMP + .irq_set_affinity =3D irq_chip_set_affinity_parent, +#endif + .irq_compose_msi_msg =3D sg2044_msi_irq_compose_msi_msg, +}; + static int sg2042_msi_parent_domain_alloc(struct irq_domain *domain, unsigned int virq, int hwirq) { @@ -119,7 +157,7 @@ static int sg2042_msi_middle_domain_alloc(struct irq_do= main *domain, goto err_hwirq; =20 irq_domain_set_hwirq_and_chip(domain, virq + i, hwirq + i, - &sg2042_msi_middle_irq_chip, data); + data->data->irqchip, data); } =20 return 0; @@ -162,6 +200,21 @@ static const struct msi_parent_ops sg2042_msi_parent_o= ps =3D { .init_dev_msi_info =3D msi_lib_init_dev_msi_info, }; =20 +#define SG2044_MSI_FLAGS_REQUIRED (MSI_FLAG_USE_DEF_DOM_OPS | \ + MSI_FLAG_USE_DEF_CHIP_OPS) + +#define SG2044_MSI_FLAGS_SUPPORTED (MSI_GENERIC_FLAGS_MASK | \ + MSI_FLAG_PCI_MSIX) + +static const struct msi_parent_ops sg2044_msi_parent_ops =3D { + .required_flags =3D SG2044_MSI_FLAGS_REQUIRED, + .supported_flags =3D SG2044_MSI_FLAGS_SUPPORTED, + .bus_select_mask =3D MATCH_PCI_MSI, + .bus_select_token =3D DOMAIN_BUS_NEXUS, + .prefix =3D "SG2044-", + .init_dev_msi_info =3D msi_lib_init_dev_msi_info, +}; + static int sg2042_msi_init_domains(struct sg2042_msi_chipdata *data, struct irq_domain *plic_domain, struct device *dev) @@ -181,7 +234,7 @@ static int sg2042_msi_init_domains(struct sg2042_msi_ch= ipdata *data, irq_domain_update_bus_token(middle_domain, DOMAIN_BUS_NEXUS); =20 middle_domain->flags |=3D IRQ_DOMAIN_FLAG_MSI_PARENT; - middle_domain->msi_parent_ops =3D &sg2042_msi_parent_ops; + middle_domain->msi_parent_ops =3D data->data->parent_ops; =20 return 0; } @@ -199,6 +252,12 @@ static int sg2042_msi_probe(struct platform_device *pd= ev) if (!data) return -ENOMEM; =20 + data->data =3D device_get_match_data(&pdev->dev); + if (!data->data) { + dev_err(&pdev->dev, "Failed to get irqchip\n"); + return -EINVAL; + } + data->reg_clr =3D devm_platform_ioremap_resource_byname(pdev, "clr"); if (IS_ERR(data->reg_clr)) { dev_err(dev, "Failed to map clear register\n"); @@ -240,11 +299,30 @@ static int sg2042_msi_probe(struct platform_device *p= dev) =20 mutex_init(&data->msi_map_lock); =20 + data->msi_map =3D devm_bitmap_zalloc(&pdev->dev, data->num_irqs, GFP_KERN= EL); + if (!data->msi_map) { + dev_err(&pdev->dev, "Unable to allocate msi mapping\n"); + return -ENOMEM; + } + return sg2042_msi_init_domains(data, plic_domain, dev); } =20 +static const struct sg2042_msi_of_data sg2042_of_data =3D { + .irqchip =3D &sg2042_msi_middle_irq_chip, + .parent_ops =3D &sg2042_msi_parent_ops, +}; + +static const struct sg2042_msi_of_data sg2044_of_data =3D { + .irqchip =3D &sg2044_msi_middle_irq_chip, + .parent_ops =3D &sg2044_msi_parent_ops, +}; + static const struct of_device_id sg2042_msi_of_match[] =3D { - { .compatible =3D "sophgo,sg2042-msi" }, + { .compatible =3D "sophgo,sg2042-msi", + .data =3D &sg2042_of_data }, + { .compatible =3D "sophgo,sg2044-msi", + .data =3D &sg2044_of_data }, {} }; =20 --=20 2.48.1