From nobody Tue Feb 10 22:56:42 2026 Received: from mail-pl1-f172.google.com (mail-pl1-f172.google.com [209.85.214.172]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 961FD22ACCA for ; Mon, 3 Mar 2025 15:16:35 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.214.172 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741014997; cv=none; b=FNSiiqdShjnfMeVCZXg8B/KDRA6WPU3IX3XZzrjysCg0DJdHx404JdGBHP1qd+faaogU86ZdzhZnuUwmOlSdhjrg5g3Y++KXisb5iKXv1D2qi5VFYuGHtf+qROlgvCAN7qzAWBuZboPkXkUdWRpLQjLMDMxZJIsaKJw2wIJ23kc= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1741014997; c=relaxed/simple; bh=rX4nJ3PHyeb9gnK5N+cxWYOBB+Jzkkre8ByfC3xgFBE=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=d9wBtortth3jPxHNJvHgR0mAMksQ7v9bElvKlYcusZJbg1eG8T4uYSBT00/Y6ktNT5S6mJ8i2hnPEox1Za1bK0+QfXKTLmeEGn5OQJhzF1y/8NdXeF+ZXfY2glm+fOv6V8w7K/kNp9RUQT44kp4GqPVmXqjbKYkkkxm9NpDVoBY= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=aBXebKEk; arc=none smtp.client-ip=209.85.214.172 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="aBXebKEk" Received: by mail-pl1-f172.google.com with SMTP id d9443c01a7336-2239c066347so28178435ad.2 for ; Mon, 03 Mar 2025 07:16:35 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1741014994; x=1741619794; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=MS7z2kKTQMha/2re0nvvr2SV5BXsIJZSh7OQaRN4Das=; b=aBXebKEkWn1drsrFz+tPHNF0gNI2Y8T/e0xP27SQ98KbDLnV0BdYuNdW8eIzk0BJiE 0rShK1zoUukMN5q32hSJUN7Se28YMiJiC3v/jhZksRm4w2oxdMKJAeu0SrICGBhzVdT6 G4Vtns3lZ/zMJ2lDEGmg7yK+Yey78lT+cCoaYn1kJ+PE/wNHqW0RWPAHJlcoItyjU3vM xmBZ33Lf+kfwmgKo/LYRQSeSq1OJV/2Ctt7SjIobuD4bOx99ghEqSthQGrNkKqA4ycpY ///BCO0ge3N9CRKz9AVu4RYexl33KCnPXy1WuXkBPdWPcdub4r+2dxedbjPFSbaKGH6n Domw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1741014994; x=1741619794; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=MS7z2kKTQMha/2re0nvvr2SV5BXsIJZSh7OQaRN4Das=; b=JJJjQ/2qV9aGLJcwEIdnmHWEt0qYEihe8oas2Y979aZxxQUIG8Pq90i23fOK34U3TF +hnSE1cDZZuCd1ZPdpPe1V0HfzZgRdbWtk1OLtaw3C8UrWuuPWnRA2cq3NB6Dk1fIj5J 1h8HnN/2Eu3n1Fg690YWqhrqPj60olIdobSBqujf5y+lAurSs26qb2ic4BDbSN3RILDm dFth3OeYvXxet0i1TnvTbME7UqCXOk6NJgW/Y6BMHY8WIFnRO3Ht7fB1qfsv5soSmSvI JuBdUIU0div/bo4wSG/POTYXvviNAjDjGk/A9iTiv/lmKVjogbKSMsP6KWPsTF4ng0Zn 1I5w== X-Forwarded-Encrypted: i=1; AJvYcCWpQ5ooX5YcdvdrgvB+MDEPPvTsUwK7sNv9nhU82ow5DGufoxeveGLj8Eha6vAcIMv8uCjLHhhNFMGPn04=@vger.kernel.org X-Gm-Message-State: AOJu0YybDsP+Jz3CxS+BQc1Hvbf63+7F68EgWpOl1wNzIfrSGXuH5vh7 TLPBlFPmY7urSrFAipn8xssfdLjsOeryPxfDxNzBOCC0h4nQVVt+zexA65G0c8EX7osi8UA3gGB axmk3+A== X-Gm-Gg: ASbGncvXVRAIAoGbH1QsS/CVv+zUxWPnXpCr4p/p7iHRy/Oh0/a5UlFkLf+r7y5clH2 GTo88vYNKfpOeJJGP8gFj+jmT4VaboWazspSpAo7/mOtIFIVPGHBSvor/5sPYPMS2uQrVTriZv+ zUs1zAACdwV/wDV/4KCBvTRsjatJ6YsjdS8NBuPjrqNkgS/nl+nk2HIlYi9k8cPOlpBv4DcOa7F mXaFQ5YcjxGyZuLnYp7WpGl+lZ3xiaXWIVPd2fkTNlQ/77g96jvxqZeqoM7aIMyEthGKnn1GAHm jHQnHAH+lvzQ3o2iWhTKOO5uaQSQdna2ZNBjb9A6Hw== X-Google-Smtp-Source: AGHT+IGqsUIgxn0VTNpF19GsGLIer8kpx9wejYDX5o6ypocdMcDRG9DFSFFgDQK2xCjfWuXX2Z073g== X-Received: by 2002:a17:902:da8d:b0:215:9bc2:42ec with SMTP id d9443c01a7336-22369260956mr180094215ad.47.1741014994609; Mon, 03 Mar 2025 07:16:34 -0800 (PST) Received: from [127.0.1.1] ([112.64.60.252]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-736584b3cffsm1851984b3a.4.2025.03.03.07.16.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 03 Mar 2025 07:16:34 -0800 (PST) From: Jun Nie Date: Mon, 03 Mar 2025 23:14:44 +0800 Subject: [PATCH v8 15/15] drm/msm/dpu: Enable quad-pipe for DSC and dual-DSI case Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250303-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v8-15-eb5df105c807@linaro.org> References: <20250303-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v8-0-eb5df105c807@linaro.org> In-Reply-To: <20250303-sm8650-v6-14-hmd-deckard-mdss-quad-upstream-oldbootwrapper-36-prep-v8-0-eb5df105c807@linaro.org> To: Rob Clark , Abhinav Kumar , Dmitry Baryshkov , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Jessica Zhang Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, Jun Nie X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=ed25519-sha256; t=1741014878; l=6430; i=jun.nie@linaro.org; s=20240403; h=from:subject:message-id; bh=rX4nJ3PHyeb9gnK5N+cxWYOBB+Jzkkre8ByfC3xgFBE=; b=9UZ4kRU7Qe3va1BaKQBnLEfFqWWUCBKjhv6fByihkWOdhAiMfzx9LyYLeSaGKDjgDcOGEd/qm nZPYWQnu/wVBHtKJD4K0/RfHVJvZg7184CAx0USfoxd9XSg+xCQPlEx X-Developer-Key: i=jun.nie@linaro.org; a=ed25519; pk=MNiBt/faLPvo+iJoP1hodyY2x6ozVXL8QMptmsKg3cc= To support high-resolution cases that exceed the width limitation of a pair of SSPPs, or scenarios that surpass the maximum MDP clock rate, additional pipes are necessary to enable parallel data processing within the SSPP width constraints and MDP clock rate. Request 4 mixers and 4 DSCs for high-resolution cases where both DSC and dual interfaces are enabled. More use cases can be incorporated later if quad-pipe capabilities are required. Signed-off-by: Jun Nie Reviewed-by: Dmitry Baryshkov --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 6 ++--- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 28 ++++++++++++++++++--= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 2 +- 6 files changed, 28 insertions(+), 14 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.c index fa487d625dde5cbd9a83ceb5163c049da45163f7..14b08f11a567b3747101fdbffa3= 6ff5701db7a83 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -200,7 +200,7 @@ static int dpu_crtc_get_lm_crc(struct drm_crtc *crtc, struct dpu_crtc_state *crtc_state) { struct dpu_crtc_mixer *m; - u32 crcs[CRTC_DUAL_MIXERS]; + u32 crcs[CRTC_QUAD_MIXERS]; =20 int rc =3D 0; int i; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h b/drivers/gpu/drm/msm= /disp/dpu1/dpu_crtc.h index b14bab2754635953da402d09e11a43b9b4cf4153..38820d05edb8b3003971dc6dc67= 5ba8ede847be8 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h @@ -210,7 +210,7 @@ struct dpu_crtc_state { =20 bool bw_control; bool bw_split_vote; - struct drm_rect lm_bounds[CRTC_DUAL_MIXERS]; + struct drm_rect lm_bounds[CRTC_QUAD_MIXERS]; =20 uint64_t input_fence_timeout_ns; =20 @@ -218,10 +218,10 @@ struct dpu_crtc_state { =20 /* HW Resources reserved for the crtc */ u32 num_mixers; - struct dpu_crtc_mixer mixers[CRTC_DUAL_MIXERS]; + struct dpu_crtc_mixer mixers[CRTC_QUAD_MIXERS]; =20 u32 num_ctls; - struct dpu_hw_ctl *hw_ctls[CRTC_DUAL_MIXERS]; + struct dpu_hw_ctl *hw_ctls[CRTC_QUAD_MIXERS]; =20 enum dpu_crtc_crc_source crc_source; int crc_frame_skip_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/= msm/disp/dpu1/dpu_encoder.c index c89a5da0fa8321e9082d5aee304fa16402bb4ad9..d4719b45f4cdd5d1f0bd585283c= 0c16f1df2f1f2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -54,7 +54,7 @@ #define MAX_PHYS_ENCODERS_PER_VIRTUAL \ (MAX_H_TILES_PER_DISPLAY * NUM_PHYS_ENCODER_TYPES) =20 -#define MAX_CHANNELS_PER_ENC 2 +#define MAX_CHANNELS_PER_ENC 4 =20 #define IDLE_SHORT_TIMEOUT 1 =20 @@ -664,9 +664,13 @@ static struct msm_display_topology dpu_encoder_get_top= ology( =20 /* Datapath topology selection * - * Dual display + * Dual display without DSC * 2 LM, 2 INTF ( Split display using 2 interfaces) * + * Dual display with DSC + * 2 LM, 2 INTF ( Split display using 2 interfaces) + * 4 LM, 2 INTF ( Split display using 2 interfaces) + * * Single display * 1 LM, 1 INTF * 2 LM, 1 INTF (stream merge to support high resolution interfaces) @@ -691,10 +695,20 @@ static struct msm_display_topology dpu_encoder_get_to= pology( * 2 DSC encoders, 2 layer mixers and 1 interface * this is power optimal and can drive up to (including) 4k * screens + * But for dual display case, we prefer 4 layer mixers. Because + * the resolution is always high in the case and 4 DSCs are more + * power optimal. */ - topology.num_dsc =3D 2; - topology.num_lm =3D 2; - topology.num_intf =3D 1; + + if (intf_count =3D=3D 2 && dpu_kms->catalog->dsc_count >=3D 4) { + topology.num_dsc =3D 4; + topology.num_lm =3D 4; + topology.num_intf =3D 2; + } else { + topology.num_dsc =3D 2; + topology.num_lm =3D 2; + topology.num_intf =3D 1; + } } =20 return topology; @@ -2189,8 +2203,8 @@ static void dpu_encoder_helper_reset_mixers(struct dp= u_encoder_phys *phys_enc) struct dpu_hw_mixer_cfg mixer; int i, num_lm; struct dpu_global_state *global_state; - struct dpu_hw_blk *hw_lm[2]; - struct dpu_hw_mixer *hw_mixer[2]; + struct dpu_hw_blk *hw_lm[MAX_CHANNELS_PER_ENC]; + struct dpu_hw_mixer *hw_mixer[MAX_CHANNELS_PER_ENC]; struct dpu_hw_ctl *ctl =3D phys_enc->hw_ctl; =20 memset(&mixer, 0, sizeof(mixer)); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu= /drm/msm/disp/dpu1/dpu_encoder_phys.h index 63f09857025c2004dcb56bd33e9c51f8e0f80e48..a9e122243dce9006aaa582a1537= 980c86b6203a4 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -302,7 +302,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper= _get_3d_blend_mode( =20 /* Use merge_3d unless DSC MERGE topology is used */ if (phys_enc->split_role =3D=3D ENC_ROLE_SOLO && - dpu_cstate->num_mixers =3D=3D CRTC_DUAL_MIXERS && + (dpu_cstate->num_mixers !=3D 1) && !dpu_encoder_use_dsc_merge(phys_enc->parent)) return BLEND_3D_H_ROW_INT; =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 4cea19e1a20380c56ae014f2d33a6884a72e0ca0..77a7a5375d545483edb316e8428= df12212191362 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -24,7 +24,7 @@ #define DPU_MAX_IMG_WIDTH 0x3fff #define DPU_MAX_IMG_HEIGHT 0x3fff =20 -#define CRTC_DUAL_MIXERS 2 +#define CRTC_QUAD_MIXERS 4 =20 #define MAX_XIN_COUNT 16 =20 diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h b/drivers/gpu/drm/= msm/disp/dpu1/dpu_hw_mdss.h index 74bf3ab9d6cfb8152b32d89a6c66e4d92d5cee1d..804858e69e7da1c8c67c725aa46= 2c1a558d1b402 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h @@ -34,7 +34,7 @@ #define DPU_MAX_PLANES 4 #endif =20 -#define STAGES_PER_PLANE 1 +#define STAGES_PER_PLANE 2 #define PIPES_PER_STAGE 2 #define PIPES_PER_PLANE (PIPES_PER_STAGE * STAGES_PER_PLANE) #ifndef DPU_MAX_DE_CURVES --=20 2.34.1