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Mon, 03 Mar 2025 05:18:52 -0800 (PST) From: Bartosz Golaszewski Date: Mon, 03 Mar 2025 14:18:39 +0100 Subject: [PATCH 14/15] gpio: aspeed-sgpio: use lock guards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250303-gpiochip-set-conversion-v1-14-1d5cceeebf8b@linaro.org> References: <20250303-gpiochip-set-conversion-v1-0-1d5cceeebf8b@linaro.org> In-Reply-To: <20250303-gpiochip-set-conversion-v1-0-1d5cceeebf8b@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Michael Hennerich , Laurent Pinchart , Mun Yew Tham , Joel Stanley , Andrew Jeffery Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, patches@opensource.cirrus.com, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Reduce the code complexity by using automatic lock guards with the raw spinlock. Signed-off-by: Bartosz Golaszewski Reviewed-by: Andrew Jeffery --- drivers/gpio/gpio-aspeed-sgpio.c | 76 +++++++++++++++---------------------= ---- 1 file changed, 29 insertions(+), 47 deletions(-) diff --git a/drivers/gpio/gpio-aspeed-sgpio.c b/drivers/gpio/gpio-aspeed-sg= pio.c index 34eb26298e32..5ce86de22563 100644 --- a/drivers/gpio/gpio-aspeed-sgpio.c +++ b/drivers/gpio/gpio-aspeed-sgpio.c @@ -6,6 +6,7 @@ */ =20 #include +#include #include #include #include @@ -170,17 +171,14 @@ static int aspeed_sgpio_get(struct gpio_chip *gc, uns= igned int offset) { struct aspeed_sgpio *gpio =3D gpiochip_get_data(gc); const struct aspeed_sgpio_bank *bank =3D to_bank(offset); - unsigned long flags; enum aspeed_sgpio_reg reg; int rc =3D 0; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 reg =3D aspeed_sgpio_is_input(offset) ? reg_val : reg_rdata; rc =3D !!(ioread32(bank_reg(gpio, bank, reg)) & GPIO_BIT(offset)); =20 - raw_spin_unlock_irqrestore(&gpio->lock, flags); - return rc; } =20 @@ -214,13 +212,10 @@ static int sgpio_set_value(struct gpio_chip *gc, unsi= gned int offset, int val) static void aspeed_sgpio_set(struct gpio_chip *gc, unsigned int offset, in= t val) { struct aspeed_sgpio *gpio =3D gpiochip_get_data(gc); - unsigned long flags; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 sgpio_set_value(gc, offset, val); - - raw_spin_unlock_irqrestore(&gpio->lock, flags); } =20 static int aspeed_sgpio_dir_in(struct gpio_chip *gc, unsigned int offset) @@ -231,15 +226,14 @@ static int aspeed_sgpio_dir_in(struct gpio_chip *gc, = unsigned int offset) static int aspeed_sgpio_dir_out(struct gpio_chip *gc, unsigned int offset,= int val) { struct aspeed_sgpio *gpio =3D gpiochip_get_data(gc); - unsigned long flags; int rc; =20 /* No special action is required for setting the direction; we'll * error-out in sgpio_set_value if this isn't an output GPIO */ =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); + rc =3D sgpio_set_value(gc, offset, val); - raw_spin_unlock_irqrestore(&gpio->lock, flags); =20 return rc; } @@ -269,7 +263,6 @@ static void aspeed_sgpio_irq_ack(struct irq_data *d) { const struct aspeed_sgpio_bank *bank; struct aspeed_sgpio *gpio; - unsigned long flags; void __iomem *status_addr; int offset; u32 bit; @@ -278,18 +271,15 @@ static void aspeed_sgpio_irq_ack(struct irq_data *d) =20 status_addr =3D bank_reg(gpio, bank, reg_irq_status); =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 iowrite32(bit, status_addr); - - raw_spin_unlock_irqrestore(&gpio->lock, flags); } =20 static void aspeed_sgpio_irq_set_mask(struct irq_data *d, bool set) { const struct aspeed_sgpio_bank *bank; struct aspeed_sgpio *gpio; - unsigned long flags; u32 reg, bit; void __iomem *addr; int offset; @@ -301,17 +291,15 @@ static void aspeed_sgpio_irq_set_mask(struct irq_data= *d, bool set) if (set) gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + scoped_guard(raw_spinlock_irqsave, &gpio->lock) { + reg =3D ioread32(addr); + if (set) + reg |=3D bit; + else + reg &=3D ~bit; =20 - reg =3D ioread32(addr); - if (set) - reg |=3D bit; - else - reg &=3D ~bit; - - iowrite32(reg, addr); - - raw_spin_unlock_irqrestore(&gpio->lock, flags); + iowrite32(reg, addr); + } =20 /* Masking the IRQ */ if (!set) @@ -339,7 +327,6 @@ static int aspeed_sgpio_set_type(struct irq_data *d, un= signed int type) const struct aspeed_sgpio_bank *bank; irq_flow_handler_t handler; struct aspeed_sgpio *gpio; - unsigned long flags; void __iomem *addr; int offset; =20 @@ -366,24 +353,22 @@ static int aspeed_sgpio_set_type(struct irq_data *d, = unsigned int type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + scoped_guard(raw_spinlock_irqsave, &gpio->lock) { + addr =3D bank_reg(gpio, bank, reg_irq_type0); + reg =3D ioread32(addr); + reg =3D (reg & ~bit) | type0; + iowrite32(reg, addr); =20 - addr =3D bank_reg(gpio, bank, reg_irq_type0); - reg =3D ioread32(addr); - reg =3D (reg & ~bit) | type0; - iowrite32(reg, addr); + addr =3D bank_reg(gpio, bank, reg_irq_type1); + reg =3D ioread32(addr); + reg =3D (reg & ~bit) | type1; + iowrite32(reg, addr); =20 - addr =3D bank_reg(gpio, bank, reg_irq_type1); - reg =3D ioread32(addr); - reg =3D (reg & ~bit) | type1; - iowrite32(reg, addr); - - addr =3D bank_reg(gpio, bank, reg_irq_type2); - reg =3D ioread32(addr); - reg =3D (reg & ~bit) | type2; - iowrite32(reg, addr); - - raw_spin_unlock_irqrestore(&gpio->lock, flags); + addr =3D bank_reg(gpio, bank, reg_irq_type2); + reg =3D ioread32(addr); + reg =3D (reg & ~bit) | type2; + iowrite32(reg, addr); + } =20 irq_set_handler_locked(d, handler); =20 @@ -487,13 +472,12 @@ static int aspeed_sgpio_reset_tolerance(struct gpio_c= hip *chip, unsigned int offset, bool enable) { struct aspeed_sgpio *gpio =3D gpiochip_get_data(chip); - unsigned long flags; void __iomem *reg; u32 val; =20 reg =3D bank_reg(gpio, to_bank(offset), reg_tolerance); =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 val =3D readl(reg); =20 @@ -504,8 +488,6 @@ static int aspeed_sgpio_reset_tolerance(struct gpio_chi= p *chip, =20 writel(val, reg); =20 - raw_spin_unlock_irqrestore(&gpio->lock, flags); - return 0; } =20 --=20 2.45.2