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Mon, 03 Mar 2025 05:18:50 -0800 (PST) From: Bartosz Golaszewski Date: Mon, 03 Mar 2025 14:18:37 +0100 Subject: [PATCH 12/15] gpio: aspeed: use lock guards Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250303-gpiochip-set-conversion-v1-12-1d5cceeebf8b@linaro.org> References: <20250303-gpiochip-set-conversion-v1-0-1d5cceeebf8b@linaro.org> In-Reply-To: <20250303-gpiochip-set-conversion-v1-0-1d5cceeebf8b@linaro.org> To: Linus Walleij , Bartosz Golaszewski , Michael Hennerich , Laurent Pinchart , Mun Yew Tham , Joel Stanley , Andrew Jeffery Cc: linux-gpio@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, patches@opensource.cirrus.com, linux-arm-kernel@lists.infradead.org, linux-aspeed@lists.ozlabs.org, Bartosz Golaszewski X-Mailer: b4 0.14.1 X-Developer-Signature: v=1; a=openpgp-sha256; l=10512; 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a=openpgp; fpr=169DEB6C0BC3C46013D2C79F11A72EA01471D772 From: Bartosz Golaszewski Reduce the code complexity by using automatic lock guards with the raw spinlock. Signed-off-by: Bartosz Golaszewski Reviewed-by: Andrew Jeffery --- drivers/gpio/gpio-aspeed.c | 101 +++++++++++++++++------------------------= ---- 1 file changed, 38 insertions(+), 63 deletions(-) diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c index 40c1bd80f8b0..e2535aad1026 100644 --- a/drivers/gpio/gpio-aspeed.c +++ b/drivers/gpio/gpio-aspeed.c @@ -5,6 +5,7 @@ * Joel Stanley */ =20 +#include #include #include #include @@ -427,37 +428,33 @@ static void aspeed_gpio_set(struct gpio_chip *gc, uns= igned int offset, int val) { struct aspeed_gpio *gpio =3D gpiochip_get_data(gc); - unsigned long flags; bool copro =3D false; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); + copro =3D aspeed_gpio_copro_request(gpio, offset); =20 __aspeed_gpio_set(gc, offset, val); =20 if (copro) aspeed_gpio_copro_release(gpio, offset); - raw_spin_unlock_irqrestore(&gpio->lock, flags); } =20 static int aspeed_gpio_dir_in(struct gpio_chip *gc, unsigned int offset) { struct aspeed_gpio *gpio =3D gpiochip_get_data(gc); - unsigned long flags; bool copro =3D false; =20 if (!have_input(gpio, offset)) return -ENOTSUPP; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 copro =3D aspeed_gpio_copro_request(gpio, offset); gpio->config->llops->reg_bit_set(gpio, offset, reg_dir, 0); if (copro) aspeed_gpio_copro_release(gpio, offset); =20 - raw_spin_unlock_irqrestore(&gpio->lock, flags); - return 0; } =20 @@ -465,13 +462,12 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc, unsigned int offset, int val) { struct aspeed_gpio *gpio =3D gpiochip_get_data(gc); - unsigned long flags; bool copro =3D false; =20 if (!have_output(gpio, offset)) return -ENOTSUPP; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 copro =3D aspeed_gpio_copro_request(gpio, offset); __aspeed_gpio_set(gc, offset, val); @@ -479,7 +475,6 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc, =20 if (copro) aspeed_gpio_copro_release(gpio, offset); - raw_spin_unlock_irqrestore(&gpio->lock, flags); =20 return 0; } @@ -487,7 +482,6 @@ static int aspeed_gpio_dir_out(struct gpio_chip *gc, static int aspeed_gpio_get_direction(struct gpio_chip *gc, unsigned int of= fset) { struct aspeed_gpio *gpio =3D gpiochip_get_data(gc); - unsigned long flags; u32 val; =20 if (!have_input(gpio, offset)) @@ -496,12 +490,10 @@ static int aspeed_gpio_get_direction(struct gpio_chip= *gc, unsigned int offset) if (!have_output(gpio, offset)) return GPIO_LINE_DIRECTION_IN; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 val =3D gpio->config->llops->reg_bit_get(gpio, offset, reg_dir); =20 - raw_spin_unlock_irqrestore(&gpio->lock, flags); - return val ? GPIO_LINE_DIRECTION_OUT : GPIO_LINE_DIRECTION_IN; } =20 @@ -527,7 +519,6 @@ static inline int irqd_to_aspeed_gpio_data(struct irq_d= ata *d, static void aspeed_gpio_irq_ack(struct irq_data *d) { struct aspeed_gpio *gpio; - unsigned long flags; int rc, offset; bool copro =3D false; =20 @@ -535,20 +526,19 @@ static void aspeed_gpio_irq_ack(struct irq_data *d) if (rc) return; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); + copro =3D aspeed_gpio_copro_request(gpio, offset); =20 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_status, 1); =20 if (copro) aspeed_gpio_copro_release(gpio, offset); - raw_spin_unlock_irqrestore(&gpio->lock, flags); } =20 static void aspeed_gpio_irq_set_mask(struct irq_data *d, bool set) { struct aspeed_gpio *gpio; - unsigned long flags; int rc, offset; bool copro =3D false; =20 @@ -560,14 +550,14 @@ static void aspeed_gpio_irq_set_mask(struct irq_data = *d, bool set) if (set) gpiochip_enable_irq(&gpio->chip, irqd_to_hwirq(d)); =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); + copro =3D aspeed_gpio_copro_request(gpio, offset); =20 gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_enable, set); =20 if (copro) aspeed_gpio_copro_release(gpio, offset); - raw_spin_unlock_irqrestore(&gpio->lock, flags); =20 /* Masking the IRQ */ if (!set) @@ -591,7 +581,6 @@ static int aspeed_gpio_set_type(struct irq_data *d, uns= igned int type) u32 type2 =3D 0; irq_flow_handler_t handler; struct aspeed_gpio *gpio; - unsigned long flags; int rc, offset; bool copro =3D false; =20 @@ -620,16 +609,19 @@ static int aspeed_gpio_set_type(struct irq_data *d, u= nsigned int type) return -EINVAL; } =20 - raw_spin_lock_irqsave(&gpio->lock, flags); - copro =3D aspeed_gpio_copro_request(gpio, offset); + scoped_guard(raw_spinlock_irqsave, &gpio->lock) { + copro =3D aspeed_gpio_copro_request(gpio, offset); =20 - gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, type0); - gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, type1); - gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, type2); + gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type0, + type0); + gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type1, + type1); + gpio->config->llops->reg_bit_set(gpio, offset, reg_irq_type2, + type2); =20 - if (copro) - aspeed_gpio_copro_release(gpio, offset); - raw_spin_unlock_irqrestore(&gpio->lock, flags); + if (copro) + aspeed_gpio_copro_release(gpio, offset); + } =20 irq_set_handler_locked(d, handler); =20 @@ -686,17 +678,16 @@ static int aspeed_gpio_reset_tolerance(struct gpio_ch= ip *chip, unsigned int offset, bool enable) { struct aspeed_gpio *gpio =3D gpiochip_get_data(chip); - unsigned long flags; bool copro =3D false; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); + copro =3D aspeed_gpio_copro_request(gpio, offset); =20 gpio->config->llops->reg_bit_set(gpio, offset, reg_tolerance, enable); =20 if (copro) aspeed_gpio_copro_release(gpio, offset); - raw_spin_unlock_irqrestore(&gpio->lock, flags); =20 return 0; } @@ -798,7 +789,6 @@ static int enable_debounce(struct gpio_chip *chip, unsi= gned int offset, { struct aspeed_gpio *gpio =3D gpiochip_get_data(chip); u32 requested_cycles; - unsigned long flags; int rc; int i; =20 @@ -812,12 +802,12 @@ static int enable_debounce(struct gpio_chip *chip, un= signed int offset, return rc; } =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 if (timer_allocation_registered(gpio, offset)) { rc =3D unregister_allocated_timer(gpio, offset); if (rc < 0) - goto out; + return rc; } =20 /* Try to find a timer already configured for the debounce period */ @@ -855,7 +845,7 @@ static int enable_debounce(struct gpio_chip *chip, unsi= gned int offset, * consistency. */ configure_timer(gpio, offset, 0); - goto out; + return rc; } =20 i =3D j; @@ -863,34 +853,26 @@ static int enable_debounce(struct gpio_chip *chip, un= signed int offset, iowrite32(requested_cycles, gpio->base + gpio->config->debounce_timers_a= rray[i]); } =20 - if (WARN(i =3D=3D 0, "Cannot register index of disabled timer\n")) { - rc =3D -EINVAL; - goto out; - } + if (WARN(i =3D=3D 0, "Cannot register index of disabled timer\n")) + return -EINVAL; =20 register_allocated_timer(gpio, offset, i); configure_timer(gpio, offset, i); =20 -out: - raw_spin_unlock_irqrestore(&gpio->lock, flags); - return rc; } =20 static int disable_debounce(struct gpio_chip *chip, unsigned int offset) { struct aspeed_gpio *gpio =3D gpiochip_get_data(chip); - unsigned long flags; int rc; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 rc =3D unregister_allocated_timer(gpio, offset); if (!rc) configure_timer(gpio, offset, 0); =20 - raw_spin_unlock_irqrestore(&gpio->lock, flags); - return rc; } =20 @@ -961,7 +943,6 @@ int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, struct aspeed_gpio *gpio =3D gpiochip_get_data(chip); int rc =3D 0, bindex, offset =3D gpio_chip_hwgpio(desc); const struct aspeed_gpio_bank *bank =3D to_bank(offset); - unsigned long flags; =20 if (!aspeed_gpio_support_copro(gpio)) return -EOPNOTSUPP; @@ -974,13 +955,12 @@ int aspeed_gpio_copro_grab_gpio(struct gpio_desc *des= c, return -EINVAL; bindex =3D offset >> 3; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 /* Sanity check, this shouldn't happen */ - if (gpio->cf_copro_bankmap[bindex] =3D=3D 0xff) { - rc =3D -EIO; - goto bail; - } + if (gpio->cf_copro_bankmap[bindex] =3D=3D 0xff) + return -EIO; + gpio->cf_copro_bankmap[bindex]++; =20 /* Switch command source */ @@ -994,8 +974,6 @@ int aspeed_gpio_copro_grab_gpio(struct gpio_desc *desc, *dreg_offset =3D bank->rdata_reg; if (bit) *bit =3D GPIO_OFFSET(offset); - bail: - raw_spin_unlock_irqrestore(&gpio->lock, flags); return rc; } EXPORT_SYMBOL_GPL(aspeed_gpio_copro_grab_gpio); @@ -1009,7 +987,6 @@ int aspeed_gpio_copro_release_gpio(struct gpio_desc *d= esc) struct gpio_chip *chip =3D gpiod_to_chip(desc); struct aspeed_gpio *gpio =3D gpiochip_get_data(chip); int rc =3D 0, bindex, offset =3D gpio_chip_hwgpio(desc); - unsigned long flags; =20 if (!aspeed_gpio_support_copro(gpio)) return -EOPNOTSUPP; @@ -1021,21 +998,19 @@ int aspeed_gpio_copro_release_gpio(struct gpio_desc = *desc) return -EINVAL; bindex =3D offset >> 3; =20 - raw_spin_lock_irqsave(&gpio->lock, flags); + guard(raw_spinlock_irqsave)(&gpio->lock); =20 /* Sanity check, this shouldn't happen */ - if (gpio->cf_copro_bankmap[bindex] =3D=3D 0) { - rc =3D -EIO; - goto bail; - } + if (gpio->cf_copro_bankmap[bindex] =3D=3D 0) + return -EIO; + gpio->cf_copro_bankmap[bindex]--; =20 /* Switch command source */ if (gpio->cf_copro_bankmap[bindex] =3D=3D 0) aspeed_gpio_change_cmd_source(gpio, offset, GPIO_CMDSRC_ARM); - bail: - raw_spin_unlock_irqrestore(&gpio->lock, flags); + return rc; } EXPORT_SYMBOL_GPL(aspeed_gpio_copro_release_gpio); --=20 2.45.2