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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e4c43a5acdsm5809705a12.77.2025.03.02.11.52.19 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Mar 2025 11:52:20 -0800 (PST) From: Alexander Sverdlin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-rtc@vger.kernel.org Cc: Jingbao Qiu , Inochi Amaoto , dlan@gentoo.org, linux-kernel@vger.kernel.org, Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Belloni , sophgo@lists.linux.dev, Alexander Sverdlin Subject: [PATCH v12 1/3] dt-bindings: mfd: sophgo: add RTC support for Sophgo CV1800 series SoC Date: Sun, 2 Mar 2025 20:51:54 +0100 Message-ID: <20250302195205.3183174-2-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250302195205.3183174-1-alexander.sverdlin@gmail.com> References: <20250302195205.3183174-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jingbao Qiu Add RTC devicetree binding for Sophgo CV1800 series SoC. The device is called RTC, but contains control registers of other HW blocks in its address space, most notably of Power-on-Reset (PoR) module, DW8051 IP (MCU core), accompanying SRAM, hence putting it in MFD subsystem. Signed-off-by: Jingbao Qiu Signed-off-by: Alexander Sverdlin --- Changelog: v12: - maintainer Jingbao Qiu -> sophgo@lists.linux.= dev - dropped Reviewed-by: Krzysztof Kozlowski - link to TRM - mentioned 8051 core in the description - binding is now MFD, not RTC - added "syscon" compatible - added "interrupt-names", "clock-names" (because of added PM/remoteproc) - main compatible "sophgo,cv1800-rtc" -> "sophgo,cv1800b-rtc" .../bindings/mfd/sophgo,cv1800b-rtc.yaml | 86 +++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 Documentation/devicetree/bindings/mfd/sophgo,cv1800b-rt= c.yaml diff --git a/Documentation/devicetree/bindings/mfd/sophgo,cv1800b-rtc.yaml = b/Documentation/devicetree/bindings/mfd/sophgo,cv1800b-rtc.yaml new file mode 100644 index 000000000000..b80d68502c48 --- /dev/null +++ b/Documentation/devicetree/bindings/mfd/sophgo,cv1800b-rtc.yaml @@ -0,0 +1,86 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/mfd/sophgo,cv1800b-rtc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Real Time Clock of the Sophgo CV1800 SoC + +description: + The RTC (Real Time Clock) is an independently powered module in the chip= . It + contains a 32KHz oscillator and a Power-On-Reset (POR) sub-module, which= can + be used for time display and scheduled alarm produce. In addition, the + hardware state machine provides triggering and timing control for chip + power-on, power-off and reset. + + Furthermore, the 8051 subsystem is located within RTCSYS and is independ= ently + powered. System software can use the 8051 to manage wake conditions and = wake + the system while the system is asleep, and communicate with external dev= ices + through peripheral controllers. + + Technical Reference Manual available at + https://github.com/sophgo/sophgo-doc/tree/main/SG200X/TRM + +maintainers: + - sophgo@lists.linux.dev + +allOf: + - $ref: /schemas/rtc/rtc.yaml# + +properties: + compatible: + items: + - const: sophgo,cv1800b-rtc + - const: syscon + + reg: + maxItems: 1 + + interrupts: + items: + - description: RTC Alarm + - description: RTC Longpress + - description: VBAT DET + + interrupt-names: + items: + - const: alarm + - const: longpress + - const: vbat + + clocks: + items: + - description: RTC clock source + - description: DW8051 MCU clock source + + clock-names: + items: + - const: rtc + - const: mcu + +required: + - compatible + - reg + - interrupts + - interrupt-names + - clocks + - clock-names + +unevaluatedProperties: false + +examples: + - | + #include + #include + + rtc@5025000 { + compatible =3D "sophgo,cv1800b-rtc", "syscon"; + reg =3D <0x5025000 0x2000>; + interrupts =3D <17 IRQ_TYPE_LEVEL_HIGH>, + <18 IRQ_TYPE_LEVEL_HIGH>, + <19 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names =3D "alarm", "longpress", "vbat"; + clocks =3D <&clk CLK_RTC_25M>, + <&clk CLK_SRC_RTC_SYS_0>; + clock-names =3D "rtc", "mcu"; + }; --=20 2.48.1 From nobody Thu Dec 18 20:16:18 2025 Received: from mail-ed1-f51.google.com (mail-ed1-f51.google.com [209.85.208.51]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 53E831EB1B9; Sun, 2 Mar 2025 19:52:24 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.208.51 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740945146; cv=none; b=Fbbsz2pVtsH+JRRzj30JN/F/xzc8rf9QJ1RNZ+TM9sBWThabVPyijy42k6cPfhsc1/7yJHxtnHTYBowE6fuf74DTJ2eHvl5PWyTinIFoUl6WGAnYPzG5nUY0qr7yphwmCxOtr8ljNkjOcgrjekAhVhFT1ui2nmckGlrbRPYkKfE= ARC-Message-Signature: i=1; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e4c43a5acdsm5809705a12.77.2025.03.02.11.52.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Mar 2025 11:52:21 -0800 (PST) From: Alexander Sverdlin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-rtc@vger.kernel.org Cc: Alexander Sverdlin , Inochi Amaoto , dlan@gentoo.org, linux-kernel@vger.kernel.org, Jingbao Qiu , Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Belloni , sophgo@lists.linux.dev Subject: [PATCH v12 2/3] mfd: sophgo: cv1800: rtcsys: New driver (handling RTC only) Date: Sun, 2 Mar 2025 20:51:55 +0100 Message-ID: <20250302195205.3183174-3-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250302195205.3183174-1-alexander.sverdlin@gmail.com> References: <20250302195205.3183174-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Add driver for Sophgo CV1800 series SoC RTC MFD. The RTC module comprises a 32kHz oscillator, Power-on-Reset (PoR) sub-module, HW state machine to control chip power-on, power-off and reset. Furthermore, the 8051 subsystem is located within RTCSYS including associated SRAM block. This patch only populates RTC sub-device. Signed-off-by: Alexander Sverdlin --- Changelog: v12: - new patch MAINTAINERS | 1 + drivers/mfd/Kconfig | 14 ++++++++ drivers/mfd/Makefile | 1 + drivers/mfd/cv1800-rtcsys.c | 66 +++++++++++++++++++++++++++++++++++++ 4 files changed, 82 insertions(+) create mode 100644 drivers/mfd/cv1800-rtcsys.c diff --git a/MAINTAINERS b/MAINTAINERS index 92fc0eca7061..446156998380 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22185,6 +22185,7 @@ M: Chen Wang M: Inochi Amaoto T: git https://github.com/sophgo/linux.git S: Maintained +F: drivers/mfd/cv1800-rtcsys.c N: sophgo K: sophgo =20 diff --git a/drivers/mfd/Kconfig b/drivers/mfd/Kconfig index 6b0682af6e32..842cc4d95c4b 100644 --- a/drivers/mfd/Kconfig +++ b/drivers/mfd/Kconfig @@ -285,6 +285,20 @@ config MFD_CS42L43_SDW Select this to support the Cirrus Logic CS42L43 PC CODEC with headphone and class D speaker drivers over SoundWire. =20 +config MFD_CV1800_RTCSYS + tristate "Sophgo CV1800 RTC MFD" + depends on ARCH_SOPHGO || COMPILE_TEST + select MFD_CORE + help + If you say yes here you get support the RTC MFD driver for Sophgo + CV1800 series SoC. The RTC module comprises a 32kHz oscillator, + Power-on-Reset (PoR) sub-module, HW state machine to control chip + power-on, power-off and reset. Furthermore, the 8051 subsystem is + located within RTCSYS including associated SRAM block. + + This driver can also be built as a module. If so, the module will be + called cv1800-rtcsys. + config MFD_MADERA tristate "Cirrus Logic Madera codecs" select MFD_CORE diff --git a/drivers/mfd/Makefile b/drivers/mfd/Makefile index 9220eaf7cf12..3cf03ffeedbb 100644 --- a/drivers/mfd/Makefile +++ b/drivers/mfd/Makefile @@ -18,6 +18,7 @@ obj-$(CONFIG_MFD_CROS_EC_DEV) +=3D cros_ec_dev.o obj-$(CONFIG_MFD_CS42L43) +=3D cs42l43.o obj-$(CONFIG_MFD_CS42L43_I2C) +=3D cs42l43-i2c.o obj-$(CONFIG_MFD_CS42L43_SDW) +=3D cs42l43-sdw.o +obj-$(CONFIG_MFD_CV1800_RTCSYS) +=3D cv1800-rtcsys.o obj-$(CONFIG_MFD_ENE_KB3930) +=3D ene-kb3930.o obj-$(CONFIG_MFD_EXYNOS_LPASS) +=3D exynos-lpass.o obj-$(CONFIG_MFD_GATEWORKS_GSC) +=3D gateworks-gsc.o diff --git a/drivers/mfd/cv1800-rtcsys.c b/drivers/mfd/cv1800-rtcsys.c new file mode 100644 index 000000000000..72d11284f1de --- /dev/null +++ b/drivers/mfd/cv1800-rtcsys.c @@ -0,0 +1,66 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Driver for Sophgo CV1800 series SoC RTC MFD + * + * The RTC module comprises a 32kHz oscillator, Power-on-Reset (PoR) sub-m= odule, + * HW state machine to control chip power-on, power-off and reset. Further= more, + * the 8051 subsystem is located within RTCSYS including associated SRAM b= lock. + * + * Copyright (C) 2025 Alexander Sverdlin + * + */ + +#include +#include +#include +#include + +static struct resource cv1800_rtcsys_irq_resources[] =3D { + DEFINE_RES_IRQ_NAMED(0, "alarm"), +}; + +static const struct mfd_cell cv1800_rtcsys_subdev[] =3D { + { + .name =3D "cv1800-rtc", + .num_resources =3D 1, + .resources =3D &cv1800_rtcsys_irq_resources[0], + }, +}; + +static const struct mfd_cell cv1800_rtcsys_rtc_subdev =3D + MFD_CELL_NAME("cv1800-rtc"); + +static int cv1800_rtcsys_probe(struct platform_device *pdev) +{ + int irq; + + irq =3D platform_get_irq_byname(pdev, "alarm"); + if (irq < 0) + return irq; + cv1800_rtcsys_irq_resources[0].start =3D irq; + cv1800_rtcsys_irq_resources[0].end =3D irq; + + return devm_mfd_add_devices(&pdev->dev, PLATFORM_DEVID_AUTO, + cv1800_rtcsys_subdev, + ARRAY_SIZE(cv1800_rtcsys_subdev), + NULL, 0, NULL); +} + +static const struct of_device_id cv1800_rtcsys_of_match[] =3D { + { .compatible =3D "sophgo,cv1800b-rtc" }, + { /* sentinel */ } +}; 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([2a02:1210:861b:6f00:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id 4fb4d7f45d1cf-5e4c43a5acdsm5809705a12.77.2025.03.02.11.52.22 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 02 Mar 2025 11:52:23 -0800 (PST) From: Alexander Sverdlin To: devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-rtc@vger.kernel.org Cc: Jingbao Qiu , Inochi Amaoto , dlan@gentoo.org, linux-kernel@vger.kernel.org, Lee Jones , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Belloni , sophgo@lists.linux.dev, Alexander Sverdlin Subject: [PATCH v12 3/3] rtc: sophgo: add rtc support for Sophgo CV1800 SoC Date: Sun, 2 Mar 2025 20:51:56 +0100 Message-ID: <20250302195205.3183174-4-alexander.sverdlin@gmail.com> X-Mailer: git-send-email 2.48.1 In-Reply-To: <20250302195205.3183174-1-alexander.sverdlin@gmail.com> References: <20250302195205.3183174-1-alexander.sverdlin@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Jingbao Qiu Implement the RTC driver for CV1800, which able to provide time alarm. Signed-off-by: Jingbao Qiu Signed-off-by: Alexander Sverdlin --- v12: - added MAINTAINERS entry - depends on cv1800-rtcsys MFD driver - use syscon for regmap - get named clock from parent MFD - corresponding platform device is expected to be instantiated by MFD stub Changes since v10: - only start RTC on set_time; Changes since v9: - further simplified bitmask macros; - unconditional RTC start (rtc_enable_sec_counter()), otherwise didn't start on SG2000; - dropped ANA_CALIB modification (has been forgotten in v8 with the drop of SW calibration to switch to HW calibration); - successfully tested on SG2000; MAINTAINERS | 1 + drivers/rtc/Kconfig | 12 +++ drivers/rtc/Makefile | 1 + drivers/rtc/rtc-cv1800.c | 218 +++++++++++++++++++++++++++++++++++++++ 4 files changed, 232 insertions(+) create mode 100644 drivers/rtc/rtc-cv1800.c diff --git a/MAINTAINERS b/MAINTAINERS index 446156998380..d4e0569da602 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -22186,6 +22186,7 @@ M: Inochi Amaoto T: git https://github.com/sophgo/linux.git S: Maintained F: drivers/mfd/cv1800-rtcsys.c +F: drivers/rtc/rtc-cv1800.c N: sophgo K: sophgo =20 diff --git a/drivers/rtc/Kconfig b/drivers/rtc/Kconfig index 0bbbf778ecfa..9da247ec4084 100644 --- a/drivers/rtc/Kconfig +++ b/drivers/rtc/Kconfig @@ -1395,6 +1395,18 @@ config RTC_DRV_ASM9260 This driver can also be built as a module. If so, the module will be called rtc-asm9260. =20 +config RTC_DRV_CV1800 + tristate "Sophgo CV1800 RTC" + depends on MFD_CV1800_RTCSYS || COMPILE_TEST + select MFD_SYSCON + select REGMAP + help + If you say yes here you get support the RTC driver for Sophgo CV1800 + series SoC. + + This driver can also be built as a module. If so, the module will be + called rtc-cv1800. + config RTC_DRV_DIGICOLOR tristate "Conexant Digicolor RTC" depends on ARCH_DIGICOLOR || COMPILE_TEST diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 489b4ab07068..621b30a33dda 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -44,6 +44,7 @@ obj-$(CONFIG_RTC_DRV_CADENCE) +=3D rtc-cadence.o obj-$(CONFIG_RTC_DRV_CMOS) +=3D rtc-cmos.o obj-$(CONFIG_RTC_DRV_CPCAP) +=3D rtc-cpcap.o obj-$(CONFIG_RTC_DRV_CROS_EC) +=3D rtc-cros-ec.o +obj-$(CONFIG_RTC_DRV_CV1800) +=3D rtc-cv1800.o obj-$(CONFIG_RTC_DRV_DA9052) +=3D rtc-da9052.o obj-$(CONFIG_RTC_DRV_DA9055) +=3D rtc-da9055.o obj-$(CONFIG_RTC_DRV_DA9063) +=3D rtc-da9063.o diff --git a/drivers/rtc/rtc-cv1800.c b/drivers/rtc/rtc-cv1800.c new file mode 100644 index 000000000000..18bc542bbdb8 --- /dev/null +++ b/drivers/rtc/rtc-cv1800.c @@ -0,0 +1,218 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * rtc-cv1800.c: RTC driver for Sophgo cv1800 RTC + * + * Author: Jingbao Qiu + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#define SEC_PULSE_GEN 0x1004 +#define ALARM_TIME 0x1008 +#define ALARM_ENABLE 0x100C +#define SET_SEC_CNTR_VAL 0x1010 +#define SET_SEC_CNTR_TRIG 0x1014 +#define SEC_CNTR_VAL 0x1018 + +/* + * When in VDDBKUP domain, this MACRO register + * does not power down + */ +#define MACRO_RO_T 0x14A8 +#define MACRO_RG_SET_T 0x1498 + +#define ALARM_ENABLE_MASK BIT(0) +#define SEL_SEC_PULSE BIT(31) + +struct cv1800_rtc_priv { + struct rtc_device *rtc_dev; + struct regmap *rtc_map; + struct clk *clk; + int irq; +}; + +static bool cv1800_rtc_enabled(struct device *dev) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + u32 reg; + + regmap_read(info->rtc_map, SEC_PULSE_GEN, ®); + + return (reg & SEL_SEC_PULSE) =3D=3D 0; +} + +static void cv1800_rtc_enable(struct device *dev) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + + /* Sec pulse generated internally */ + regmap_update_bits(info->rtc_map, SEC_PULSE_GEN, SEL_SEC_PULSE, 0); +} + +static int cv1800_rtc_alarm_irq_enable(struct device *dev, unsigned int en= abled) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + + regmap_write(info->rtc_map, ALARM_ENABLE, enabled); + + return 0; +} + +static int cv1800_rtc_set_alarm(struct device *dev, struct rtc_wkalrm *alr= m) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + unsigned long alarm_time; + + alarm_time =3D rtc_tm_to_time64(&alrm->time); + + cv1800_rtc_alarm_irq_enable(dev, 0); + + regmap_write(info->rtc_map, ALARM_TIME, alarm_time); + + cv1800_rtc_alarm_irq_enable(dev, alrm->enabled); + + return 0; +} + +static int cv1800_rtc_read_alarm(struct device *dev, struct rtc_wkalrm *al= arm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + u32 enabled; + u32 time; + + if (!cv1800_rtc_enabled(dev)) { + alarm->enabled =3D 0; + return 0; + } + + regmap_read(info->rtc_map, ALARM_ENABLE, &enabled); + + alarm->enabled =3D enabled & ALARM_ENABLE_MASK; + + regmap_read(info->rtc_map, ALARM_TIME, &time); + + rtc_time64_to_tm(time, &alarm->time); + + return 0; +} + +static int cv1800_rtc_read_time(struct device *dev, struct rtc_time *tm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + u32 sec; + + if (!cv1800_rtc_enabled(dev)) + return -EINVAL; + + regmap_read(info->rtc_map, SEC_CNTR_VAL, &sec); + + rtc_time64_to_tm(sec, tm); + + return 0; +} + +static int cv1800_rtc_set_time(struct device *dev, struct rtc_time *tm) +{ + struct cv1800_rtc_priv *info =3D dev_get_drvdata(dev); + unsigned long sec; + + sec =3D rtc_tm_to_time64(tm); + + regmap_write(info->rtc_map, SET_SEC_CNTR_VAL, sec); + regmap_write(info->rtc_map, SET_SEC_CNTR_TRIG, 1); + + regmap_write(info->rtc_map, MACRO_RG_SET_T, sec); + + cv1800_rtc_enable(dev); + + return 0; +} + +static irqreturn_t cv1800_rtc_irq_handler(int irq, void *dev_id) +{ + struct cv1800_rtc_priv *info =3D dev_id; + + rtc_update_irq(info->rtc_dev, 1, RTC_IRQF | RTC_AF); + + regmap_write(info->rtc_map, ALARM_ENABLE, 0); + + return IRQ_HANDLED; +} + +static const struct rtc_class_ops cv1800_rtc_ops =3D { + .read_time =3D cv1800_rtc_read_time, + .set_time =3D cv1800_rtc_set_time, + .read_alarm =3D cv1800_rtc_read_alarm, + .set_alarm =3D cv1800_rtc_set_alarm, + .alarm_irq_enable =3D cv1800_rtc_alarm_irq_enable, +}; + +static int cv1800_rtc_probe(struct platform_device *pdev) +{ + struct cv1800_rtc_priv *rtc; + int ret; + + rtc =3D devm_kzalloc(&pdev->dev, sizeof(*rtc), GFP_KERNEL); + if (!rtc) + return -ENOMEM; + + rtc->rtc_map =3D device_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(rtc->rtc_map)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->rtc_map), + "cannot get parent regmap\n"); + + rtc->irq =3D platform_get_irq(pdev, 0); + if (rtc->irq < 0) + return rtc->irq; + + rtc->clk =3D devm_clk_get_enabled(pdev->dev.parent, "rtc"); + if (IS_ERR(rtc->clk)) + return dev_err_probe(&pdev->dev, PTR_ERR(rtc->clk), + "rtc clk not found\n"); + + platform_set_drvdata(pdev, rtc); + + device_init_wakeup(&pdev->dev, 1); + + rtc->rtc_dev =3D devm_rtc_allocate_device(&pdev->dev); + if (IS_ERR(rtc->rtc_dev)) + return PTR_ERR(rtc->rtc_dev); + + rtc->rtc_dev->ops =3D &cv1800_rtc_ops; + rtc->rtc_dev->range_max =3D U32_MAX; + + ret =3D devm_request_irq(&pdev->dev, rtc->irq, cv1800_rtc_irq_handler, + IRQF_TRIGGER_HIGH, "rtc alarm", rtc); + if (ret) + return dev_err_probe(&pdev->dev, ret, + "cannot register interrupt handler\n"); + + return devm_rtc_register_device(rtc->rtc_dev); +} + +static const struct platform_device_id cv1800_rtc_id[] =3D { + { .name =3D "cv1800-rtc" }, + { /* sentinel */ }, +}; +MODULE_DEVICE_TABLE(platform, cv1800_rtc_id); + +static struct platform_driver cv1800_rtc_driver =3D { + .driver =3D { + .name =3D "sophgo-cv1800-rtc", + }, + .probe =3D cv1800_rtc_probe, + .id_table =3D cv1800_rtc_id, +}; + +module_platform_driver(cv1800_rtc_driver); +MODULE_AUTHOR("Jingbao Qiu"); +MODULE_DESCRIPTION("Sophgo cv1800 RTC Driver"); +MODULE_LICENSE("GPL"); --=20 2.48.1