From nobody Wed Feb 11 06:56:58 2026 Received: from lelvem-ot02.ext.ti.com (lelvem-ot02.ext.ti.com [198.47.23.235]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id B5C471172A; Sun, 2 Mar 2025 15:35:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=198.47.23.235 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740929720; cv=none; b=jd5VmGRCInytXPsGWE+PlRuIPqTrN8a7voW4uswUJHP6R+8KjFE5m87esMSHhDJXPev/DS7MtjnqcsrCFE0fv2GqlaDla1J55x4mYeRB70CVSYBYWTGO0JrOK3k+vVEIjbKtRuNJ00kOChSfSbe+dGWS7qch1qzgwRxIft+IgM4= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740929720; c=relaxed/simple; bh=qiPSUpZ8tQSUoMFXn8Nz2U3vwWL4hFbjzezFBG5v5pY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=Pu9EkEgM0HKl+9iB/bYlHZTvNgYdxjExK2P08s7ULi/fRRC1GteqYSxTrPqO/t9qWeE7GhvxDiFydxnadr++2NzVXaHuLguF0n1vN/bxUYdN6Z+WEMOtDy9FJx+9/TakxzMtwwGZJRJMI4Rf6t3aKhPx0aRpJK6ntqWkfxlme/8= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com; spf=pass smtp.mailfrom=ti.com; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b=VEWT5QN1; arc=none smtp.client-ip=198.47.23.235 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=quarantine dis=none) header.from=ti.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=ti.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (1024-bit key) header.d=ti.com header.i=@ti.com header.b="VEWT5QN1" Received: from lelv0265.itg.ti.com ([10.180.67.224]) by lelvem-ot02.ext.ti.com (8.15.2/8.15.2) with ESMTPS id 522FZ6QA3097659 (version=TLSv1.2 cipher=DHE-RSA-AES256-GCM-SHA384 bits=256 verify=OK); Sun, 2 Mar 2025 09:35:06 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=ti.com; s=ti-com-17Q1; t=1740929706; bh=NPKcnI2BsC2HrW88aQ+QAUgaihzhMvelNRF2yVdbpOU=; h=From:To:CC:Subject:Date:In-Reply-To:References; b=VEWT5QN1SNYxDkbSSMS4MirAcx6Mlsz8RqR8MJp0+iwuvaIKvQNrUYOgXjTLYmHfA H8r3nEPxajewDYhS5AF+rFTpt51y/P4st1548l59zIunyKRfTOSPGqAnQsVHh1DYG4 Eg8Ptwk0laYFtKSBxy1TTLNUKiWIj1CBdrCKECBE= Received: from DFLE111.ent.ti.com (dfle111.ent.ti.com [10.64.6.32]) by lelv0265.itg.ti.com (8.15.2/8.15.2) with ESMTPS id 522FZ59e002255 (version=TLSv1.2 cipher=AES256-GCM-SHA384 bits=256 verify=FAIL); Sun, 2 Mar 2025 09:35:06 -0600 Received: from DFLE103.ent.ti.com (10.64.6.24) by DFLE111.ent.ti.com (10.64.6.32) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23; Sun, 2 Mar 2025 09:35:05 -0600 Received: from lelvsmtp5.itg.ti.com (10.180.75.250) by DFLE103.ent.ti.com (10.64.6.24) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.2507.23 via Frontend Transport; Sun, 2 Mar 2025 09:35:05 -0600 Received: from localhost (chintan-thinkstation-p360-tower.dhcp.ti.com [172.24.227.220]) by lelvsmtp5.itg.ti.com (8.15.2/8.15.2) with ESMTP id 522FZ4t1071822; Sun, 2 Mar 2025 09:35:05 -0600 From: Chintan Vankar To: Conor Dooley , Krzysztof Kozlowski , Rob Herring , Tero Kristo , Vignesh Raghavendra , Nishanth Menon CC: , , , , Subject: [PATCH v2 1/2] arm64: dts: ti: k3-am68-sk/k3-j721s2-mcu: Add bootph-all property to enable Ethernet boot Date: Sun, 2 Mar 2025 21:05:01 +0530 Message-ID: <20250302153502.181832-2-c-vankar@ti.com> X-Mailer: git-send-email 2.34.1 In-Reply-To: <20250302153502.181832-1-c-vankar@ti.com> References: <20250302153502.181832-1-c-vankar@ti.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-C2ProcessedOrg: 333ef613-75bf-4e12-a4b1-8e3623f5dcea Content-Type: text/plain; charset="utf-8" Ethernet boot requires CPSW nodes to be present starting from R5 SPL stage. Add bootph-all property to required nodes to enable Ethernet boot on AM68-SK and J721S2-EVM. Signed-off-by: Chintan Vankar Reviewed-by: Siddharth Vadapalli --- Link to v1: https://lore.kernel.org/r/20250106123122.3531845-2-c-vankar@ti.com/ Changes from v1 to v2: - No changes. arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts | 3 +++ arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi | 4 ++++ 2 files changed, 7 insertions(+) diff --git a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts b/arch/arm64/= boot/dts/ti/k3-am68-sk-base-board.dts index 11522b36e0ce..8e9101dd2152 100644 --- a/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts +++ b/arch/arm64/boot/dts/ti/k3-am68-sk-base-board.dts @@ -333,6 +333,7 @@ J721S2_WKUP_IOPAD(0x008, PIN_OUTPUT, 0) /* (E22) MCU_RG= MII1_TD3 */ J721S2_WKUP_IOPAD(0x018, PIN_OUTPUT, 0) /* (F21) MCU_RGMII1_TXC */ J721S2_WKUP_IOPAD(0x000, PIN_OUTPUT, 0) /* (F22) MCU_RGMII1_TX_CTL */ >; + bootph-all; }; =20 mcu_mdio_pins_default: mcu-mdio-default-pins { @@ -340,6 +341,7 @@ mcu_mdio_pins_default: mcu-mdio-default-pins { J721S2_WKUP_IOPAD(0x034, PIN_OUTPUT, 0) /* (A21) MCU_MDIO0_MDC */ J721S2_WKUP_IOPAD(0x030, PIN_INPUT, 0) /* (A22) MCU_MDIO0_MDIO */ >; + bootph-all; }; =20 mcu_mcan0_pins_default: mcu-mcan0-default-pins { @@ -615,6 +617,7 @@ &mcu_cpsw { &davinci_mdio { phy0: ethernet-phy@0 { reg =3D <0>; + bootph-all; ti,rx-internal-delay =3D ; ti,fifo-depth =3D ; ti,min-output-impedance; diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi b/arch/arm64/= boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi index bc31266126d0..29cd4b1ffbbf 100644 --- a/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi +++ b/arch/arm64/boot/dts/ti/k3-j721s2-mcu-wakeup.dtsi @@ -154,12 +154,14 @@ mcu_conf: bus@40f00000 { cpsw_mac_syscon: ethernet-mac-syscon@200 { compatible =3D "ti,am62p-cpsw-mac-efuse", "syscon"; reg =3D <0x200 0x8>; + bootph-all; }; =20 phy_gmii_sel: phy@4040 { compatible =3D "ti,am654-phy-gmii-sel"; reg =3D <0x4040 0x4>; #phy-cells =3D <1>; + bootph-all; }; =20 }; @@ -538,6 +540,7 @@ mcu_cpsw: ethernet@46000000 { clocks =3D <&k3_clks 29 28>; clock-names =3D "fck"; power-domains =3D <&k3_pds 29 TI_SCI_PD_EXCLUSIVE>; + bootph-all; =20 dmas =3D <&mcu_udmap 0xf000>, <&mcu_udmap 0xf001>, @@ -562,6 +565,7 @@ cpsw_port1: port@1 { label =3D "port1"; ti,syscon-efuse =3D <&cpsw_mac_syscon 0x0>; phys =3D <&phy_gmii_sel 1>; + bootph-all; }; }; =20 --=20 2.34.1