From nobody Wed Feb 11 07:00:53 2026 Received: from mgamail.intel.com (mgamail.intel.com [192.198.163.7]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 58F4A1E9915 for ; Sun, 2 Mar 2025 14:21:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=192.198.163.7 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740925272; cv=none; b=DMSno5bBaIUmTdtg04ukLmd/PCoCOj7JE7aGhELC069b4Ac71KmyBuY9kGuUvswZfguMVNc2RmSChBSTvIK/5QDGxhDLWLDDB+75fRB9sJrm6wMxf0CN7C1n71hk8d+bdBiyaSCWpdrxsu7oa+LS+rBTWMJRkgCoRZfPcYobF+I= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740925272; c=relaxed/simple; bh=02tjDKQNWeXHFLJTCMQ3g4lvV4tJ61jI02p0lATS/lk=; h=From:To:Cc:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version; b=Qd9sio+lx16rhjbVj0XOsBs0VTXMDdlmzLA/JYrXdgOxY+LJJ2BYjHgcivUVK4vI4YRoj/hxlOe7e758Kls9vyxvO9ESqUCoWekPsUEXPgr8f+Sb1A3PfTLWAdXiSDS0moCQnRtbmYQwQY0lKHmxeBkemjJgP5EbJF7sqobvEOA= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com; spf=pass smtp.mailfrom=intel.com; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b=Nzy70OJh; arc=none smtp.client-ip=192.198.163.7 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=intel.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=intel.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=intel.com header.i=@intel.com header.b="Nzy70OJh" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1740925271; x=1772461271; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=02tjDKQNWeXHFLJTCMQ3g4lvV4tJ61jI02p0lATS/lk=; b=Nzy70OJh/1SAabq2R2YDIz/CwghB+RENHg5oLC6EnsrQ6Q0L69eOB7LU Is2kHUguLbxHxoPM15QWmP7QxJ0ASNg351zCu0Wd15fYJOpp1zfqurSV1 BWPpApFc5OJ1zXngJI33rf4ko6xXybg+9JOMa+hP5QjG0bxixfILeOeJH QPQLeSD/nD57zxPdpZn5MrdKSImFSvXtwt4YDoA8Zk5pecohsgcpTLw6H nYRweASDEThOoZig/MfDDdNNbMi2Er70G/+tsRsbuA95JnBgfbr2sBK27 AxDPJVpN9zgwNldfg5dGBv6ssIN2G2+vh63xsye34QItyO5fQHbBbypVf A==; X-CSE-ConnectionGUID: 4JtuLfOxSUC+jQz0JMmfow== X-CSE-MsgGUID: Fx9vETC3TZm0pE1Wx4cJFQ== X-IronPort-AV: E=McAfee;i="6700,10204,11361"; a="67176449" X-IronPort-AV: E=Sophos;i="6.13,327,1732608000"; d="scan'208";a="67176449" Received: from orviesa003.jf.intel.com ([10.64.159.143]) by fmvoesa101.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2025 06:21:11 -0800 X-CSE-ConnectionGUID: Nr5kF5eDQUKNGsO7hr0BIw== X-CSE-MsgGUID: Y8Pxrq6mRayadUVDiwWYng== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.13,327,1732608000"; d="scan'208";a="122737353" Received: from sannilnx-dsk.jer.intel.com ([10.12.231.107]) by ORVIESA003-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 02 Mar 2025 06:21:05 -0800 From: Alexander Usyskin To: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Lucas De Marchi , =?UTF-8?q?Thomas=20Hellstr=C3=B6m?= , Rodrigo Vivi , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jani Nikula , Joonas Lahtinen , Tvrtko Ursulin , Karthik Poosa Cc: Reuven Abliyev , Oren Weil , linux-mtd@lists.infradead.org, dri-devel@lists.freedesktop.org, intel-gfx@lists.freedesktop.org, linux-kernel@vger.kernel.org, Alexander Usyskin Subject: [PATCH v6 06/11] mtd: intel-dg: align 64bit read and write Date: Sun, 2 Mar 2025 16:09:16 +0200 Message-ID: <20250302140921.504304-7-alexander.usyskin@intel.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250302140921.504304-1-alexander.usyskin@intel.com> References: <20250302140921.504304-1-alexander.usyskin@intel.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" GSC NVM controller HW errors on quad access overlapping 1K border. Align 64bit read and write to avoid readq/writeq over 1K border. Acked-by: Miquel Raynal Signed-off-by: Alexander Usyskin --- drivers/mtd/devices/mtd_intel_dg.c | 35 ++++++++++++++++++++++++++++++ 1 file changed, 35 insertions(+) diff --git a/drivers/mtd/devices/mtd_intel_dg.c b/drivers/mtd/devices/mtd_i= ntel_dg.c index 4023f2ebc344..3535f7b64429 100644 --- a/drivers/mtd/devices/mtd_intel_dg.c +++ b/drivers/mtd/devices/mtd_intel_dg.c @@ -238,6 +238,24 @@ static ssize_t idg_write(struct intel_dg_nvm *nvm, u8 = region, len_s -=3D to_shift; } =20 + if (!IS_ALIGNED(to, sizeof(u64)) && + ((to ^ (to + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data; + + memcpy(&data, &buf[0], sizeof(u32)); + idg_nvm_write32(nvm, to, data); + if (idg_nvm_error(nvm)) + return -EIO; + buf +=3D sizeof(u32); + to +=3D sizeof(u32); + len_s -=3D sizeof(u32); + } + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); for (i =3D 0; i < len8; i +=3D sizeof(u64)) { u64 data; @@ -295,6 +313,23 @@ static ssize_t idg_read(struct intel_dg_nvm *nvm, u8 r= egion, from +=3D from_shift; } =20 + if (!IS_ALIGNED(from, sizeof(u64)) && + ((from ^ (from + len_s)) & GENMASK(31, 10))) { + /* + * Workaround reads/writes across 1k-aligned addresses + * (start u32 before 1k, end u32 after) + * as this fails on hardware. + */ + u32 data =3D idg_nvm_read32(nvm, from); + + if (idg_nvm_error(nvm)) + return -EIO; + memcpy(&buf[0], &data, sizeof(data)); + len_s -=3D sizeof(u32); + buf +=3D sizeof(u32); + from +=3D sizeof(u32); + } + len8 =3D ALIGN_DOWN(len_s, sizeof(u64)); for (i =3D 0; i < len8; i +=3D sizeof(u64)) { u64 data =3D idg_nvm_read64(nvm, from + i); --=20 2.43.0