From nobody Mon Feb 9 17:04:58 2026 Received: from mail-lf1-f47.google.com (mail-lf1-f47.google.com [209.85.167.47]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 4A2291D88C3 for ; Sat, 1 Mar 2025 09:25:11 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=209.85.167.47 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740821113; cv=none; b=fvu+keieizrmuolc60vIY63kZ0oQvOPgC6IXfKSK3BqHioVpmfISW7NqxzevPClw4qpVcfKVKDDTVQYqLOJc3UtAUWPWsdDUYriZ9XtmiACqhAbNEFtyGiQ9JLbHcnT2ZvWroMOA8t/7vqxAujVmkRGWKrMTxjXh/QBP6++NWEk= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740821113; c=relaxed/simple; bh=FGk4O1VHJ/AALXi9JU8E7/AS9MUo+YPgs+S6pZa0Mrg=; h=From:Date:Subject:MIME-Version:Content-Type:Message-Id:References: In-Reply-To:To:Cc; b=s9mMsOYLbVkNKbKqDKcQxFPvwESrPO4YEDtNJ98bhPPHXHmd6ZMB3splQ+5rS55WYDJbsD+bG94g9KoH4AKv7dgF1aY5CES11evlN964xZtv0UPVpx5QwjCr+ahSE9kmKnQJMNTPYjAIarpycZNqkY4wC1Tz7kgrkek+Rla8pKQ= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org; spf=pass smtp.mailfrom=linaro.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b=RaqkO3Cn; arc=none smtp.client-ip=209.85.167.47 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=linaro.org Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=linaro.org Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="RaqkO3Cn" Received: by mail-lf1-f47.google.com with SMTP id 2adb3069b0e04-547bcef2f96so3126230e87.1 for ; Sat, 01 Mar 2025 01:25:10 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; t=1740821109; x=1741425909; darn=vger.kernel.org; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:from:to:cc:subject:date:message-id :reply-to; bh=0S3CqHmaZKk/knnnYKsC2gVCXeH/ZZG8lvfqN607uo8=; b=RaqkO3CnpKN4K4zuizDWlpYM0J/WGH1kktjt6tmVgYzXTiTPgdHz4nKKl6C5ybU2P2 /3EnILEiNn1wK05TYQJNW6xoqihEc4Uqh6dLhSc8/JFp4ATTA5/zgJ/pa2gD+bvzVTml 4ccedfugTt0XngbPeRkHBX2Brxmi6mQX6GbqQ/6x055yLLYJg6uh6ZRPYBaelYlCuQ9M NsfrfBmUUxDKvuS3NKPxHO/ggZey7VTf+NZBNo3xmUffEaBRD1RvtqqWtH1kyHAa2Cg5 JgHDZzl2gzgjrZYC6CxY8777NHQ0zv6wLHNkv77FjlIyBluxpKXmMlKip9t9QpH7ST9F glnQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1740821109; x=1741425909; h=cc:to:in-reply-to:references:message-id:content-transfer-encoding :mime-version:subject:date:from:x-gm-message-state:from:to:cc :subject:date:message-id:reply-to; bh=0S3CqHmaZKk/knnnYKsC2gVCXeH/ZZG8lvfqN607uo8=; b=fFKR/UzABsUNZi6GiZjY3/GQ+oEhhKwHawMMHRsuL2ObJRROU8FC61kpUp4RWCZ68H 38KuyOrc1hE3JUh/w2dH1QZkP1hfHYSJaoA0kYBlIDBXz02QLoNG0ctQVY3GXcCReJfl CgUGCHCqAZzGHxbGWcWLed0kFMm0TxpDLZf9MwGPOg569PRcM2RjtuD/kRQF3qPwa9ya e/PQLve+xYqHnkQqsMXdyZcUbo18rXkd2do592/RHSITnSNQlKnuMWqgYdz212BfpSbC l7c8gmGqJhC8thP9me8EXZIhWCUG7Qm07RDScXsf66b4IiOTkHK2rZONnMNSv3U7i420 z2Hg== X-Forwarded-Encrypted: i=1; AJvYcCV+P6hZta8el//tw0ox952f+dL45j7FntzK5Swhvd4xZoBOGrP31PzkYU/WbnY1VpcbwJyeoltvtvPc29A=@vger.kernel.org X-Gm-Message-State: AOJu0YzXOZq8vVbA1m48cdHrxKC6Mz7MCHLlE0IxaYssQr7xRDAbcGSf YzX/7UfRNjW+DKoqDX6yzDLA1f4+q/WG4H5ur42aOlrGO5fjzsg4OcWc9sFOmXU= X-Gm-Gg: ASbGnctZaFtMFiJ+AkzDxAf5IecpLxVBF0YeZZGsN6JBOBwiBfR7mePqa5C9z8di31v 0LG82yPFCbi0qEQQRpPlugVXI64QEKIbRJshhJ6Dt7WIhBX1Y0U/Kr6GuVh4k99nSHWECltikLu huFmg0VRLW1ydjzxKlsc67c/RNPwu8/9knpyylp1uL3AABfF3UHfjqRnxkvgvxo+kjMC1GyUu1p 3LLGnqGCwA418IsuRE+4lX2ic/VDnuNecNpAOPOexBSmI/8DKdp1OTXCoMCkcxo9VoRq9rbmEla sWjUdlCAFs3ysuxAJiM9gZGEGQURwQgnWn2k7E0JyYy+dc4eKeH7 X-Google-Smtp-Source: AGHT+IH/J66JM3jXcQg4Hm2VzetV+is+xE4RZX/iaVVXbntv7XIHbZKu0lKbD6OmxDUwOs9xArkiDg== X-Received: by 2002:a05:6512:b88:b0:549:5b54:2c68 with SMTP id 2adb3069b0e04-5495b54357bmr396446e87.22.1740821109321; Sat, 01 Mar 2025 01:25:09 -0800 (PST) Received: from umbar.lan ([192.130.178.90]) by smtp.gmail.com with ESMTPSA id 2adb3069b0e04-5494417432csm738406e87.52.2025.03.01.01.25.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 01 Mar 2025 01:25:08 -0800 (PST) From: Dmitry Baryshkov Date: Sat, 01 Mar 2025 11:24:57 +0200 Subject: [PATCH v2 4/5] drm/msm/dpu: drop TE2 definitions Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Message-Id: <20250301-dpu-fix-catalog-v2-4-498271be8b50@linaro.org> References: <20250301-dpu-fix-catalog-v2-0-498271be8b50@linaro.org> In-Reply-To: <20250301-dpu-fix-catalog-v2-0-498271be8b50@linaro.org> To: Rob Clark , Abhinav Kumar , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , =?utf-8?q?Barnab=C3=A1s_Cz=C3=A9m=C3=A1n?= , Konrad Dybcio Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org X-Mailer: b4 0.14.2 X-Developer-Signature: v=1; a=openpgp-sha256; l=8773; i=dmitry.baryshkov@linaro.org; h=from:subject:message-id; bh=FGk4O1VHJ/AALXi9JU8E7/AS9MUo+YPgs+S6pZa0Mrg=; b=owEBbQGS/pANAwAKAYs8ij4CKSjVAcsmYgBnwtJoUqN4knEcdJD0ev8uxf4olTQ0qPmspUIZZ dF+m4E+3HuJATMEAAEKAB0WIQRMcISVXLJjVvC4lX+LPIo+Aiko1QUCZ8LSaAAKCRCLPIo+Aiko 1WZJB/0QBY82ZFrTQlyyCk4Fj81ctmok/eKg87Go3jbdS/MB3AXf0GlaRXlRL1cfEtEPsCDnV6R j5aRI23DxgzeZf6iBBgrUfsDWiWenGEC1O/MxgcR7uphZmn14/D/1D3MOZeZ+NnQtuk1W0/N0EX EkWd7X5Jc2Qimj9WSGRIeoPt8EZEDZy4V/ojdhJAJxytHbR5Sh4lYUhAjYnVxuReDT6l6nCySDr quWpPjOOb5raORp7puz5D3o2OdE+ChOhgFPv95xNijDrI7IfDsM109K5HNOhP107Sv7qH2LD1lI 8rEhgiM3Xc6DzRL16MB3GnydaXEu/7NGgvzvIOWTYW+aWvLY X-Developer-Key: i=dmitry.baryshkov@linaro.org; a=openpgp; fpr=8F88381DD5C873E4AE487DA5199BF1243632046A Neither DPU driver nor vendor SDE driver do not use TE2 definitions (and, in case of SDE driver, never did). Semantics of the TE2 feature bit and .te2 sblk are not completely clear. Drop these bits from the catalog with the possibility of reintroducing them later if we need to support ppsplit. Signed-off-by: Dmitry Baryshkov Reviewed-by: Abhinav Kumar --- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h | 4 ++-- drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h | 8 ++++---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 17 -------------= ---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 6 +----- 7 files changed, 19 insertions(+), 40 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h index 491f6f5827d151011dd3f74bef2a4b8bf69591ab..400739295de5aa509ed3a7f6c82= ef45dda21c47f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_1_7_msm8996.h @@ -181,15 +181,15 @@ static const struct dpu_pingpong_cfg msm8996_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_TE2_MASK, - .sblk =3D &msm8996_pp_sblk_te, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_MSM8996_TE2_MASK, - .sblk =3D &msm8996_pp_sblk_te, + .features =3D PINGPONG_MSM8996_MASK, + .sblk =3D &msm8996_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h b/driv= ers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h index 64c94e919a69804599916404dff59fa4a6ac6cff..a253e0fdc556b57aa3752b81b80= 3e84550ba146e 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_0_msm8998.h @@ -170,15 +170,15 @@ static const struct dpu_pingpong_cfg msm8998_pp[] =3D= { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, - .sblk =3D &sdm845_pp_sblk_te, + .features =3D PINGPONG_SDM845_MASK, + .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, - .sblk =3D &sdm845_pp_sblk_te, + .features =3D PINGPONG_SDM845_MASK, + .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h index 424815e7fb7dd858448bd41b5368b729373035f8..4464d4568aba0577a6f957bbd5d= 8d1c73f68b403 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_2_sdm660.h @@ -141,15 +141,15 @@ static const struct dpu_pingpong_cfg sdm660_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, - .sblk =3D &sdm845_pp_sblk_te, + .features =3D PINGPONG_SDM845_MASK, + .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, - .sblk =3D &sdm845_pp_sblk_te, + .features =3D PINGPONG_SDM845_MASK, + .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h index df01227fc36468f4945c03e767e1409ea4fc0896..3aed9aa4c533f167ece7b4a5eb8= 4fe49c4929df5 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_3_3_sdm630.h @@ -115,8 +115,8 @@ static const struct dpu_pingpong_cfg sdm630_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, - .sblk =3D &sdm845_pp_sblk_te, + .features =3D PINGPONG_SDM845_MASK, + .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h b/drive= rs/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h index 72bd4f7e9e504c771d999dcf6277fceb169cffca..c122782ec8bd7e5ad68729c8c12= bc8ccd0cfe0c2 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_4_0_sdm845.h @@ -194,15 +194,15 @@ static const struct dpu_pingpong_cfg sdm845_pp[] =3D { { .name =3D "pingpong_0", .id =3D PINGPONG_0, .base =3D 0x70000, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, - .sblk =3D &sdm845_pp_sblk_te, + .features =3D PINGPONG_SDM845_MASK, + .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 8), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), }, { .name =3D "pingpong_1", .id =3D PINGPONG_1, .base =3D 0x70800, .len =3D 0xd4, - .features =3D PINGPONG_SDM845_TE2_MASK, - .sblk =3D &sdm845_pp_sblk_te, + .features =3D PINGPONG_SDM845_MASK, + .sblk =3D &sdm845_pp_sblk, .intr_done =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 9), .intr_rdptr =3D DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, { diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.c index 0b342c043875f3329a9f71c5e751b2244f9f5ef7..b67578738dffe1ac83530d93eb0= e631f21384efc 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -98,15 +98,9 @@ #define PINGPONG_MSM8996_MASK \ (BIT(DPU_PINGPONG_DSC)) =20 -#define PINGPONG_MSM8996_TE2_MASK \ - (PINGPONG_MSM8996_MASK | BIT(DPU_PINGPONG_TE2)) - #define PINGPONG_SDM845_MASK \ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 -#define PINGPONG_SDM845_TE2_MASK \ - (PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2)) - #define PINGPONG_SM8150_MASK \ (BIT(DPU_PINGPONG_DITHER) | BIT(DPU_PINGPONG_DSC)) =20 @@ -465,22 +459,11 @@ static const struct dpu_dspp_sub_blks sdm845_dspp_sbl= k =3D { /************************************************************* * PINGPONG sub blocks config *************************************************************/ -static const struct dpu_pingpong_sub_blks msm8996_pp_sblk_te =3D { - .te2 =3D {.name =3D "te2", .base =3D 0x2000, .len =3D 0x0, - .version =3D 0x1}, -}; =20 static const struct dpu_pingpong_sub_blks msm8996_pp_sblk =3D { /* No dither block */ }; =20 -static const struct dpu_pingpong_sub_blks sdm845_pp_sblk_te =3D { - .te2 =3D {.name =3D "te2", .base =3D 0x2000, .len =3D 0x0, - .version =3D 0x1}, - .dither =3D {.name =3D "dither", .base =3D 0x30e0, - .len =3D 0x20, .version =3D 0x10000}, -}; - static const struct dpu_pingpong_sub_blks sdm845_pp_sblk =3D { .dither =3D {.name =3D "dither", .base =3D 0x30e0, .len =3D 0x20, .version =3D 0x10000}, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/d= rm/msm/disp/dpu1/dpu_hw_catalog.h index 4cea19e1a20380c56ae014f2d33a6884a72e0ca0..07b50e23ee954b96e7e6bd684dc= 12823f99d630b 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -115,7 +115,6 @@ enum { =20 /** * PINGPONG sub-blocks - * @DPU_PINGPONG_TE2 Additional tear check block for split pipes * @DPU_PINGPONG_SPLIT PP block supports split fifo * @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo * @DPU_PINGPONG_DITHER Dither blocks @@ -123,8 +122,7 @@ enum { * @DPU_PINGPONG_MAX */ enum { - DPU_PINGPONG_TE2 =3D 0x1, - DPU_PINGPONG_SPLIT, + DPU_PINGPONG_SPLIT =3D 0x1, DPU_PINGPONG_SLAVE, DPU_PINGPONG_DITHER, DPU_PINGPONG_DSC, @@ -404,8 +402,6 @@ struct dpu_dspp_sub_blks { }; =20 struct dpu_pingpong_sub_blks { - struct dpu_pp_blk te; - struct dpu_pp_blk te2; struct dpu_pp_blk dither; }; =20 --=20 2.39.5