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Fri, 28 Feb 2025 02:40:06 -0800 (PST) From: Stefan Eichenberger To: vkoul@kernel.org, kishon@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, p.zabel@pengutronix.de, tharvey@gateworks.com, hongxing.zhu@nxp.com, francesco.dolcini@toradex.com Cc: linux-phy@lists.infradead.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan Eichenberger Subject: [PATCH v1 1/2] phy: freescale: imx8m-pcie: cleanup reset logic Date: Fri, 28 Feb 2025 11:38:33 +0100 Message-ID: <20250228103959.47419-2-eichest@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250228103959.47419-1-eichest@gmail.com> References: <20250228103959.47419-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Eichenberger Remove the switch statement and base perst release on whether it is found in the device tree. The probe function fails without the reset property, making it mandatory. Therefore, always release reset independent of the variant. This does not change the behavior of the driver but reduces driver complexity and allows for easier future modifications. Signed-off-by: Stefan Eichenberger --- drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 12 ++++-------- 1 file changed, 4 insertions(+), 8 deletions(-) diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/frees= cale/phy-fsl-imx8m-pcie.c index e98361dcdeadf..00f957a42d9dc 100644 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c @@ -141,15 +141,11 @@ static int imx8_pcie_phy_power_on(struct phy *phy) IMX8MM_GPR_PCIE_REF_CLK_PLL); usleep_range(100, 200); =20 - switch (imx8_phy->drvdata->variant) { - case IMX8MP: + if (imx8_phy->perst) reset_control_deassert(imx8_phy->perst); - fallthrough; - case IMX8MM: - reset_control_deassert(imx8_phy->reset); - usleep_range(200, 500); - break; - } + + reset_control_deassert(imx8_phy->reset); + usleep_range(200, 500); =20 /* Do the PHY common block reset */ regmap_update_bits(imx8_phy->iomuxc_gpr, IOMUXC_GPR14, --=20 2.45.2 From nobody Sat Feb 7 20:05:09 2026 Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 38C4C25F7A6; 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Fri, 28 Feb 2025 02:40:07 -0800 (PST) Received: from eichest-laptop.toradex.int ([2a02:168:af72:0:31d5:4145:8035:cb68]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-43b73703caesm52078855e9.12.2025.02.28.02.40.06 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 28 Feb 2025 02:40:06 -0800 (PST) From: Stefan Eichenberger To: vkoul@kernel.org, kishon@kernel.org, shawnguo@kernel.org, s.hauer@pengutronix.de, kernel@pengutronix.de, festevam@gmail.com, p.zabel@pengutronix.de, tharvey@gateworks.com, hongxing.zhu@nxp.com, francesco.dolcini@toradex.com Cc: linux-phy@lists.infradead.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Stefan Eichenberger , stable@vger.kernel.org Subject: [PATCH v1 2/2] phy: freescale: imx8m-pcie: assert phy reset and perst in power off Date: Fri, 28 Feb 2025 11:38:34 +0100 Message-ID: <20250228103959.47419-3-eichest@gmail.com> X-Mailer: git-send-email 2.45.2 In-Reply-To: <20250228103959.47419-1-eichest@gmail.com> References: <20250228103959.47419-1-eichest@gmail.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" From: Stefan Eichenberger Ensure the PHY reset and perst is asserted during power-off to guarantee it is in a reset state upon repeated power-on calls. This resolves an issue where the PHY may not properly initialize during subsequent power-on cycles. Power-on will deassert the reset at the appropriate time after tuning the PHY parameters. During suspend/resume cycles, we observed that the PHY PLL failed to lock during resume when the CPU temperature increased from 65C to 75C. The observed errors were: phy phy-32f00000.pcie-phy.3: phy poweron failed --> -110 imx6q-pcie 33800000.pcie: waiting for PHY ready timeout! imx6q-pcie 33800000.pcie: PM: dpm_run_callback(): genpd_resume_noirq+0x0/= 0x80 returns -110 imx6q-pcie 33800000.pcie: PM: failed to resume noirq: error -110 This resulted in a complete CPU freeze, which is resolved by ensuring the PHY is in reset during power-on, thus preventing PHY PLL failures. Cc: stable@vger.kernel.org Fixes: 1aa97b002258 ("phy: freescale: pcie: Initialize the imx8 pcie standa= lone phy driver") Signed-off-by: Stefan Eichenberger --- drivers/phy/freescale/phy-fsl-imx8m-pcie.c | 12 ++++++++++++ 1 file changed, 12 insertions(+) diff --git a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c b/drivers/phy/frees= cale/phy-fsl-imx8m-pcie.c index 00f957a42d9dc..36bef416618de 100644 --- a/drivers/phy/freescale/phy-fsl-imx8m-pcie.c +++ b/drivers/phy/freescale/phy-fsl-imx8m-pcie.c @@ -158,6 +158,17 @@ static int imx8_pcie_phy_power_on(struct phy *phy) return ret; } =20 +static int imx8_pcie_phy_power_off(struct phy *phy) +{ + struct imx8_pcie_phy *imx8_phy =3D phy_get_drvdata(phy); + + reset_control_assert(imx8_phy->reset); + if (imx8_phy->perst) + reset_control_assert(imx8_phy->perst); + + return 0; +} + static int imx8_pcie_phy_init(struct phy *phy) { struct imx8_pcie_phy *imx8_phy =3D phy_get_drvdata(phy); @@ -178,6 +189,7 @@ static const struct phy_ops imx8_pcie_phy_ops =3D { .init =3D imx8_pcie_phy_init, .exit =3D imx8_pcie_phy_exit, .power_on =3D imx8_pcie_phy_power_on, + .power_off =3D imx8_pcie_phy_power_off, .owner =3D THIS_MODULE, }; =20 --=20 2.45.2