From nobody Thu Mar 13 22:49:01 2025 Received: from mx0b-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6E9DD26E951; Thu, 27 Feb 2025 19:26:02 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740684365; cv=none; b=YvdUj2u9U1Eo5H7bwd1LdkD718cebHWGBQhqI678VrMe/xJb+BLy6EJRE7JAkXcI5EA2csUxv/fmpIuTX5U3pWH3yAl0WHRLSh/AdY2OkHIYrXHM3sgh42n7cKY3FILOlIpOGCkV0BGfRqYyG2S4/vK5wRV8FwiBdZ+wuxxS4Ms= ARC-Message-Signature: i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1740684365; c=relaxed/simple; bh=jfhyCIT1u2l4MOfw5bZcxLsXuzvMXXJhDxKZOGfQBgY=; h=From:To:CC:Subject:Date:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=L4ioKsr8ErMkzajAff7FjcKVygTfwijcNfbQmMPNix66m/i1WLnjY5vA2LHmus79FaGhVzuW/Ke9/w0Uroco1YfdefSYEcoMDapwxFGNmRVQqHyaIqMUNLrpAzsiCUg/uQfnCznkM76vRaRKt44JZ6CIvzvJQX4ve/C+XwMEIUk= ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com; spf=pass smtp.mailfrom=marvell.com; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b=VnIeBX4w; arc=none smtp.client-ip=67.231.148.174 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=marvell.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=marvell.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=marvell.com header.i=@marvell.com header.b="VnIeBX4w" Received: from pps.filterd (m0045849.ppops.net [127.0.0.1]) by mx0a-0016f401.pphosted.com (8.18.1.2/8.18.1.2) with ESMTP id 51RFdiZ8015307; Thu, 27 Feb 2025 11:25:40 -0800 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=marvell.com; h= cc:content-transfer-encoding:content-type:date:from:in-reply-to :message-id:mime-version:references:subject:to; s=pfpt0220; bh=D YPf7pOW+Hj9D8sJ8EeNXB6OJG/17TDHY4ejPKDvTh8=; b=VnIeBX4whSckZyxXO cw7vWLHgxdRIvUD32YI3HhQAABY0MrYuFr9EQuHvZnUCB6PVIRs3IhMuUxKvZkOu VAPm/OiK+vERfnNA22BHMcWObW4faBWHgB1RIwwhQYEtRmF2l7YcKzWTiXBOVqzi E5mZ14GqfbVTWxe97HxyP2plimYYHpqf+1VThD5NaXo5BuRrwtqT7M1qDdr8YKyM qNKOpb9V00gZRYO5jIfMujlIintq4Vt63AKNFKGxtGZhwpCCIm6IsGLRi7ALvT95 Z40magpFpbLip4KHGbQaELg/VamJ3ROjbtB8V+b2j4s6+up1rZRzTyBMG6XHdZoF o/ZlA== Received: from dc6wp-exch02.marvell.com ([4.21.29.225]) by mx0a-0016f401.pphosted.com (PPS) with ESMTPS id 452tvrrhfk-1 (version=TLSv1.2 cipher=ECDHE-RSA-AES256-GCM-SHA384 bits=256 verify=NOT); Thu, 27 Feb 2025 11:25:39 -0800 (PST) Received: from DC6WP-EXCH02.marvell.com (10.76.176.209) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 27 Feb 2025 11:25:38 -0800 Received: from maili.marvell.com (10.69.176.80) by DC6WP-EXCH02.marvell.com (10.76.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 27 Feb 2025 11:25:38 -0800 Received: from wd-ubuntu-24-04.marvell.com (wd-ubuntu-24-04.marvell.com [10.111.132.113]) by maili.marvell.com (Postfix) with ESMTP id 3D28B3F707B; Thu, 27 Feb 2025 11:25:38 -0800 (PST) From: Wilson Ding To: , , CC: , , , , , , , , , Wilson Ding Subject: [PATCH v3 1/3] dt-bindings: reset: Add Armada8K reset controller Date: Thu, 27 Feb 2025 11:25:34 -0800 Message-ID: <20250227192536.2426490-2-dingwei@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227192536.2426490-1-dingwei@marvell.com> References: <20250227192536.2426490-1-dingwei@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-GUID: Y680ExBWjBukpnyqiqhf4B8U9NOTk1FL X-Authority-Analysis: v=2.4 cv=COHQXQrD c=1 sm=1 tr=0 ts=67c0bc33 cx=c_pps a=gIfcoYsirJbf48DBMSPrZA==:117 a=gIfcoYsirJbf48DBMSPrZA==:17 a=T2h4t0Lz3GQA:10 a=gEfo2CItAAAA:8 a=M5GUcnROAAAA:8 a=Xx2rH3x8VMMp6ogthC8A:9 a=RVmHIydaz68A:10 a=sptkURWiP4Gy88Gu7hUp:22 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-ORIG-GUID: Y680ExBWjBukpnyqiqhf4B8U9NOTk1FL X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-27_07,2025-02-27_01,2024-11-22_01 Content-Type: text/plain; charset="utf-8" Add device-tree binding documentation for the Armada8K reset driver and create the new head file for the reset line index definitions. Signed-off-by: Wilson Ding --- .../reset/marvell,armada8k-reset.yaml | 48 +++++++++++++++++++ .../reset/marvell,armada8k-reset.h | 27 +++++++++++ 2 files changed, 75 insertions(+) create mode 100644 Documentation/devicetree/bindings/reset/marvell,armada8= k-reset.yaml create mode 100644 include/dt-bindings/reset/marvell,armada8k-reset.h diff --git a/Documentation/devicetree/bindings/reset/marvell,armada8k-reset= .yaml b/Documentation/devicetree/bindings/reset/marvell,armada8k-reset.yaml new file mode 100644 index 000000000000..9af352f528de --- /dev/null +++ b/Documentation/devicetree/bindings/reset/marvell,armada8k-reset.yaml @@ -0,0 +1,48 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +# Copyright 2025 Wilson Ding +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/reset/marvell,armada8k-reset.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Marvell Armada8K reset controller + +maintainers: + - Wilson Ding + +description: The reset controller node must be a sub-node of the system + controller node on Armada7K/8K or CN913x SoCs. + +properties: + compatible: + const: marvell,armada8k-reset + + reg: + description: + The register offset (to syscon register address) and size + maxItems: 1 + + "#reset-cells": + const: 1 + +required: + - compatible + - reg + - "#reset-cells" + +additionalProperties: false + +examples: + - | + syscon0: system-controller@440000 { + compatible =3D "syscon", "simple-mfd"; + reg =3D <0x440000 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <1>; + + swrst: reset-controller@268 { + compatible =3D "marvell,armada8k-reset"; + reg =3D <0x268 0x4>; + #reset-cells =3D <1>; + }; + }; diff --git a/include/dt-bindings/reset/marvell,armada8k-reset.h b/include/d= t-bindings/reset/marvell,armada8k-reset.h new file mode 100644 index 000000000000..18c6f4f761e2 --- /dev/null +++ b/include/dt-bindings/reset/marvell,armada8k-reset.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */ +/* + * Copyright (c) 2025, Marvell. All Rights Reserved. + */ + +#ifndef _DT_BINDINGS_MARVELL_ARMADA8K_RESET_H_ +#define _DT_BINDINGS_MARVELL_ARMADA8K_RESET_H_ + +#define CP110_RESET_AUDIO 0 +#define CP110_RESET_TDM 1 +#define CP110_RESET_ICU 2 +#define CP110_RESET_PP2 3 +#define CP110_RESET_SDIO 4 +#define CP110_RESET_XOR1 7 +#define CP110_RESET_XOR0 8 +#define CP110_RESET_PCIE0_X1 11 +#define CP110_RESET_PCIE1_X1 12 +#define CP110_RESET_PCIE_X4 13 +#define CP110_RESET_SATA 15 +#define CP110_RESET_USB3_HOST0 22 +#define CP110_RESET_USB3_HOST1 23 +#define CP110_RESET_USB3_DEV 24 +#define CP110_RESET_EIP150F 25 +#define CP110_RESET_EIP197 26 +#define CP110_RESET_MSS 29 + +#endif /* _DT_BINDINGS_MARVELL_ARMADA8K_RESET_H_ */ --=20 2.43.0 From nobody Thu Mar 13 22:49:01 2025 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DDB4826E950; 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Thu, 27 Feb 2025 11:25:39 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 27 Feb 2025 11:25:38 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 27 Feb 2025 11:25:38 -0800 Received: from wd-ubuntu-24-04.marvell.com (wd-ubuntu-24-04.marvell.com [10.111.132.113]) by maili.marvell.com (Postfix) with ESMTP id 5B0F53F707D; Thu, 27 Feb 2025 11:25:38 -0800 (PST) From: Wilson Ding To: , , CC: , , , , , , , , , Wilson Ding Subject: [PATCH v3 2/3] reset: Add support for Armada8K reset controller Date: Thu, 27 Feb 2025 11:25:35 -0800 Message-ID: <20250227192536.2426490-3-dingwei@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227192536.2426490-1-dingwei@marvell.com> References: <20250227192536.2426490-1-dingwei@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: YBzRlG9k6QrEIuhHyOm14XtK_IaCnYW0 X-Authority-Analysis: v=2.4 cv=UIYnHDfy c=1 sm=1 tr=0 ts=67c0bc33 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=T2h4t0Lz3GQA:10 a=M5GUcnROAAAA:8 a=uP1ucDPQAAAA:8 a=TCups3AGXvnK9ebHqNkA:9 a=OBjm3rFKGHvpk9ecZwUJ:22 a=9a9ggB8z3XFZH39hjkD6:22 X-Proofpoint-GUID: YBzRlG9k6QrEIuhHyOm14XtK_IaCnYW0 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-27_07,2025-02-27_01,2024-11-22_01 Content-Type: text/plain; charset="utf-8" Armada8K has one register for unit soft-reset configuration within the system controller register area. This patch created a new driver based on the simple-reset driver to support the reset controller of a SYSCON device. Signed-off-by: Wilson Ding --- drivers/reset/Kconfig | 12 ++ drivers/reset/Makefile | 1 + drivers/reset/reset-simple-syscon.c | 188 ++++++++++++++++++++++++++++ include/linux/reset/reset-simple.h | 3 + 4 files changed, 204 insertions(+) create mode 100644 drivers/reset/reset-simple-syscon.c diff --git a/drivers/reset/Kconfig b/drivers/reset/Kconfig index 5b3abb6db248..e98b22195317 100644 --- a/drivers/reset/Kconfig +++ b/drivers/reset/Kconfig @@ -248,6 +248,18 @@ config RESET_SIMPLE - SiFive FU740 SoCs - Sophgo SoCs =20 +config RESET_SIMPLE_SYSCON + bool "Simple SYSCON Reset Controller Driver" if COMPILE_TEST || EXPERT + depends on HAS_IOMEM + select MFD_SYSCON + help + This enables a simple reset controller driver for reset lines that + that can be asserted and deasserted by toggling bits in a contiguous, + exclusive register space. + + Currently this driver supports: + - Marvell Armada8K SoCs + config RESET_SOCFPGA bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFP= GA) default ARM && ARCH_INTEL_SOCFPGA diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile index 677c4d1e2632..c43642fe4d9b 100644 --- a/drivers/reset/Makefile +++ b/drivers/reset/Makefile @@ -32,6 +32,7 @@ obj-$(CONFIG_RESET_RASPBERRYPI) +=3D reset-raspberrypi.o obj-$(CONFIG_RESET_RZG2L_USBPHY_CTRL) +=3D reset-rzg2l-usbphy-ctrl.o obj-$(CONFIG_RESET_SCMI) +=3D reset-scmi.o obj-$(CONFIG_RESET_SIMPLE) +=3D reset-simple.o +obj-$(CONFIG_RESET_SIMPLE_SYSCON) +=3D reset-simple-syscon.o obj-$(CONFIG_RESET_SOCFPGA) +=3D reset-socfpga.o obj-$(CONFIG_RESET_SUNPLUS) +=3D reset-sunplus.o obj-$(CONFIG_RESET_SUNXI) +=3D reset-sunxi.o diff --git a/drivers/reset/reset-simple-syscon.c b/drivers/reset/reset-simp= le-syscon.c new file mode 100644 index 000000000000..798467f29911 --- /dev/null +++ b/drivers/reset/reset-simple-syscon.c @@ -0,0 +1,188 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Simple SYSCON Reset Controller Driver + * + * Copyright (C) 2025 Marvell, Wilson Ding + * + * Based on Simple Reset Controller Driver + * + * Copyright (C) 2017 Pengutronix, Philipp Zabel + * Copyright 2013 Maxime Ripard + * + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +static inline struct reset_simple_data * +to_reset_simple_data(struct reset_controller_dev *rcdev) +{ + return container_of(rcdev, struct reset_simple_data, rcdev); +} + +static int reset_simple_syscon_update(struct reset_controller_dev *rcdev, + unsigned long id, bool assert) +{ + struct reset_simple_data *data =3D to_reset_simple_data(rcdev); + int reg_width =3D sizeof(u32); + int bank =3D id / (reg_width * BITS_PER_BYTE); + int offset =3D id % (reg_width * BITS_PER_BYTE); + u32 mask, val; + + mask =3D BIT(offset); + + if (assert ^ data->active_low) + val =3D mask; + else + val =3D 0; + + return regmap_write_bits(data->regmap, + data->reg_offset + (bank * reg_width), + mask, val); +} + +static int reset_simple_syscon_assert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return reset_simple_syscon_update(rcdev, id, true); +} + +static int reset_simple_syscon_deassert(struct reset_controller_dev *rcdev, + unsigned long id) +{ + return reset_simple_syscon_update(rcdev, id, false); +} + +static int reset_simple_syscon_reset(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct reset_simple_data *data =3D to_reset_simple_data(rcdev); + int ret; + + if (!data->reset_us) + return -EINVAL; + + ret =3D reset_simple_syscon_assert(rcdev, id); + if (ret) + return ret; + + usleep_range(data->reset_us, data->reset_us * 2); + + return reset_simple_syscon_deassert(rcdev, id); +} + +static int reset_simple_syscon_status(struct reset_controller_dev *rcdev, + unsigned long id) +{ + struct reset_simple_data *data =3D to_reset_simple_data(rcdev); + int reg_width =3D sizeof(u32); + int bank =3D id / (reg_width * BITS_PER_BYTE); + int offset =3D id % (reg_width * BITS_PER_BYTE); + u32 reg; + int ret; + + ret =3D regmap_read(data->regmap, data->reg_offset + (bank * reg_width), + ®); + if (ret) + return ret; + + return !(reg & BIT(offset)) ^ !data->status_active_low; +} + +const struct reset_control_ops reset_simple_syscon_ops =3D { + .assert =3D reset_simple_syscon_assert, + .deassert =3D reset_simple_syscon_deassert, + .reset =3D reset_simple_syscon_reset, + .status =3D reset_simple_syscon_status, +}; +EXPORT_SYMBOL_GPL(reset_simple_syscon_ops); + +/** + * struct reset_simple_syscon_devdata - simple reset controller properties + * @reg_offset: offset between base address and first reset register. + * @nr_resets: number of resets. If not set, default to resource size in b= its. + * @active_low: if true, bits are cleared to assert the reset. Otherwise, = bits + * are set to assert the reset. + * @status_active_low: if true, bits read back as cleared while the reset = is + * asserted. Otherwise, bits read back as set while the + * reset is asserted. + */ +struct reset_simple_syscon_devdata { + u32 reg_offset; + u32 nr_resets; + bool active_low; + bool status_active_low; +}; + +static const +struct reset_simple_syscon_devdata reset_simple_syscon_active_low =3D { + .active_low =3D true, + .status_active_low =3D true, +}; + +static const struct of_device_id reset_simple_syscon_dt_ids[] =3D { + { .compatible =3D "marvell,armada8k-reset", + .data =3D &reset_simple_syscon_active_low }, + { /* sentinel */ }, +}; + +static int reset_simple_syscon_probe(struct platform_device *pdev) +{ + struct device *dev =3D &pdev->dev; + const struct reset_simple_syscon_devdata *devdata; + struct reset_simple_data *data; + u32 reg[2]; + + devdata =3D of_device_get_match_data(dev); + + data =3D devm_kzalloc(dev, sizeof(*data), GFP_KERNEL); + if (!data) + return -ENOMEM; + + data->regmap =3D syscon_node_to_regmap(pdev->dev.parent->of_node); + if (IS_ERR(data->regmap)) + return PTR_ERR(data->regmap); + + /* + * If the "reg" property is available, retrieve the reg_offset + * and calculate the nr_resets based on the register size. + */ + if (!device_property_read_u32_array(&pdev->dev, "reg", reg, 2)) { + data->reg_offset =3D reg[0]; + data->rcdev.nr_resets =3D reg[1] * BITS_PER_BYTE; + } + + spin_lock_init(&data->lock); + data->rcdev.owner =3D THIS_MODULE; + data->rcdev.ops =3D &reset_simple_syscon_ops; + data->rcdev.of_node =3D dev->of_node; + + if (devdata) { + if (devdata->reg_offset) + data->reg_offset =3D devdata->reg_offset; + if (devdata->nr_resets) + data->rcdev.nr_resets =3D devdata->nr_resets; + data->active_low =3D devdata->active_low; + data->status_active_low =3D devdata->status_active_low; + } + + return devm_reset_controller_register(dev, &data->rcdev); +} + +static struct platform_driver reset_simple_syscon_driver =3D { + .probe =3D reset_simple_syscon_probe, + .driver =3D { + .name =3D "simple-reset-syscon", + .of_match_table =3D reset_simple_syscon_dt_ids, + }, +}; +builtin_platform_driver(reset_simple_syscon_driver); diff --git a/include/linux/reset/reset-simple.h b/include/linux/reset/reset= -simple.h index c3e44f45b0f7..9a8eebd5892f 100644 --- a/include/linux/reset/reset-simple.h +++ b/include/linux/reset/reset-simple.h @@ -13,6 +13,7 @@ #define __RESET_SIMPLE_H__ =20 #include +#include #include #include =20 @@ -37,6 +38,8 @@ struct reset_simple_data { spinlock_t lock; void __iomem *membase; + struct regmap *regmap; + u32 reg_offset; struct reset_controller_dev rcdev; bool active_low; bool status_active_low; --=20 2.43.0 From nobody Thu Mar 13 22:49:01 2025 Received: from mx0a-0016f401.pphosted.com (mx0a-0016f401.pphosted.com [67.231.148.174]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 3FC9826E958; Thu, 27 Feb 2025 19:26:00 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=67.231.148.174 ARC-Seal: i=1; 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Thu, 27 Feb 2025 11:25:40 -0800 (PST) Received: from DC5-EXCH05.marvell.com (10.69.176.209) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.1544.4; Thu, 27 Feb 2025 11:25:38 -0800 Received: from maili.marvell.com (10.69.176.80) by DC5-EXCH05.marvell.com (10.69.176.209) with Microsoft SMTP Server id 15.2.1544.4 via Frontend Transport; Thu, 27 Feb 2025 11:25:38 -0800 Received: from wd-ubuntu-24-04.marvell.com (wd-ubuntu-24-04.marvell.com [10.111.132.113]) by maili.marvell.com (Postfix) with ESMTP id 786455B6927; Thu, 27 Feb 2025 11:25:38 -0800 (PST) From: Wilson Ding To: , , CC: , , , , , , , , , Wilson Ding Subject: [PATCH v3 3/3] arm64: dts: marvell: cp11x: Add reset controller node Date: Thu, 27 Feb 2025 11:25:36 -0800 Message-ID: <20250227192536.2426490-4-dingwei@marvell.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20250227192536.2426490-1-dingwei@marvell.com> References: <20250227192536.2426490-1-dingwei@marvell.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable X-Proofpoint-ORIG-GUID: F9GJO5NrJ5WTW0ERHCE9qRfpK7xQkZIZ X-Authority-Analysis: v=2.4 cv=UIYnHDfy c=1 sm=1 tr=0 ts=67c0bc34 cx=c_pps a=rEv8fa4AjpPjGxpoe8rlIQ==:117 a=rEv8fa4AjpPjGxpoe8rlIQ==:17 a=T2h4t0Lz3GQA:10 a=M5GUcnROAAAA:8 a=DYY7cqjbEommNVqY-hUA:9 a=cX4pScRg4-JUD0_czzmr:22 a=OBjm3rFKGHvpk9ecZwUJ:22 X-Proofpoint-GUID: F9GJO5NrJ5WTW0ERHCE9qRfpK7xQkZIZ X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1057,Hydra:6.0.680,FMLib:17.12.68.34 definitions=2025-02-27_07,2025-02-27_01,2024-11-22_01 Content-Type: text/plain; charset="utf-8" Add the reset controller node as a sub-node to the system controller node. Signed-off-by: Wilson Ding --- arch/arm64/boot/dts/marvell/armada-cp11x.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi b/arch/arm64/boo= t/dts/marvell/armada-cp11x.dtsi index 161beec0b6b0..c27058d1534e 100644 --- a/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi +++ b/arch/arm64/boot/dts/marvell/armada-cp11x.dtsi @@ -226,6 +226,8 @@ CP11X_LABEL(rtc): rtc@284000 { CP11X_LABEL(syscon0): system-controller@440000 { compatible =3D "syscon", "simple-mfd"; reg =3D <0x440000 0x2000>; + #address-cells =3D <1>; + #size-cells =3D <1>; =20 CP11X_LABEL(clk): clock { compatible =3D "marvell,cp110-clock"; @@ -273,6 +275,12 @@ CP11X_LABEL(gpio2): gpio@140 { <&CP11X_LABEL(clk) 1 17>; status =3D "disabled"; }; + + CP11X_LABEL(swrst): reset-controller@268 { + compatible =3D "marvell,armada8k-reset"; + reg =3D <0x268 0x4>; + #reset-cells =3D <1>; + }; }; =20 CP11X_LABEL(syscon1): system-controller@400000 { --=20 2.43.0